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project_6/cccl_upstream/cudax/test/coop/reduce/this_grid.cu
EngineX CI 56fd68e7dd [INFRA] Import NVIDIA/CCCL upstream as optimization reference library
CCCL (CUDA C++ Core Libraries) provides:
- CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk)
- Thrust: high-level parallel algorithms (transform_reduce, sort, scan)
- libcudacxx: CUDA C++ standard library (atomics, barriers, memory)
- cudax: experimental features (memory resources, allocators)
- Tuning policies: per-SM hardware-specific algorithm parameters

Competition optimization vectors mapped to CCCL:
- Output TPS (83% weight): warp_reduce, block_reduce, device_topk
- Input TPS (14% weight): device_scan, block_load, prefetch
- Cache TPS (3% weight): prefix caching strategy patterns
- Memory (0.9 util): pooled/cached/buddy allocators

Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only)
License: Apache-2.0
2026-07-30 09:35:51 +00:00

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//===----------------------------------------------------------------------===//
//
// Part of CUDA Experimental in CUDA C++ Core Libraries,
// under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
//
//===----------------------------------------------------------------------===//
#include <cuda/devices>
#include <cuda/functional>
#include <cuda/hierarchy>
#include <cuda/launch>
#include <cuda/std/algorithm>
#include <cuda/std/type_traits>
#include <cuda/stream>
#include <cuda/experimental/coop.cuh>
#include <cuda/experimental/group.cuh>
#include <testing.cuh>
#include <c2h/catch2_test_helper.h>
#include <c2h/extended_types.h>
#include <c2h/generators.h>
#include <catch2/matchers/catch_matchers_floating_point.hpp>
constexpr int cluster_size = 2;
constexpr int block_size = 128;
/***********************************************************************************************************************
* Thread Reduce Wrapper Kernels
**********************************************************************************************************************/
template <bool Broadcasted>
struct ReduceKernel
{
template <class Config, int NumItems, class T, class RedOp>
__device__ void operator()(
Config config,
cuda::std::integral_constant<int, NumItems>,
const T* __restrict__ d_in,
T* __restrict__ d_out,
RedOp red_op)
{
cudax::this_grid grid{config};
T thread_data[NumItems];
for (int i = 0; i < NumItems; ++i)
{
thread_data[i] = d_in[cuda::gpu_thread.rank_as<int>(grid) + i * cuda::gpu_thread.count_as<int>(grid)];
}
if constexpr (Broadcasted)
{
const auto result = cudax::coop::reduce(cudax::broadcasted, grid, thread_data, red_op);
d_out[cuda::gpu_thread.rank(grid)] = result;
}
else
{
const auto result = cudax::coop::reduce(grid, thread_data, red_op);
REQUIRE(result.has_value() == cuda::gpu_thread.is_root_rank(grid));
if (cuda::gpu_thread.is_root_rank(grid))
{
*d_out = result.value();
}
}
}
};
/***********************************************************************************************************************
* Type list definition
**********************************************************************************************************************/
using integral_type_list =
c2h::type_list<cuda::std::int8_t, cuda::std::int16_t, cuda::std::uint16_t, cuda::std::int32_t, cuda::std::int64_t>;
using fp_type_list = c2h::type_list<float, double>;
using operator_integral_list =
c2h::type_list<cuda::std::plus<>,
cuda::std::multiplies<>,
cuda::std::bit_and<>,
cuda::std::bit_or<>,
cuda::std::bit_xor<>,
cuda::minimum<>,
cuda::maximum<>>;
using operator_fp_list = c2h::type_list<cuda::std::plus<>, cuda::std::multiplies<>, cuda::minimum<>, cuda::maximum<>>;
using grid_size_list = c2h::enum_type_list<int, 1, 12, 32>;
/***********************************************************************************************************************
* Verify results and kernel launch`
**********************************************************************************************************************/
template <class T>
void verify_results(const T& expected_data, const T& test_results)
{
if constexpr (cuda::std::is_floating_point_v<T>)
{
REQUIRE_THAT(expected_data, Catch::Matchers::WithinRel(test_results, T{0.05}));
}
else
{
REQUIRE(expected_data == test_results);
}
}
template <int GridSize, class T, class RedOp, bool Broadcasted = false>
void run_reduce_kernel(
cuda::stream_ref stream,
cuda::std::integral_constant<int, GridSize>,
int num_items,
const c2h::device_vector<T>& in,
c2h::device_vector<T>& out,
RedOp red_op,
cuda::std::bool_constant<Broadcasted> = {})
{
const auto config = cuda::make_config(
cuda::grid_dims<GridSize>(),
cuda::cluster_dims<cluster_size>(),
cuda::block_dims<block_size>(),
cuda::cooperative_launch{});
const auto in_ptr = thrust::raw_pointer_cast(in.data());
const auto out_ptr = thrust::raw_pointer_cast(out.data());
const ReduceKernel<Broadcasted> kernel{};
switch (num_items)
{
case 1:
cuda::launch(stream, config, kernel, cuda::std::integral_constant<int, 1>{}, in_ptr, out_ptr, red_op);
break;
case 4:
cuda::launch(stream, config, kernel, cuda::std::integral_constant<int, 4>{}, in_ptr, out_ptr, red_op);
break;
default:
FAIL("Unsupported number of items");
}
stream.sync();
}
constexpr int max_size = 4;
constexpr int num_seeds = 10;
/***********************************************************************************************************************
* Test cases
**********************************************************************************************************************/
_CCCL_DIAG_SUPPRESS_MSVC(4244) // warning C4244: '=': conversion from 'int' to '_Tp', possible loss of data
C2H_TEST("reduce/this_grid Integral Type Tests",
"[reduce][this_grid]",
integral_type_list,
operator_integral_list,
grid_size_list)
{
const auto device = cuda::devices[0];
if (cuda::device_attributes::compute_capability_major(device) < 9)
{
return;
}
using value_t = c2h::get<0, TestType>;
using op_t = c2h::get<1, TestType>;
using grid_size_t = c2h::get<2, TestType>;
constexpr auto reduce_op = op_t{};
constexpr auto operator_identity = cuda::identity_element<op_t, value_t>();
CAPTURE(c2h::type_name<value_t>(), max_size, c2h::type_name<decltype(reduce_op)>());
c2h::device_vector<value_t> d_in(max_size * grid_size_t::value * cluster_size * block_size);
c2h::device_vector<value_t> d_out(1);
c2h::gen(C2H_SEED(num_seeds), d_in, cuda::std::numeric_limits<value_t>::min());
c2h::host_vector<value_t> h_in = d_in;
cuda::stream stream{device};
for (int num_items : {1, 4})
{
auto reference_result = cuda::std::accumulate(
h_in.begin(),
h_in.begin() + num_items * grid_size_t::value * cluster_size * block_size,
operator_identity,
reduce_op);
run_reduce_kernel(stream, grid_size_t{}, num_items, d_in, d_out, reduce_op);
verify_results(reference_result, c2h::host_vector<value_t>(d_out)[0]);
}
}
C2H_TEST(
"reduce/this_grid Floating-Point Type Tests", "[reduce][this_grid]", fp_type_list, operator_fp_list, grid_size_list)
{
const auto device = cuda::devices[0];
if (cuda::device_attributes::compute_capability_major(device) < 9)
{
return;
}
using value_t = c2h::get<0, TestType>;
using op_t = c2h::get<1, TestType>;
using grid_size_t = c2h::get<2, TestType>;
constexpr auto reduce_op = op_t{};
const auto operator_identity = cuda::identity_element<op_t, value_t>();
CAPTURE(c2h::type_name<value_t>(), max_size, c2h::type_name<decltype(reduce_op)>());
c2h::device_vector<value_t> d_in(max_size * grid_size_t::value * cluster_size * block_size);
c2h::device_vector<value_t> d_out(1);
c2h::gen(C2H_SEED(num_seeds), d_in, cuda::std::numeric_limits<value_t>::min());
c2h::host_vector<value_t> h_in = d_in;
cuda::stream stream{device};
for (int num_items : {1, 4})
{
auto reference_result = cuda::std::accumulate(
h_in.begin(),
h_in.begin() + num_items * grid_size_t::value * cluster_size * block_size,
operator_identity,
reduce_op);
run_reduce_kernel(stream, grid_size_t{}, num_items, d_in, d_out, reduce_op);
verify_results(reference_result, c2h::host_vector<value_t>(d_out)[0]);
}
}
C2H_TEST("reduce/this_grid Broadcasted", "[reduce][this_grid]", integral_type_list, grid_size_list)
{
const auto device = cuda::devices[0];
if (cuda::device_attributes::compute_capability_major(device) < 9)
{
return;
}
using value_t = c2h::get<0, TestType>;
using op_t = cuda::std::plus<>;
using grid_size_t = c2h::get<1, TestType>;
constexpr auto reduce_op = op_t{};
constexpr auto operator_identity = cuda::identity_element<op_t, value_t>();
CAPTURE(c2h::type_name<value_t>(), max_size, c2h::type_name<decltype(reduce_op)>());
c2h::device_vector<value_t> d_in(max_size * grid_size_t::value * cluster_size * block_size);
c2h::gen(C2H_SEED(num_seeds), d_in, cuda::std::numeric_limits<value_t>::min());
c2h::host_vector<value_t> h_in = d_in;
cuda::stream stream{device};
for (int num_items : {1, 4})
{
c2h::device_vector<value_t> d_out(grid_size_t::value * cluster_size * block_size);
auto reference_result = cuda::std::accumulate(
h_in.begin(),
h_in.begin() + num_items * grid_size_t::value * cluster_size * block_size,
operator_identity,
reduce_op);
run_reduce_kernel(stream, grid_size_t{}, num_items, d_in, d_out, reduce_op, cuda::std::true_type{});
verify_results(c2h::host_vector<value_t>(grid_size_t::value * cluster_size * block_size, reference_result),
c2h::host_vector<value_t>(d_out));
}
}