56fd68e7dd
CCCL (CUDA C++ Core Libraries) provides: - CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk) - Thrust: high-level parallel algorithms (transform_reduce, sort, scan) - libcudacxx: CUDA C++ standard library (atomics, barriers, memory) - cudax: experimental features (memory resources, allocators) - Tuning policies: per-SM hardware-specific algorithm parameters Competition optimization vectors mapped to CCCL: - Output TPS (83% weight): warp_reduce, block_reduce, device_topk - Input TPS (14% weight): device_scan, block_load, prefetch - Cache TPS (3% weight): prefix caching strategy patterns - Memory (0.9 util): pooled/cached/buddy allocators Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only) License: Apache-2.0
119 lines
3.2 KiB
Plaintext
119 lines
3.2 KiB
Plaintext
//===----------------------------------------------------------------------===//
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//
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// Part of CUDASTF in CUDA C++ Core Libraries,
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// under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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// SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES.
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//
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//===----------------------------------------------------------------------===//
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/**
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* @file
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* @brief Toy example to reproduce the asynchrony of a 1F1B pipeline
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*/
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#include <cuda/experimental/stf.cuh>
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using namespace cuda::experimental::stf;
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__global__ void forward(slice<int>, long long int clock_cnt)
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{
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long long int start_clock = clock64();
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long long int clock_offset = 0;
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while (clock_offset < clock_cnt)
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{
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clock_offset = clock64() - start_clock;
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}
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}
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__global__ void backward(slice<int>, long long int clock_cnt)
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{
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long long int start_clock = clock64();
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long long int clock_offset = 0;
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while (clock_offset < clock_cnt)
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{
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clock_offset = clock64() - start_clock;
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}
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}
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int main(int argc, char** argv)
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{
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context ctx;
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// Use a graph context if the second argument is set and not null
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if (argc > 2 && atoi(argv[2]))
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{
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ctx = graph_ctx();
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}
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int device;
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cudaGetDevice(&device);
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// cudaDevAttrClockRate: Peak clock frequency in kilohertz;
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int clock_rate;
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cudaDeviceGetAttribute(&clock_rate, cudaDevAttrClockRate, device);
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auto occ_f = reserved::compute_occupancy(forward);
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auto occ_b = reserved::compute_occupancy(backward);
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int factor = 1;
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if (argc > 1)
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{
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factor = atoi(argv[1]);
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}
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size_t num_batches = 8 * factor;
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int num_devs = 8;
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int real_devs;
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cuda_safe_call(cudaGetDeviceCount(&real_devs));
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std::vector<logical_data<slice<int>>> data;
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for (size_t b = 0; b < num_batches; b++)
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{
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auto batch_data = ctx.logical_data(shape_of<slice<int>>(1024));
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data.push_back(batch_data);
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ctx.task(exec_place::device(0), data[b].write())->*[](cudaStream_t, auto) {
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// Init ...
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};
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}
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cuda_safe_call(cudaStreamSynchronize(ctx.fence()));
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size_t niter = 10;
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for (size_t iter = 0; iter < niter; iter++)
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{
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for (size_t b = 0; b < num_batches; b++)
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{
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for (int d = 0; d < num_devs; d++)
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{
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ctx.task(exec_place::device(d % real_devs), data[b].rw())->*[=](cudaStream_t s, auto bd) {
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int ms = 10;
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long long int clock_cnt = (long long int) (ms * clock_rate / factor);
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forward<<<occ_f.min_grid_size, occ_f.block_size, 0, s>>>(bd, clock_cnt);
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};
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}
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// }
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//
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// for (size_t b = 0; b < num_batches; b++) {
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for (int d = num_devs; d-- > 0;)
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{
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ctx.task(exec_place::device(d % real_devs), data[b].rw())->*[=](cudaStream_t s, auto bd) {
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int ms = 20;
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long long int clock_cnt = (long long int) (ms * clock_rate / factor);
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backward<<<occ_b.min_grid_size, occ_b.block_size, 0, s>>>(bd, clock_cnt);
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};
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}
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}
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/* We introduce a fence because the actual pipeline would introduce
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* some all to all communication to update coefficients */
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cuda_safe_call(cudaStreamSynchronize(ctx.fence()));
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}
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ctx.finalize();
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return 0;
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}
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