56fd68e7dd
CCCL (CUDA C++ Core Libraries) provides: - CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk) - Thrust: high-level parallel algorithms (transform_reduce, sort, scan) - libcudacxx: CUDA C++ standard library (atomics, barriers, memory) - cudax: experimental features (memory resources, allocators) - Tuning policies: per-SM hardware-specific algorithm parameters Competition optimization vectors mapped to CCCL: - Output TPS (83% weight): warp_reduce, block_reduce, device_topk - Input TPS (14% weight): device_scan, block_load, prefetch - Cache TPS (3% weight): prefix caching strategy patterns - Memory (0.9 util): pooled/cached/buddy allocators Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only) License: Apache-2.0
45 lines
1.8 KiB
Plaintext
45 lines
1.8 KiB
Plaintext
// SPDX-FileCopyrightText: Copyright (c) 2026, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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// This tunes the lookahead implementation of scan, which is only available on SM100+. It has entirely different tuning
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// parameters and is agnostic of the offset type. It is thus in a separate file, so we can continue to tune the old scan
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// implementation on older hardware architectures.
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#include <cuda/__cccl_config>
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#if _CCCL_PP_COUNT(__CUDA_ARCH_LIST__) != 1
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# warning "This benchmark does not support being compiled for multiple architectures. Disabling it."
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#else // _CCCL_PP_COUNT(__CUDA_ARCH_LIST__) != 1
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# if __CUDA_ARCH_LIST__ < 1000
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// We don't care if clang-tidy can't parse this
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# ifndef _CCCL_CLANG_TIDY_INVOKED
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# warning "Lookahead scan requires at least sm_100. Disabling it."
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# endif // !defined _CCCL_CLANG_TIDY_INVOKED
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# else // __CUDA_ARCH_LIST__ < 1000
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# if __cccl_ptx_isa < 860
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# warning "Lookahead scan requires at least PTX ISA 8.6. Disabling it."
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# else // if __cccl_ptx_isa < 860
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# include <nvbench_helper.cuh>
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// %RANGE% TUNE_NUM_REDUCE_SCAN_WARPS wrps 1:8:1
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// %RANGE% TUNE_NUM_LOOKBACK_ITEMS lbi 1:8:1
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// TODO(bgruber): find a good range and step width, items per thread should be coprime with 32 to avoid SMEM conflicts.
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// Should we specify nominal items per thread instead?
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// %RANGE% TUNE_ITEMS_PLUS_ONE ipt 8:256:8
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// %RANGE% TUNE_LOOKBACK_STAGES lbs -2:2:1
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// %RANGE% TUNE_BLOCK_IDX_STAGES bis -2:2:1
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# define USES_LOOKAHEAD() 1
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using op_t = ::cuda::std::plus<>;
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using scan_offset_types = nvbench::type_list<int64_t>;
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# include "base.cuh"
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# endif // __cccl_ptx_isa < 860
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# endif // __CUDA_ARCH_LIST__ < 1000
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#endif // _CCCL_PP_COUNT(__CUDA_ARCH_LIST__) != 1
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