56fd68e7dd
CCCL (CUDA C++ Core Libraries) provides: - CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk) - Thrust: high-level parallel algorithms (transform_reduce, sort, scan) - libcudacxx: CUDA C++ standard library (atomics, barriers, memory) - cudax: experimental features (memory resources, allocators) - Tuning policies: per-SM hardware-specific algorithm parameters Competition optimization vectors mapped to CCCL: - Output TPS (83% weight): warp_reduce, block_reduce, device_topk - Input TPS (14% weight): device_scan, block_load, prefetch - Cache TPS (3% weight): prefix caching strategy patterns - Memory (0.9 util): pooled/cached/buddy allocators Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only) License: Apache-2.0
78 lines
2.4 KiB
Plaintext
78 lines
2.4 KiB
Plaintext
// SPDX-FileCopyrightText: Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
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// SPDX-License-Identifier: BSD-3
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#include <cub/device/device_reduce.cuh>
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#include <cuda/execution.determinism.h>
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#include <cuda/execution.require.h>
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#include <cuda/std/utility>
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#include <nvbench_helper.cuh>
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#include <nvbench/range.cuh>
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#include <nvbench/types.cuh>
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// %RANGE% TUNE_ITEMS_PER_THREAD ipt 3:24:1
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// %RANGE% TUNE_THREADS_PER_BLOCK tpb 128:1024:32
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#if !TUNE_BASE
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struct policy_selector_t
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{
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[[nodiscard]] _CCCL_HOST_DEVICE constexpr auto operator()(cuda::compute_capability) const -> cub::ReducePolicy
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{
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const auto p = cub::ReducePassPolicy{
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TUNE_THREADS_PER_BLOCK, TUNE_ITEMS_PER_THREAD, 1, cub::BLOCK_REDUCE_RAKING, cub::LOAD_DEFAULT};
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return {p, p};
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}
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};
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#endif // !TUNE_BASE
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template <class T, class OffsetT>
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void deterministic_sum(nvbench::state& state, nvbench::type_list<T, OffsetT>)
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try
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{
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using init_value_t = T;
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if (!cuda::std::in_range<OffsetT>(state.get_int64("Elements{io}")))
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{
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state.skip("Skipping: Elements{io} is not representable by OffsetT.");
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return;
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}
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const auto elements = static_cast<OffsetT>(state.get_int64("Elements{io}"));
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thrust::device_vector<T> in = generate(elements);
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thrust::device_vector<T> out(1);
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const T* d_in = thrust::raw_pointer_cast(in.data());
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T* d_out = thrust::raw_pointer_cast(out.data());
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state.add_element_count(elements);
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state.add_global_memory_reads<T>(elements, "Size");
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state.add_global_memory_writes<T>(out.size());
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caching_allocator_t alloc;
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state.exec(nvbench::exec_tag::gpu | nvbench::exec_tag::no_batch, [&](nvbench::launch& launch) {
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auto env = cub_bench_env(
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alloc,
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launch,
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cuda::execution::require(cuda::execution::determinism::gpu_to_gpu)
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#if !TUNE_BASE
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,
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cuda::execution::tune(policy_selector_t{})
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#endif // !TUNE_BASE
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);
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_CCCL_TRY_CUDA_API(
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cub::DeviceReduce::Reduce, "Reduce failed", d_in, d_out, elements, cuda::std::plus<>{}, init_value_t{}, env);
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});
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}
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catch (const std::bad_alloc&)
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{
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state.skip("Skipping: out of memory.");
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}
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using types = nvbench::type_list<float, double>;
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NVBENCH_BENCH_TYPES(deterministic_sum, NVBENCH_TYPE_AXES(types, offset_types))
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.set_name("base")
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.set_type_axes_names({"T{ct}", "OffsetT{ct}"})
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// 2^32 exceeds INT32_MAX to cover the code paths for problem sizes that exceed a single 32-bit chunk
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.add_int64_power_of_two_axis("Elements{io}", {16, 20, 24, 28, 32});
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