56fd68e7dd
CCCL (CUDA C++ Core Libraries) provides: - CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk) - Thrust: high-level parallel algorithms (transform_reduce, sort, scan) - libcudacxx: CUDA C++ standard library (atomics, barriers, memory) - cudax: experimental features (memory resources, allocators) - Tuning policies: per-SM hardware-specific algorithm parameters Competition optimization vectors mapped to CCCL: - Output TPS (83% weight): warp_reduce, block_reduce, device_topk - Input TPS (14% weight): device_scan, block_load, prefetch - Cache TPS (3% weight): prefix caching strategy patterns - Memory (0.9 util): pooled/cached/buddy allocators Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only) License: Apache-2.0
96 lines
2.9 KiB
Plaintext
96 lines
2.9 KiB
Plaintext
// SPDX-FileCopyrightText: Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
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// SPDX-License-Identifier: BSD-3-Clause
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#include <cub/device/device_reduce.cuh>
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#include <cub/device/dispatch/tuning/tuning_reduce.cuh>
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#include <cuda/std/type_traits>
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#include <nvbench_helper.cuh>
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// %RANGE% TUNE_ITEMS_PER_THREAD ipt 7:24:1
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// %RANGE% TUNE_THREADS_PER_BLOCK tpb 128:1024:32
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// %RANGE% TUNE_ITEMS_PER_VEC_LOAD_POW2 ipv 1:2:1
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#if !TUNE_BASE
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struct tuned_policy_selector
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{
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[[nodiscard]] _CCCL_HOST_DEVICE constexpr auto operator()(cuda::compute_capability) const -> cub::ReducePolicy
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{
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cub::ReducePassPolicy rp{
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TUNE_THREADS_PER_BLOCK,
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TUNE_ITEMS_PER_THREAD,
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1 << TUNE_ITEMS_PER_VEC_LOAD_POW2,
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cub::BLOCK_REDUCE_WARP_REDUCTIONS,
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cub::LOAD_DEFAULT};
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return {rp, rp};
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}
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};
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#endif // !TUNE_BASE
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template <typename T, typename OpT>
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void arg_reduce(nvbench::state& state, nvbench::type_list<T, OpT>)
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{
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// Offset type used to index within the total input in the range [d_in, d_in + num_items)
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using offset_t = cuda::std::int64_t;
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// Retrieve axis parameters
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const auto elements = static_cast<std::size_t>(state.get_int64("Elements{io}"));
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thrust::device_vector<T> in = generate(elements);
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thrust::device_vector<offset_t> out_index(1);
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thrust::device_vector<T> out_extremum(1);
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const T* d_in = thrust::raw_pointer_cast(in.data());
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offset_t* d_out_index = thrust::raw_pointer_cast(out_index.data());
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T* d_out_extremum = thrust::raw_pointer_cast(out_extremum.data());
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// Enable throughput calculations and add "Size" column to results.
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state.add_element_count(elements);
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state.add_global_memory_reads<T>(elements, "Size");
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state.add_global_memory_writes<offset_t>(1);
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state.add_global_memory_writes<T>(1);
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caching_allocator_t alloc;
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state.exec(nvbench::exec_tag::gpu | nvbench::exec_tag::no_batch, [&](nvbench::launch& launch) {
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auto env = cub_bench_env(
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alloc,
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launch
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#if !TUNE_BASE
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,
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cuda::execution::tune(tuned_policy_selector{})
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#endif // !TUNE_BASE
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);
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if constexpr (cuda::std::is_same_v<OpT, cub::detail::arg_min>)
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{
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_CCCL_TRY_CUDA_API(
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cub::DeviceReduce::ArgMin,
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"ArgMin failed",
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d_in,
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d_out_extremum,
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d_out_index,
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static_cast<offset_t>(elements),
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cuda::std::less{},
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env);
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}
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else
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{
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_CCCL_TRY_CUDA_API(
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cub::DeviceReduce::ArgMax,
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"ArgMax failed",
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d_in,
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d_out_extremum,
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d_out_index,
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static_cast<offset_t>(elements),
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cuda::std::less{},
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env);
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}
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});
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}
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using op_types = nvbench::type_list<cub::detail::arg_min, cub::detail::arg_max>;
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NVBENCH_BENCH_TYPES(arg_reduce, NVBENCH_TYPE_AXES(fundamental_types, op_types))
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.set_name("base")
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.set_type_axes_names({"T{ct}", "Operation{ct}"})
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.add_int64_power_of_two_axis("Elements{io}", nvbench::range(16, 28, 4));
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