9b21a13119
Pipeline: 1. extract.py: Parses all 26 CCCL tuning_*.cuh → 26 YAML schemas in muh/schema/ 2. parse.py: .muh file parser with extends-inheritance + schema validation 3. gen_yaml.py: .muh → computility-run.yaml (verified: matches competition reference) 4. gen_patch.py: .muh → vllm kernel unified diff patches (6 algorithm mappings) 5. baseline.muh: Competition reference config, all tuning values pending BI-V100 benchmarks Schemas extracted: 26 algorithms, 8-19 params each, SM75/80/90/100 reference tunings Priority mapping: reduce→attention, topk→sampling, scan→paged_attention, transform→activations, batch_memcpy→KV_cache, for→RoPE Tested: extract→parse→validate→gen_yaml→gen_patch full pipeline passes
123 lines
3.5 KiB
Plaintext
123 lines
3.5 KiB
Plaintext
# baseline.muh — Competition reference configuration
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# Corresponds to: dev.modelhub.org.cn EngineX-Iluvatar/enginex-vllm-bi100-qwen36
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#
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# This is the starting point. All tuning values are pending BI-V100 benchmarks.
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# Child .muh files use 'extends: baseline.muh' to override specific algorithms.
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# --- Hardware description ---
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hardware:
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name: Iluvatar-BI-V100-50c-200G
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gpu_count: 4
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# These need to be confirmed on actual hardware:
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warp_size: 32
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max_threads_per_block: 1024
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max_shared_memory_per_block: 49152
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max_registers_per_thread: 255
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l2_cache_size_bytes: 6291456
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memory_bandwidth_gbps: 900
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compute_capability: iluvatar_bi100
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# --- vllm launch configuration ---
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# Maps directly to computility-run.yaml command
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vllm:
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model_path: /model
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served_model_name: llm
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max_model_len: 100000
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gpu_memory_utilization: 0.9
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tensor_parallel: 4
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max_num_seqs: 1
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max_num_batched_tokens: 8192
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max_seq_len_to_capture: 32768
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trust_remote_code: true
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disable_log_requests: true
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disable_frontend_multiprocessing: true
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enable_chunked_prefill: true
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enable_auto_tool_choice: true
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tool_call_parser: qwen3_coder
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reasoning_parser: qwen3
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enable_prefix_caching: true
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# --- Concurrency ---
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concurrency: 1
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# --- Environment ---
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env:
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VLLM_ENGINE_ITERATION_TIMEOUT_S: 3600
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# --- Tuning overrides (per CCCL algorithm) ---
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# Each key corresponds to a tuning_*.cuh schema in muh/schema/
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# Values are TBD until we run benchmarks on BI-V100
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#
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# Priority order (by competition score impact):
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# 1. reduce — attention reduction (Output TPS × 16.796)
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# 2. topk — sampling top-k/top-p (Output TPS × 16.796)
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# 3. scan — prefix scan in paged attention
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# 4. transform — activation kernels (SiLU, GELU)
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# 5. batch_memcpy — KV cache management (Cache TPS × 0.56)
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# 6. for — RoPE position encoding
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tuning:
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reduce:
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_priority: P0
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_vllm_impact: attention_reduction
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_score_weight: Output TPS × 16.796
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# CCCL SM90 reference: threads=128, items=24, vec_size=4
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# CCCL SM100 reference: threads varies by accum_size
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threads_per_block: null
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items_per_thread: null
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vec_size: null
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topk:
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_priority: P0
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_vllm_impact: sampling_decode
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_score_weight: Output TPS × 16.796
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# CCCL reference: threads=512, items=4, bits_per_pass=11
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threads_per_block: null
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items_per_thread: null
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bits_per_pass: null
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scan:
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_priority: P0
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_vllm_impact: paged_attention_prefix_scan
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_score_weight: Input TPS × 2.799
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# CCCL SM90 lookback: threads=128, items=24, delay=fixed(688, 1140) for float32
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# CCCL SM100 lookback: threads=384, items=22, delay=exponential_backon(1904, 830)
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# CCCL SM100 lookahead: warps=4, items=80-1, lookahead_items=3
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threads_per_block: null
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items_per_thread: null
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load_algorithm: null
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store_algorithm: null
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scan_algorithm: null
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transform:
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_priority: P1
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_vllm_impact: activation_elementwise
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_score_weight: Output TPS × 16.796
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threads_per_block: null
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items_per_thread: null
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batch_memcpy:
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_priority: P1
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_vllm_impact: kv_cache_copy
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_score_weight: Cache TPS × 0.56
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threads_per_block: null
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for:
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_priority: P2
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_vllm_impact: rope_position_encoding
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threads_per_block: null
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items_per_thread: null
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radix_sort:
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_priority: P2
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_vllm_impact: beam_search_token_sort
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threads_per_block: null
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items_per_thread: null
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radix_bits: null
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merge:
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_priority: P2
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_vllm_impact: sequence_merging
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threads_per_block: null
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items_per_thread: null
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