8d6f9eaeb0
从 cccl_upstream 递归追踪 cub/util_allocator.cuh 的全部 include 依赖: cub/ 9 files (config, util_*, version, detect_cuda_runtime) cuda/ libcudacxx type_traits, concepts, algorithm, iterator... nv/ target macros, preprocessor 总计 288 个头文件 (1.4MB)，打包到 include/ 目录，编译时 -I include 即可完全脱离 CCCL 原始目录结构。 .cu 文件直接 #include <cub/util_allocator.cuh>， 走原版 CUB CachingDeviceAllocator，零 mock。 BI-V100 参数: growth=2 bins=[8..32] max_cached=8GB/device
251 lines
8.0 KiB
Plaintext
251 lines
8.0 KiB
Plaintext
//===----------------------------------------------------------------------===//
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//
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// Part of libcu++, the C++ Standard Library for your entire system,
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// under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES.
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//
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//===----------------------------------------------------------------------===//
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// This header contains a preview of a portability system that enables
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// CUDA C++ development with NVC++, NVCC, and supported host compilers.
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// These interfaces are not guaranteed to be stable.
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#ifndef __NV_TARGET_H
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#define __NV_TARGET_H
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#if defined(__NVCC__) || defined(__CUDACC_RTC__)
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# define _NV_COMPILER_NVCC
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#elif defined(__NVCOMPILER) && __cplusplus >= 201103L
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# define _NV_COMPILER_NVCXX
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#elif defined(__clang__) && defined(__CUDA__) && defined(__CUDA_ARCH__)
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// clang compiling CUDA code, device mode.
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# define _NV_COMPILER_CLANG_CUDA
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#endif
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// Hide `if target` support from NVRTC and C
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// Some toolkit headers use <nv/target> in true C contexts
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#if !defined(__CUDACC_RTC__) && defined(__cplusplus)
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# if defined(_NV_COMPILER_NVCXX)
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# define _NV_BITSET_ATTRIBUTE [[nv::__target_bitset]]
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# else
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# define _NV_BITSET_ATTRIBUTE
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# endif
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// This must be a nested namespace as <nv/target> works with older dialects.
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namespace nv // NOLINT(modernize-concat-nested-namespaces)
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{
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namespace target // NOLINT(modernize-concat-nested-namespaces)
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{
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namespace detail
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{
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using base_int_t = unsigned long long;
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// No host specialization
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constexpr base_int_t all_hosts = 1;
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// NVIDIA GPUs
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constexpr base_int_t sm_35_bit = 1 << 1;
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constexpr base_int_t sm_37_bit = 1 << 2;
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constexpr base_int_t sm_50_bit = 1 << 3;
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constexpr base_int_t sm_52_bit = 1 << 4;
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constexpr base_int_t sm_53_bit = 1 << 5;
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constexpr base_int_t sm_60_bit = 1 << 6;
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constexpr base_int_t sm_61_bit = 1 << 7;
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constexpr base_int_t sm_62_bit = 1 << 8;
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constexpr base_int_t sm_70_bit = 1 << 9;
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constexpr base_int_t sm_72_bit = 1 << 10;
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constexpr base_int_t sm_75_bit = 1 << 11;
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constexpr base_int_t sm_80_bit = 1 << 12;
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constexpr base_int_t sm_86_bit = 1 << 13;
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constexpr base_int_t sm_87_bit = 1 << 14;
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constexpr base_int_t sm_88_bit = 1 << 15;
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constexpr base_int_t sm_89_bit = 1 << 16;
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constexpr base_int_t sm_90_bit = 1 << 17;
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constexpr base_int_t sm_100_bit = 1 << 18;
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constexpr base_int_t sm_103_bit = 1 << 19;
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constexpr base_int_t sm_107_bit = 1 << 20;
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constexpr base_int_t sm_110_bit = 1 << 21;
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constexpr base_int_t sm_120_bit = 1 << 22;
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constexpr base_int_t sm_121_bit = 1 << 23;
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constexpr base_int_t all_devices =
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sm_35_bit | sm_37_bit | sm_50_bit | sm_52_bit | sm_53_bit | sm_60_bit | sm_61_bit | sm_62_bit | sm_70_bit | sm_72_bit
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| sm_75_bit | sm_80_bit | sm_86_bit | sm_87_bit | sm_88_bit | sm_89_bit | sm_90_bit | sm_100_bit | sm_103_bit
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| sm_107_bit | sm_110_bit | sm_120_bit | sm_121_bit;
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// Store a set of targets as a set of bits
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struct _NV_BITSET_ATTRIBUTE target_description
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{
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base_int_t targets;
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constexpr target_description(base_int_t a)
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: targets(a)
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{}
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};
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// The type of the user-visible names of the NVIDIA GPU targets
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enum class sm_selector : base_int_t
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{
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sm_35 = 35,
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sm_37 = 37,
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sm_50 = 50,
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sm_52 = 52,
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sm_53 = 53,
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sm_60 = 60,
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sm_61 = 61,
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sm_62 = 62,
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sm_70 = 70,
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sm_72 = 72,
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sm_75 = 75,
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sm_80 = 80,
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sm_86 = 86,
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sm_87 = 87,
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sm_88 = 88,
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sm_89 = 89,
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sm_90 = 90,
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sm_100 = 100,
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sm_103 = 103,
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sm_107 = 107,
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sm_110 = 110,
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sm_120 = 120,
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sm_121 = 121,
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};
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constexpr base_int_t toint(sm_selector a)
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{
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return static_cast<base_int_t>(a);
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}
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constexpr base_int_t bitexact(sm_selector a)
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{
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return toint(a) == 35 ? sm_35_bit
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: toint(a) == 37 ? sm_37_bit
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: toint(a) == 50 ? sm_50_bit
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: toint(a) == 52 ? sm_52_bit
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: toint(a) == 53 ? sm_53_bit
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: toint(a) == 60 ? sm_60_bit
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: toint(a) == 61 ? sm_61_bit
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: toint(a) == 62 ? sm_62_bit
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: toint(a) == 70 ? sm_70_bit
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: toint(a) == 72 ? sm_72_bit
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: toint(a) == 75 ? sm_75_bit
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: toint(a) == 80 ? sm_80_bit
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: toint(a) == 86 ? sm_86_bit
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: toint(a) == 87 ? sm_87_bit
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: toint(a) == 88 ? sm_88_bit
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: toint(a) == 89 ? sm_89_bit
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: toint(a) == 90 ? sm_90_bit
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: toint(a) == 100 ? sm_100_bit
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: toint(a) == 103 ? sm_103_bit
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: toint(a) == 107 ? sm_107_bit
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: toint(a) == 110 ? sm_110_bit
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: toint(a) == 120 ? sm_120_bit
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: toint(a) == 121 ? sm_121_bit
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: 0;
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}
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constexpr base_int_t bitrounddown(sm_selector a)
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{
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return toint(a) >= 121 ? sm_121_bit
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: toint(a) >= 120 ? sm_120_bit
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: toint(a) >= 110 ? sm_110_bit
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: toint(a) >= 107 ? sm_107_bit
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: toint(a) >= 103 ? sm_103_bit
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: toint(a) >= 100 ? sm_100_bit
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: toint(a) >= 90 ? sm_90_bit
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: toint(a) >= 89 ? sm_89_bit
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: toint(a) >= 88 ? sm_88_bit
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: toint(a) >= 87 ? sm_87_bit
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: toint(a) >= 86 ? sm_86_bit
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: toint(a) >= 80 ? sm_80_bit
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: toint(a) >= 75 ? sm_75_bit
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: toint(a) >= 72 ? sm_72_bit
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: toint(a) >= 70 ? sm_70_bit
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: toint(a) >= 62 ? sm_62_bit
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: toint(a) >= 61 ? sm_61_bit
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: toint(a) >= 60 ? sm_60_bit
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: toint(a) >= 53 ? sm_53_bit
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: toint(a) >= 52 ? sm_52_bit
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: toint(a) >= 50 ? sm_50_bit
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: toint(a) >= 37 ? sm_37_bit
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: toint(a) >= 35 ? sm_35_bit
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: 0;
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}
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// Public API for NVIDIA GPUs
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constexpr target_description is_exactly(sm_selector a)
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{
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return target_description(bitexact(a));
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}
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constexpr target_description provides(sm_selector a)
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{
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return target_description(~(bitrounddown(a) - 1) & all_devices);
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}
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// Boolean operations on target sets
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constexpr target_description operator&&(target_description a, target_description b)
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{
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return target_description(a.targets & b.targets);
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}
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constexpr target_description operator||(target_description a, target_description b)
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{
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return target_description(a.targets | b.targets);
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}
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constexpr target_description operator!(target_description a)
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{
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return target_description(~a.targets & (all_devices | all_hosts));
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}
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} // namespace detail
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using detail::sm_selector;
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using detail::target_description;
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// The predicates for basic host/device selection
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constexpr target_description is_host = target_description(detail::all_hosts);
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constexpr target_description is_device = target_description(detail::all_devices);
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constexpr target_description any_target = target_description(detail::all_hosts | detail::all_devices);
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constexpr target_description no_target = target_description(0);
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// The public names for NVIDIA GPU architectures
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constexpr sm_selector sm_35 = sm_selector::sm_35;
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constexpr sm_selector sm_37 = sm_selector::sm_37;
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constexpr sm_selector sm_50 = sm_selector::sm_50;
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constexpr sm_selector sm_52 = sm_selector::sm_52;
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constexpr sm_selector sm_53 = sm_selector::sm_53;
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constexpr sm_selector sm_60 = sm_selector::sm_60;
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constexpr sm_selector sm_61 = sm_selector::sm_61;
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constexpr sm_selector sm_62 = sm_selector::sm_62;
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constexpr sm_selector sm_70 = sm_selector::sm_70;
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constexpr sm_selector sm_72 = sm_selector::sm_72;
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constexpr sm_selector sm_75 = sm_selector::sm_75;
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constexpr sm_selector sm_80 = sm_selector::sm_80;
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constexpr sm_selector sm_86 = sm_selector::sm_86;
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constexpr sm_selector sm_87 = sm_selector::sm_87;
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constexpr sm_selector sm_88 = sm_selector::sm_88;
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constexpr sm_selector sm_89 = sm_selector::sm_89;
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constexpr sm_selector sm_90 = sm_selector::sm_90;
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constexpr sm_selector sm_100 = sm_selector::sm_100;
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constexpr sm_selector sm_103 = sm_selector::sm_103;
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constexpr sm_selector sm_107 = sm_selector::sm_107;
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constexpr sm_selector sm_110 = sm_selector::sm_110;
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constexpr sm_selector sm_120 = sm_selector::sm_120;
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constexpr sm_selector sm_121 = sm_selector::sm_121;
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using detail::is_exactly;
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using detail::provides;
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} // namespace target
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} // namespace nv
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#endif // C++ && !defined(__CUDACC_RTC__)
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#include <nv/detail/__target_macros>
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#endif // __NV_TARGET_H
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