56fd68e7dd
CCCL (CUDA C++ Core Libraries) provides: - CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk) - Thrust: high-level parallel algorithms (transform_reduce, sort, scan) - libcudacxx: CUDA C++ standard library (atomics, barriers, memory) - cudax: experimental features (memory resources, allocators) - Tuning policies: per-SM hardware-specific algorithm parameters Competition optimization vectors mapped to CCCL: - Output TPS (83% weight): warp_reduce, block_reduce, device_topk - Input TPS (14% weight): device_scan, block_load, prefetch - Cache TPS (3% weight): prefix caching strategy patterns - Memory (0.9 util): pooled/cached/buddy allocators Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only) License: Apache-2.0
33 lines
948 B
Plaintext
33 lines
948 B
Plaintext
// SPDX-FileCopyrightText: Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved.
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// SPDX-License-Identifier: BSD-3
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#include "base.cuh"
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struct op_t
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{
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template <class PolicyT, class InputIterator1, class InputIterator2, class OutputIterator>
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__host__ OutputIterator operator()(
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const PolicyT& policy,
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InputIterator1 first1,
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InputIterator1 last1,
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InputIterator2 first2,
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InputIterator2 last2,
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OutputIterator result) const
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{
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return thrust::set_difference(policy, first1, last1, first2, last2, result);
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}
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};
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template <typename T>
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static void basic(nvbench::state& state, nvbench::type_list<T> tl)
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{
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basic(state, tl, op_t{});
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}
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NVBENCH_BENCH_TYPES(basic, NVBENCH_TYPE_AXES(types))
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.set_name("base")
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.set_type_axes_names({"T{ct}"})
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.add_int64_power_of_two_axis("Elements", nvbench::range(16, 28, 4))
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.add_string_axis("Entropy", {"1.000", "0.201"})
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.add_int64_axis("SizeRatio", {25, 50, 75});
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