CCCL (CUDA C++ Core Libraries) provides: - CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk) - Thrust: high-level parallel algorithms (transform_reduce, sort, scan) - libcudacxx: CUDA C++ standard library (atomics, barriers, memory) - cudax: experimental features (memory resources, allocators) - Tuning policies: per-SM hardware-specific algorithm parameters Competition optimization vectors mapped to CCCL: - Output TPS (83% weight): warp_reduce, block_reduce, device_topk - Input TPS (14% weight): device_scan, block_load, prefetch - Cache TPS (3% weight): prefix caching strategy patterns - Memory (0.9 util): pooled/cached/buddy allocators Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only) License: Apache-2.0
64 lines
2.7 KiB
C++
64 lines
2.7 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of libcu++, the C++ Standard Library for your entire system,
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// under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
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//
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//===----------------------------------------------------------------------===//
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#ifndef DETAIL_H
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#define DETAIL_H
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/// @file
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/// Supporting details for the image pipeline example: synthetic image
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/// generation and printing/output helpers. These are not part of the
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/// pipeline itself — in a real application, image generation would be
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/// replaced by actual data loading, and the printing would be replaced
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/// by your application's logging.
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#include <image_pipeline.h>
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// ── Image generation ─────────────────────────────────────────────────
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/// Generate a synthetic space observation on the GPU, tile by tile,
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/// and produce a downscaled input preview.
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/// In a real application this would be replaced by loading actual data.
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void generate_image(cuda::stream_ref stream, tile_buffers& bufs, int num_tiles, cuda::std::span<pixel_t> host_preview);
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// ── Printing / output helpers ────────────────────────────────────────
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void print_device_info(cuda::device_ref dev, cuda::arch_traits_t traits, size_t total_mem);
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void print_tile_plan(int tile_rows, int tile_alignment, int num_tiles, size_t budget, size_t total_mem);
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void print_allocation_info(size_t device_total, size_t gpu_budget, size_t tile_pixels, int tile_rows);
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void print_pool_stats(tile_buffers& bufs);
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struct iqr_result
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{
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int p25, p75;
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[[nodiscard]] int width() const noexcept
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{
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return p75 - p25;
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}
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};
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[[nodiscard]] iqr_result compute_iqr(cuda::std::span<const histogram_count_t> hist, size_t total);
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void print_pass_stats(double ms, long long total_selected, double mean_selected, float global_min, float global_max);
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void print_sanity_check(iqr_result orig, iqr_result eq);
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void print_summary(int num_tiles, int tile_rows, double pass1_ms, double pass2_ms, bool ok);
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[[nodiscard]] bool write_bmp(const char* filename, cuda::std::span<const pixel_t> data, int width, int height);
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/// Downscale a device tile using CUB BlockReduce and copy the result
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/// to the host preview buffer.
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void downscale_tile(
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cuda::stream_ref stream,
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tile_buffers& bufs,
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int slot,
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cuda::std::span<const pixel_t> dev_src,
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int row_offset,
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int tile_rows,
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cuda::std::span<pixel_t> host_preview);
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#endif // DETAIL_H
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