56fd68e7dd
CCCL (CUDA C++ Core Libraries) provides: - CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk) - Thrust: high-level parallel algorithms (transform_reduce, sort, scan) - libcudacxx: CUDA C++ standard library (atomics, barriers, memory) - cudax: experimental features (memory resources, allocators) - Tuning policies: per-SM hardware-specific algorithm parameters Competition optimization vectors mapped to CCCL: - Output TPS (83% weight): warp_reduce, block_reduce, device_topk - Input TPS (14% weight): device_scan, block_load, prefetch - Cache TPS (3% weight): prefix caching strategy patterns - Memory (0.9 util): pooled/cached/buddy allocators Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only) License: Apache-2.0
87 lines
2.7 KiB
Plaintext
87 lines
2.7 KiB
Plaintext
// SPDX-FileCopyrightText: Copyright (c) 2026, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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#include <cub/device/device_reduce.cuh>
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#include <thrust/detail/raw_pointer_cast.h>
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#include <thrust/device_vector.h>
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#include <cuda/argument>
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#include <cuda/std/functional>
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#include <nvbench_helper.cuh>
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#include <nvbench/range.cuh>
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#include <nvbench/types.cuh>
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// %RANGE% TUNE_ITEMS_PER_THREAD ipt 7:24:1
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// %RANGE% TUNE_THREADS_PER_BLOCK tpb 128:1024:32
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// %RANGE% TUNE_ITEMS_PER_VEC_LOAD_POW2 ipv 1:2:1
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#if !TUNE_BASE
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template <typename AccumT>
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struct policy_selector
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{
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[[nodiscard]] _CCCL_HOST_DEVICE constexpr auto operator()(cuda::compute_capability) const -> cub::ReducePolicy
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{
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const auto [items, threads] =
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cub::detail::scale_mem_bound(TUNE_THREADS_PER_BLOCK, TUNE_ITEMS_PER_THREAD, int{sizeof(AccumT)});
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const auto policy = cub::ReducePassPolicy{
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threads, items, 1 << TUNE_ITEMS_PER_VEC_LOAD_POW2, cub::BLOCK_REDUCE_WARP_REDUCTIONS, cub::LOAD_DEFAULT};
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return {policy, policy};
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}
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};
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#endif // !TUNE_BASE
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using op_t = cuda::std::plus<>;
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template <typename T, typename OffsetT>
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void reduce(nvbench::state& state, nvbench::type_list<T, OffsetT>)
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{
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using init_value_t = T;
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// Retrieve axis parameters
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const auto elements = state.get_int64("Elements{io}");
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thrust::device_vector<T> in = generate(elements);
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thrust::device_vector<T> out(1, thrust::default_init);
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thrust::device_vector<OffsetT> device_num_items(1, static_cast<OffsetT>(elements));
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auto d_in = thrust::raw_pointer_cast(in.data());
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auto d_out = thrust::raw_pointer_cast(out.data());
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auto d_num_items = thrust::raw_pointer_cast(device_num_items.data());
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// Enable throughput calculations and add "Size" column to results.
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state.add_element_count(elements);
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state.add_global_memory_reads<T>(elements, "Size");
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state.add_global_memory_writes<T>(1);
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caching_allocator_t alloc;
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state.exec(nvbench::exec_tag::gpu | nvbench::exec_tag::no_batch, [&](nvbench::launch& launch) {
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auto env = cub_bench_env(
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alloc,
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launch
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#if !TUNE_BASE
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,
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cuda::execution::tune(policy_selector<cuda::std::__accumulator_t<op_t, T, init_value_t>>{})
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#endif // !TUNE_BASE
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);
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_CCCL_TRY_CUDA_API(
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cub::DeviceReduce::Reduce,
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"Reduce failed",
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d_in,
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d_out,
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cuda::args::deferred{d_num_items},
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op_t{},
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init_value_t{},
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env);
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});
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}
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using value_types = all_types;
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NVBENCH_BENCH_TYPES(reduce, NVBENCH_TYPE_AXES(value_types, offset_types))
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.set_name("base")
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.set_type_axes_names({"T{ct}", "OffsetT{ct}"})
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.add_int64_power_of_two_axis("Elements{io}", nvbench::range(16, 28, 4));
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