project_6

Files

muh 0cfdb6ae5d [docs] CCCL ↔ EngineX architecture alignment — from reading 3792 CCCL source files

Documents the three-layer mapping between CCCL's device-level API
(dispatch/kernel/agent) and EngineX's actual execution surface
(precompiled .so + Triton JIT + Python runtime).

Key finding: EngineX has ZERO .cu source files. All CUDA kernels are
precompiled in 3 .so files. Our optimization surface is:
1. Python runtime params (paged_attn.py, _custom_ops.py)
2. Triton JIT kernels (flash_attention, rmsnorm, rope, splitk)
3. Server config (computility-run.yaml)

CCCL patterns applied:
- GridEvenShare (grid_even_share.cuh) → V1/V2 dispatch + tile sizing
- Compound reduce (summary_statistics.cu) → online softmax accumulator
- Two-phase reduce (kernel_reduce.cuh) → paged_attention_v2 partition/merge
- spread_out_items_per_thread (dispatch_transform.cuh) → Triton BLOCK_SIZE
- Lookback delay (tuning_scan.cuh) → no_delay optimal for 16 SMs

Source: read agent_reduce.cuh (425 lines), kernel_reduce.cuh (290 lines),
dispatch_reduce.cuh (530 lines), grid_even_share.cuh (180 lines),
dispatch_transform.cuh (250 lines), kernel_scan.cuh (175 lines),
tuning_reduce.cuh (478 lines), common.cuh (330 lines),
flash_attention.py (230 lines), rmsnorm_kernels.py (140 lines),
triton_splitk.py (739 lines), prefix_prefill.py (866 lines)

2026-08-06 06:02:40 +00:00

server_recon

docs: document Qwen3.6-35B-A3B bootstrap failure and architecture analysis

2026-08-01 13:16:01 +00:00

CCCL_BENCHMARK_REFERENCE.md

[DOCS] CCCL benchmark reference: 199 annotations from 27 tuning files extracted

2026-08-06 02:16:42 +00:00

CCCL_ENGINEX_ARCHITECTURE_ALIGNMENT.md

[docs] CCCL ↔ EngineX architecture alignment — from reading 3792 CCCL source files

2026-08-06 06:02:40 +00:00

CCCL_REDUCE_ARCHITECTURE_NOTES.md

[docs] GridEvenShare work distribution — BI-V100 attention reduce needs only 9 CTAs