9b21a13119
Pipeline: 1. extract.py: Parses all 26 CCCL tuning_*.cuh → 26 YAML schemas in muh/schema/ 2. parse.py: .muh file parser with extends-inheritance + schema validation 3. gen_yaml.py: .muh → computility-run.yaml (verified: matches competition reference) 4. gen_patch.py: .muh → vllm kernel unified diff patches (6 algorithm mappings) 5. baseline.muh: Competition reference config, all tuning values pending BI-V100 benchmarks Schemas extracted: 26 algorithms, 8-19 params each, SM75/80/90/100 reference tunings Priority mapping: reduce→attention, topk→sampling, scan→paged_attention, transform→activations, batch_memcpy→KV_cache, for→RoPE Tested: extract→parse→validate→gen_yaml→gen_patch full pipeline passes
68 lines
1.2 KiB
YAML
68 lines
1.2 KiB
YAML
# muh schema for batch_memcpy
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# Auto-extracted from cub/cub/device/dispatch/tuning/tuning_batch_memcpy.cuh
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# Generated by muh/extract.py
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algorithm: batch_memcpy
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source: cub/cub/device/dispatch/tuning/tuning_batch_memcpy.cuh
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parameters:
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threads_per_block:
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type: int
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range:
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- 32
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- 1024
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step: 32
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buffers_per_thread:
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type: int
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range:
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- 1
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- 1024
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step: 1
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note: unknown_range
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bytes_per_thread:
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type: int
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range:
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- 1
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- 1024
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step: 1
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note: unknown_range
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block_level_tile_size:
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type: int
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range:
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- 1
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- 1024
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step: 1
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note: unknown_range
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warp_level_threshold:
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type: int
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range:
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- 1
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- 1024
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step: 1
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note: unknown_range
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block_level_threshold:
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type: int
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range:
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- 1
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- 1024
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step: 1
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note: unknown_range
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buffer_lookback_delay:
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type: int
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range:
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- 1
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- 1024
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step: 1
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note: unknown_range
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block_lookback_delay:
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type: int
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range:
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- 1
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- 1024
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step: 1
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note: unknown_range
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bi_v100:
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status: pending_benchmark
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note: Run muh benchmark on Iluvatar BI-V100 to fill these values
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threads_per_block: TBD
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items_per_thread: TBD
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