9ca33cf4d5
Sources (all CUDA 10.2 compatible, no CUTLASS/Triton dependency): - leimao/CUDA-GEMM-Optimization: v00-v07, fp16 WMMA variant, double buffered - siboehm/SGEMM_CUDA: kernel 1-12, warp tiling + double buffering - wangzyon/NVIDIA_SGEMM_PRACTICE: kernel 1-7 - edtallison/sgemm-cuda: kernel 1-12 (reimplementation with notes) Key porting issue: ALL kernels hardcode WARPSIZE=32. BI-V100 has warp_size=64. Need to: 1. Replace all 32U / WARPSIZE constants with 64 2. Adjust warp subtile decomposition (WMITER, WNITER, WSUBM, WSUBN) 3. Adjust shared memory bank conflict avoidance (may have different bank count) 4. Test __shfl_down_sync with mask=0xFFFFFFFFFFFFFFFF (64-bit)
14 lines
581 B
Plaintext
14 lines
581 B
Plaintext
#pragma once
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#include "kernels/01_naive.cuh"
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#include "kernels/02_kernel_global_mem_coalesce.cuh"
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#include "kernels/03_kernel_shared_mem_blocking.cuh"
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#include "kernels/04_kernel_1D_blocktiling.cuh"
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#include "kernels/05_kernel_2D_blocktiling.cuh"
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#include "kernels/06_kernel_vectorize.cuh"
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#include "kernels/07_kernel_resolve_bank_conflicts.cuh"
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#include "kernels/08_kernel_bank_extra_col.cuh"
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#include "kernels/09_kernel_autotuned.cuh"
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#include "kernels/10_kernel_warptiling.cuh"
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#include "kernels/11_kernel_double_buffering.cuh"
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#include "kernels/12_kernel_double_buffering.cuh" |