9ca33cf4d5
Sources (all CUDA 10.2 compatible, no CUTLASS/Triton dependency): - leimao/CUDA-GEMM-Optimization: v00-v07, fp16 WMMA variant, double buffered - siboehm/SGEMM_CUDA: kernel 1-12, warp tiling + double buffering - wangzyon/NVIDIA_SGEMM_PRACTICE: kernel 1-7 - edtallison/sgemm-cuda: kernel 1-12 (reimplementation with notes) Key porting issue: ALL kernels hardcode WARPSIZE=32. BI-V100 has warp_size=64. Need to: 1. Replace all 32U / WARPSIZE constants with 64 2. Adjust warp subtile decomposition (WMITER, WNITER, WSUBM, WSUBN) 3. Adjust shared memory bank conflict avoidance (may have different bank count) 4. Test __shfl_down_sync with mask=0xFFFFFFFFFFFFFFFF (64-bit)
38 lines
1.4 KiB
Plaintext
38 lines
1.4 KiB
Plaintext
# pragma once
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#include <cstdio>
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#include <cstdlib>
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#include <cublas_v2.h>
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#include <cuda_runtime.h>
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/*
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Matrix sizes:
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MxK * KxN = MxN
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*/
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__global__ void sgemm_naive(
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int M, int N, int K, // sizes
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float alpha, const float *A, const float *B, float beta, float *C // pointers used to point to matrices
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) {
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// compute position in C that this thread is responsible for
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// "which block" * "width of block" to get to start of block + "which thread"
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const uint x = blockIdx.x * blockDim.x + threadIdx.x; // "which row?" (inverted from graphical intuition, confusingly)
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const uint y = blockIdx.y * blockDim.y + threadIdx.y; // "which column?"
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// if M or N are not multiples of 32, there will be "extra"/"remainder" threads on the last block in x/y.
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// we don't want those leftover threads to do anything (tile quantisation)
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if (x < M && y < N) {
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float tmp = 0.0;
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for (int i = 0; i < K; ++i) { // K is the size of the row in A, col in B i.e. the dot product
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// A: x * K gives the start of relevant row, i enumerates across the row (col by col)
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// B: y gives the relevant column, i * N enumerates down the column, (row by row)
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tmp += A[x * K + i] * B[i * N + y];
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}
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// C = alpha*(A@B) + beta*C
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// x * N takes to start of relevant row, y moves across to the relevant column
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C[x * N + y] = alpha * tmp + beta * C[x * N + y];
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}
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}
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