9ca33cf4d5
Sources (all CUDA 10.2 compatible, no CUTLASS/Triton dependency): - leimao/CUDA-GEMM-Optimization: v00-v07, fp16 WMMA variant, double buffered - siboehm/SGEMM_CUDA: kernel 1-12, warp tiling + double buffering - wangzyon/NVIDIA_SGEMM_PRACTICE: kernel 1-7 - edtallison/sgemm-cuda: kernel 1-12 (reimplementation with notes) Key porting issue: ALL kernels hardcode WARPSIZE=32. BI-V100 has warp_size=64. Need to: 1. Replace all 32U / WARPSIZE constants with 64 2. Adjust warp subtile decomposition (WMITER, WNITER, WSUBM, WSUBN) 3. Adjust shared memory bank conflict avoidance (may have different bank count) 4. Test __shfl_down_sync with mask=0xFFFFFFFFFFFFFFFF (64-bit)
45 lines
1.2 KiB
Plaintext
45 lines
1.2 KiB
Plaintext
#pragma once
|
||
|
||
#include <cuda_runtime.h>
|
||
#include <cublas_v2.h>
|
||
#include <stdio.h>
|
||
#include <stdlib.h>
|
||
|
||
template<const int BLOCK_SIZE>
|
||
__global__ void mysgemm_v2(int M, int N, int K, float alpha, float *A, float *B, float beta, float *C) {
|
||
int bx = blockIdx.x;
|
||
int by = blockIdx.y;
|
||
|
||
const int BM = BLOCK_SIZE;
|
||
const int BN = BLOCK_SIZE;
|
||
const int BK = BLOCK_SIZE;
|
||
|
||
int tx = threadIdx.x % BN;
|
||
int ty = threadIdx.x / BN;
|
||
|
||
// 申请共享内存空间
|
||
__shared__ float As[BM * BK];
|
||
__shared__ float Bs[BK * BN];
|
||
|
||
// 移动到当前block
|
||
A = &A[by * BM * K];
|
||
B = &B[bx * BN];
|
||
C = &C[by * BM * N + bx * BN];
|
||
|
||
float tmp = 0.;
|
||
for (int k = 0; k < K; k += BK) {
|
||
// 缓存A_tile和B_tile
|
||
As[ty * BK + tx] = A[ty * K + tx];
|
||
Bs[ty * BN + tx] = B[ty * N + tx];
|
||
// 同步所有线程缓存完成
|
||
__syncthreads();
|
||
A += BK;
|
||
B += BK * N;
|
||
for (int i = 0; i < BK; i++) {
|
||
tmp += As[ty * BK + i] * Bs[i * BN + tx];
|
||
}
|
||
// FMA计算需要读取缓存数据，在新一轮写入缓存前进行同步，确保所有线程计算完成
|
||
__syncthreads();
|
||
}
|
||
C[ty * N + tx] = alpha * tmp + beta * C[ty * N + tx];
|
||
} |