9ca33cf4d5
Sources (all CUDA 10.2 compatible, no CUTLASS/Triton dependency): - leimao/CUDA-GEMM-Optimization: v00-v07, fp16 WMMA variant, double buffered - siboehm/SGEMM_CUDA: kernel 1-12, warp tiling + double buffering - wangzyon/NVIDIA_SGEMM_PRACTICE: kernel 1-7 - edtallison/sgemm-cuda: kernel 1-12 (reimplementation with notes) Key porting issue: ALL kernels hardcode WARPSIZE=32. BI-V100 has warp_size=64. Need to: 1. Replace all 32U / WARPSIZE constants with 64 2. Adjust warp subtile decomposition (WMITER, WNITER, WSUBM, WSUBN) 3. Adjust shared memory bank conflict avoidance (may have different bank count) 4. Test __shfl_down_sync with mask=0xFFFFFFFFFFFFFFFF (64-bit)
19 lines
580 B
Plaintext
19 lines
580 B
Plaintext
#pragma once
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#include <cuda_runtime.h>
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#include <cublas_v2.h>
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#include <stdio.h>
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#include <stdlib.h>
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__global__ __launch_bounds__(1024) void
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mysgemm_v1(int M, int N, int K, float alpha, float *A, float *B, float beta, float *C) {
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int gx = blockIdx.x * blockDim.x + threadIdx.x; // 全局x
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int gy = blockIdx.y * blockDim.y + threadIdx.y; // 全局y
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float tmp = 0.;
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for (int i = 0; i < K; i++) {
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tmp += A[gy * K + i] * B[i * N + gx]; // 两次全局内存访问和一次FMA（累加乘）
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}
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C[gy * N + gx] = alpha * tmp + beta * C[gy * N + gx];
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} |