9ca33cf4d5
Sources (all CUDA 10.2 compatible, no CUTLASS/Triton dependency): - leimao/CUDA-GEMM-Optimization: v00-v07, fp16 WMMA variant, double buffered - siboehm/SGEMM_CUDA: kernel 1-12, warp tiling + double buffering - wangzyon/NVIDIA_SGEMM_PRACTICE: kernel 1-7 - edtallison/sgemm-cuda: kernel 1-12 (reimplementation with notes) Key porting issue: ALL kernels hardcode WARPSIZE=32. BI-V100 has warp_size=64. Need to: 1. Replace all 32U / WARPSIZE constants with 64 2. Adjust warp subtile decomposition (WMITER, WNITER, WSUBM, WSUBN) 3. Adjust shared memory bank conflict avoidance (may have different bank count) 4. Test __shfl_down_sync with mask=0xFFFFFFFFFFFFFFFF (64-bit)
13 lines
433 B
C++
13 lines
433 B
C++
#ifndef CUDA_GEMM_UTILS_HPP
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#define CUDA_GEMM_UTILS_HPP
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#include <cuda_runtime.h>
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#define CHECK_CUDA_ERROR(val) check_cuda((val), #val, __FILE__, __LINE__)
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void check_cuda(cudaError_t err, const char* const func, const char* const file,
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const int line);
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#define CHECK_LAST_CUDA_ERROR() check_cuda_last(__FILE__, __LINE__)
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void check_cuda_last(const char* const file, const int line);
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#endif // CUDA_GEMM_UTILS_HPP
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