project_6

Files

claude ec140f3605 docs: complete porting assessment — 5 repos, 2660 build targets, ivcore10 compatibility

cat'd every source:
  - CCCL c/parallel/src/reduce.cu: NVRTC JIT (cannot port directly)
  - CCCL c/parallel.v2/src/reduce.cu: hostjit/libnvcc (cannot port directly)
  - CUB block/warp headers: pure header-only (CAN compile with corex)
  - CUTLASS SM70 SIMT GEMM: CAN port (example 24 grouped_gemm)
  - FlashAttention: SM80 Tensor Core (cannot port), but layer_norm is SIMT
  - FLA: pure Triton (needs corex Triton verification)
  - xllm ILU: all already ported

Key finding: CCCL c/parallel depends on nvrtc JIT — must bypass with AOT compilation
using CUB header-only API + corex clang --cuda-gpu-arch=ivcore10

2026-08-14 08:17:25 +00:00

server_recon

docs: document Qwen3.6-35B-A3B bootstrap failure and architecture analysis

2026-08-01 13:16:01 +00:00

CCCL_BENCHMARK_REFERENCE.md

[DOCS] CCCL benchmark reference: 199 annotations from 27 tuning files extracted

2026-08-06 02:16:42 +00:00

CCCL_ENGINEX_ARCHITECTURE_ALIGNMENT.md

[docs] CCCL ↔ EngineX architecture alignment — from reading 3792 CCCL source files

2026-08-06 06:02:40 +00:00

CCCL_REDUCE_ARCHITECTURE_NOTES.md

[docs] GridEvenShare work distribution — BI-V100 attention reduce needs only 9 CTAs