/*************************************************************************************************** * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, are permitted * provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, this list of * conditions and the following disclaimer in the documentation and/or other materials * provided with the distribution. * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used * to endorse or promote products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * **************************************************************************************************/ /*************************************************************************************************** * Copyright (c) 2021 Iluvatar CoreX. All rights reserved. * Copyright Declaration: This software, including all of its code and documentation, * except for the third-party software it contains, is a copyrighted work of Shanghai Iluvatar CoreX * Semiconductor Co., Ltd. and its affiliates ("Iluvatar CoreX") in accordance with the PRC Copyright * Law and relevant international treaties, and all rights contained therein are enjoyed by Iluvatar * CoreX. No user of this software shall have any right, ownership or interest in this software and * any use of this software shall be in compliance with the terms and conditions of the End User * License Agreement. **************************************************************************************************/ /*! \file \brief Defines basic properties needed by CTA-level GEMMs assuming expectations about data layout of the global memory fragments, data types, and internal tile sizes. Partial specializations for threadblock::Mma operations targeting TensorOp instructions. */ #pragma once #include "cutlass/cutlass.h" #include "cutlass/array.h" #include "cutlass/numeric_types.h" #include "cutlass/matrix_shape.h" #include "cutlass/gemm/warp/mma.h" #include "cutlass/gemm/threadblock/mma_pipelined.h" #include "cutlass/gemm/threadblock/mma_singlestage.h" #include "cutlass/gemm/threadblock/mma_preload.h" #include "cutlass/arch/cache_operation.h" ///////////////////////////////////////////////////////////////////////////////////////////////// namespace cutlass { namespace gemm { namespace threadblock { ///////////////////////////////////////////////////////////////////////////////////////////////// /// Template defininng default matrix multiply operators inferred from threadblock tile size, /// global memory data layout, and target math instruction. template < /// Shape of threadblock-scoped matrix multiply operator typename Shape, /// Shape of warp-level matrix multiply operator typename WarpShape, /// Shape of one matrix production operation (concept: GemmShape) typename InstructionShape, /// Element data type of A operand typename ElementA, /// Layout of operand A typename LayoutA, /// Element data type of B operand typename ElementB, /// Layout of operand B typename LayoutB, /// Data type of accumulator typename ElementC, /// Layout of accumulator typename LayoutC, /// Indicates type of math operator (arch::OpClassSimt or arch::OpClassTensorOp) typename OperatorClass, /// Number of stages int Stages = 2, /// Operation performed by MMA typename Operator = cutlass::arch::OpMultiplyAdd, /// Store the accumulators in row major or column major. Row major is used /// when output layout is interleaved. bool AccumulatorsInRowMajor = false, /// Cache operation of operand A cutlass::arch::CacheOperation::Kind CacheOpA = cutlass::arch::CacheOperation::Global, /// Cache operation of operand B cutlass::arch::CacheOperation::Kind CacheOpB = cutlass::arch::CacheOperation::Global, /// per-element transformation for elements of A ComplexTransform TransformA = ComplexTransform::kNone, /// per-element transformation for elements of B ComplexTransform TransformB = ComplexTransform::kNone, bool IsComplex = false // (is_complex::value || is_complex::value) > struct DefaultMmaCore; ///////////////////////////////////////////////////////////////////////////////////////////////// } // namespace threadblock } // namespace gemm } // namespace cutlass