claude
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8d75652949
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feat: import CUDA kernels from xllm/CCCL/FLA upstream repos
Sources cloned and tree'd (no --depth):
- jd-opensource/xllm: ILU kernels, CUDA kernels, MoE kernels
- NVIDIA/cccl: CUB tuning/dispatch headers (block-level primitives)
- fla-org/flash-linear-attention: Triton GDN kernels
- NVIDIA/cutlass: grouped GEMM reference (read, not copied)
- Dao-AILab/flash-attention: attention kernel reference (SM80+, read only)
New CUDA kernels (from xllm, SM-agnostic, portable to BI-V100):
ex_engine/xllm_kernels/cuda/activation.cu (188 lines) — silu_and_mul, gelu
ex_engine/xllm_kernels/cuda/norm.cu (600 lines) — rms_norm, fused_add_rms_norm
ex_engine/xllm_kernels/cuda/rope.cu (258 lines) — rotary_embedding
ex_engine/xllm_kernels/cuda/block_copy.cu (209 lines) — copy_blocks, swap_blocks
ex_engine/xllm_kernels/cuda/reshape_paged_cache.cu (101 lines) — KV cache ops
ex_engine/xllm_kernels/cuda/headers/ (5 headers for compilation)
ILU bridge kernel sources (from xllm, verified SAME as upstream):
ex_engine/xllm_kernels/ilu/ (10 files, 925 lines total)
— activation.cpp, attention.cpp, fused_moe.cpp, group_gemm.cpp,
matmul.cpp, norm.cpp, rope.cpp, ilu_ops_api.h, ixformer.h, utils.h
FLA Triton GDN kernels (for GatedDeltaNet without SM90+ FlashQLA):
ex_engine/fla_kernels/gated_delta_rule/ (7 files, 2370 lines)
— chunk_fwd.py (428), chunk.py (487), wy_fast.py (409),
fused_recurrent.py (392), naive.py (161), gate.py (380)
CCCL sync (12 tuning + 14 dispatch headers updated from NVIDIA/cccl):
cccl_upstream/cub/cub/device/dispatch/tuning/ — 12 changed files synced
cccl_upstream/cub/cub/device/dispatch/ — 14 changed dispatch files synced
Compilation targets for real machine (ivcore10):
1. CUDA kernels: --cuda-gpu-arch=ivcore10 via corex clang/16
2. ILU bridges: torch.utils.cpp_extension linking ixformer .so
3. FLA kernels: Triton JIT (if Triton works on BI-V100)
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2026-08-14 07:48:52 +00:00 |
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EX Engine
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002f9879b2
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ref(upstream): FULL TREE — Deep-Spark xllm (1470) + ds_vllm csrc/models (703)
Replaces cherry-picked upstream_ref with complete source trees.
xllm/ — Iluvatar official C++ inference engine (15MB, 1470 files)
Complete: kernels → layers → models → runtime → scheduler → api
Excluded: .git, binary images, third_party submodule checkouts
ds_vllm/ — Iluvatar official vllm fork (8MB, 703 files)
Included: csrc/ (ALL CUDA kernels), fused_moe/, qwen3_5 model, _custom_ops
Excluded: tests, benchmarks, docs, examples (not needed for reference)
Critical call chains now fully traceable:
MoE: moe_topk_softmax_kernels.cuh → ixformer.h → fused_moe.cpp → layer
GDN: qwen3_gated_delta_net_base.cpp → qwen3_5_gated_delta_net.cpp
Attention: ixformer.h → xllm_paged_attention → attention.cpp
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2026-08-10 02:54:03 +00:00 |
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EX Engine
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ea82b00e54
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ref(upstream): add Deep-Spark xllm + vllm MoE/GDN reference code
Sources (Apache 2.0, cloned 2026-08-09):
- Deep-Spark/xllm: Iluvatar's official C++ inference engine
- Deep-Spark/vllm: Iluvatar's vllm fork
Key files for our EX Engine development:
MoE topk_softmax (fixes 2304 calls/token PyTorch fallback):
- xllm/kernels/cuda/moe/moe_topk_softmax_kernels.cuh
CUB-based fused softmax+topk, power-of-2 expert count optimized
For 64 experts: topk_gating_softmax<T,VPT=2,64,WARPS=4,BYTES=4>
- xllm/kernels/ilu/ixformer.h
Official ixformer C++ API: topk_softmax(), paged_attention(), etc.
- xllm/kernels/ilu/fused_moe.cpp
How xllm calls ixformer::infer::topk_softmax()
- ds_vllm/csrc/moe/topk_softmax_kernels.cu
vllm-native topk_softmax (TensorRT-LLM derived, 874 lines)
GatedDeltaNet (fixes NaN in 4 GDN layers):
- xllm/layers/npu_torch/qwen3_gated_delta_net_base.cpp
fp32 state accumulation, proper recurrent update
Complete FusedMoE pipeline reference:
- xllm/layers/ilu/fused_moe.cpp
gate -> topk -> expand -> gemm1 -> act -> gemm2 -> combine
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2026-08-10 02:48:23 +00:00 |
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