claude
3a2cfc87c9
test: xllm CUDA kernel verification suite for BI-V100
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test_xllm_cuda_kernels.py — 7 test groups:
1. activation.cu: silu_and_mul via ixf_F, compare vs torch.nn.functional.silu
2. norm.cu: rms_norm + fused_add_rms_norm via ixf_F, compare vs PyTorch
3. rope.cu: rotary_embedding via ixf_F, verify rotation applied
4. moe_topk_softmax: corex .so, verify shapes + weights sum to 1
5. ix_moe_bridge: full 7-step fused MoE pipeline (topk→expand→gemm→act→gemm→combine)
6. ix_attn_bridge: load test (prefill_attention, decode_attention, linear)
7. ix_full_bridge: silu_and_mul + rms_norm through bridge .so
Revert: undo unnecessary cccl_upstream sync (already up to date)
Run on real machine: python3 qwen3_6_scripts/test_xllm_cuda_kernels.py
2026-08-14 08:01:23 +00:00
claude
8d75652949
feat: import CUDA kernels from xllm/CCCL/FLA upstream repos
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Sources cloned and tree'd (no --depth):
- jd-opensource/xllm: ILU kernels, CUDA kernels, MoE kernels
- NVIDIA/cccl: CUB tuning/dispatch headers (block-level primitives)
- fla-org/flash-linear-attention: Triton GDN kernels
- NVIDIA/cutlass: grouped GEMM reference (read, not copied)
- Dao-AILab/flash-attention: attention kernel reference (SM80+, read only)
New CUDA kernels (from xllm, SM-agnostic, portable to BI-V100):
ex_engine/xllm_kernels/cuda/activation.cu (188 lines) — silu_and_mul, gelu
ex_engine/xllm_kernels/cuda/norm.cu (600 lines) — rms_norm, fused_add_rms_norm
ex_engine/xllm_kernels/cuda/rope.cu (258 lines) — rotary_embedding
ex_engine/xllm_kernels/cuda/block_copy.cu (209 lines) — copy_blocks, swap_blocks
ex_engine/xllm_kernels/cuda/reshape_paged_cache.cu (101 lines) — KV cache ops
ex_engine/xllm_kernels/cuda/headers/ (5 headers for compilation)
ILU bridge kernel sources (from xllm, verified SAME as upstream):
ex_engine/xllm_kernels/ilu/ (10 files, 925 lines total)
— activation.cpp, attention.cpp, fused_moe.cpp, group_gemm.cpp,
matmul.cpp, norm.cpp, rope.cpp, ilu_ops_api.h, ixformer.h, utils.h
FLA Triton GDN kernels (for GatedDeltaNet without SM90+ FlashQLA):
ex_engine/fla_kernels/gated_delta_rule/ (7 files, 2370 lines)
— chunk_fwd.py (428), chunk.py (487), wy_fast.py (409),
fused_recurrent.py (392), naive.py (161), gate.py (380)
CCCL sync (12 tuning + 14 dispatch headers updated from NVIDIA/cccl):
cccl_upstream/cub/cub/device/dispatch/tuning/ — 12 changed files synced
cccl_upstream/cub/cub/device/dispatch/ — 14 changed dispatch files synced
Compilation targets for real machine (ivcore10):
1. CUDA kernels: --cuda-gpu-arch=ivcore10 via corex clang/16
2. ILU bridges: torch.utils.cpp_extension linking ixformer .so
3. FLA kernels: Triton JIT (if Triton works on BI-V100)
2026-08-14 07:48:52 +00:00
muh-bot
c8d79e2b02
sync: update cccl_upstream benchmarks to latest NVIDIA/cccl main
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- Updated 5 modified benchmark files (select/if, select/flagged, select/unique, histogram_common, for_each/extents)
- Added 3 new benchmark files (bitonic_sort: warp_keys.cu, warp_pairs.cu, bitonic_common.cuh)
- Now at parity with NVIDIA/cccl main for all 23 benchmark algorithm dirs
- Full inventory: 91 benchmark files, 18 cub examples, 243 test files, 60 thrust examples
2026-08-07 01:32:29 +00:00
EngineX CI
56fd68e7dd
[INFRA] Import NVIDIA/CCCL upstream as optimization reference library
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CCCL (CUDA C++ Core Libraries) provides:
- CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk)
- Thrust: high-level parallel algorithms (transform_reduce, sort, scan)
- libcudacxx: CUDA C++ standard library (atomics, barriers, memory)
- cudax: experimental features (memory resources, allocators)
- Tuning policies: per-SM hardware-specific algorithm parameters
Competition optimization vectors mapped to CCCL:
- Output TPS (83% weight): warp_reduce, block_reduce, device_topk
- Input TPS (14% weight): device_scan, block_load, prefetch
- Cache TPS (3% weight): prefix caching strategy patterns
- Memory (0.9 util): pooled/cached/buddy allocators
Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only)
License: Apache-2.0
2026-07-30 09:35:51 +00:00
