Commit Graph

3 Commits

Author SHA1 Message Date
root
6beb497447 fix(hardware): SM count 50→16 confirmed on Phanthy Cloud BI-V100
ixsmi + torch.cuda.get_device_properties confirmed:
- multi_processor_count: 16 (not 50 as in spec sheet)
- compute_capability: 7.0 (Volta-compatible)
- max_threads_per_SM: 8192
- total_memory: 32GB per GPU
- SM clock: 1500MHz (max 2500MHz)

Impact: bandwidth_per_sm = 900/16 = 56.25 GB/s (was 18 GB/s at 50 SM)
All occupancy and tile-size calculations need revision.
2026-08-01 13:39:28 +00:00
dylanyunlon
3ebc37d80d [muh] fix scale_mem_bound: 3 bugs vs CCCL util_arch.cuh
1. Return order: (items, threads) not (threads, items) — matches CCCL scaling_result
2. Items clamp upper bound: nominal*2, not nominal*1 — allows small types to double
3. Threads SMEM cap: min(nominal, round_up(max_smem/(type*items), 32)) — prevents SMEM overflow

Verified against all 18 CCCL test cases in catch2_test_util_arch.cu (was 4/14, now 18/18).

Note: C++ tuning headers (tuning_reduce.cuh etc.) have corresponding auto [t, i] destructuring
that also needs to flip to auto [i, t]. The bi100_* struct values themselves are correct
(hand-derived from SMEM constraints), but the policy_selector callers of scale_mem_bound
will produce wrong destructuring. Tracked in project/6 as separate fix item.
2026-08-01 00:00:02 +08:00
Claude
173c6afe09 [muh] kernel_map: full vllm→CCCL mapping with SMEM overflow detection
muh_kernel_map.py maps every vllm kernel to its CCCL algorithm(s):
  paged_attention_v1 → reduce (compound: summary_statistics pattern)
  paged_attention_v2 → reduce + scan (two-pass partitioned)
  sampling_topk → topk + radix_sort
  activation_kernels → transform (SiLU/GELU)
  layernorm_kernels → reduce + transform (variance + normalize)
  rotary_embedding → for_each + transform (RoPE)
  cache_kernels → batch_memcpy (KV block copy)

Found 5 lookahead SMEM overflows — documented in SPECIALIZATION_ANALYSIS.md.
These are non-functional (BI-V100 lacks warpspeed pipeline) but the
dispatch correctly falls back to lookback.

The competitive moat:
  Others: tune 5 vllm launch params → hours
  Us: tune 7 CUB primitive dimensions per algorithm × 6 algorithms,
      constrained by SMEM/occupancy/L2, with CCCL benchmark protocol
2026-07-31 11:13:33 +00:00