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300 Commits

Author SHA1 Message Date
dylan
6f1904aa8c perf: MoE decode — pre-transposed bmm replaces F.linear (6.9ms vs 8.0ms, 14%) 
Probe data (probe_moe_fused_breakdown.sh on BI-V100):
  F.linear loop 8 experts:     8.060 ms
  bmm pre-transposed full MoE: 6.918 ms  ← 14% faster
  transpose+contiguous runtime: 22.219 ms ← why CUTLASS was 27ms

Changes:
  - Lazy-cache w13_t (E,H,2I) and w2_t (E,I,H) on first decode call
  - FC1: torch.bmm(x_expand, w13_t_sel) replaces F.linear(x, w13_sel.reshape)
  - FC2: torch.bmm(act, w2_t_sel) replaces torch.bmm(w2_sel, act^T)
  - Zero runtime transpose cost after first call
 2026-08-15 12:52:55 +00:00
Claude
9f265894cc test: MoE breakdown — F.linear vs torch.mm vs torch.bmm vs bmm pre-transposed 2026-08-15 12:46:37 +00:00
Claude
e47b66e268 fix: module name in probe_moe_fused_breakdown.sh 2026-08-15 12:43:55 +00:00
Claude
b0af7d54ff test: breakdown moe_decode_fused timing by step — find the real bottleneck 2026-08-15 12:41:33 +00:00
dylan
3481f2903f fix(build): cutlass.h lives under tensorflow/include on this image 2026-08-15 12:03:12 +00:00
dylan
f41900c06b fix(build): auto-find cutlass/cutlass.h under COREX_ROOT 2026-08-15 12:02:23 +00:00
dylan
bfa18cd5b4 fix(build): use CoreX clang++ instead of nvcc — match working build scripts 2026-08-15 12:01:17 +00:00
dylan
04cc9b88af fix(build): add CUDA include path to g++ step in build_corex_batched_gemm.sh 2026-08-15 11:58:53 +00:00
dylan
ddcfbad431 feat: pybind wrapper for CUTLASS batched GEMM → MoE decode path 
Based on verified result (issue #68):
  CUTLASS Cu10 TensorOp batched: 2.462ms (8 experts, 1 launch)
  vs 8× torch.matmul: 4.6ms (8 launches)
  vs Python F.linear loop: 10.36ms

New files:
  ex_engine/xllm_kernels/cuda/bindings/corex_batched_gemm_bind.cpp
    pybind11 wrapper: batched_gemm_fp16() + moe_decode_fused()
  ex_engine/xllm_kernels/cuda/corex_batched_gemm_kernel.cu
    CUTLASS GemmBatched<half> kernel (from cat_files/batched_gemm.cu)
  qwen3_6_scripts/build_corex_batched_gemm.sh
    Build script for BI-V100 (ivcore10)

Modified:
  qwen3_6_scripts/qwen3_5.py
    import corex_batched_gemm + _USE_COREX_BATCHED_GEMM flag
    Tier 1.5 in MoE decode: after corex_direct_routed, before corex_gather

Build on device: bash qwen3_6_scripts/build_corex_batched_gemm.sh
Output: prebuilt/corex-3.2.3-ivcore10/corex_batched_gemm.so
 2026-08-15 11:54:26 +00:00
dylan
e8f0948fe1 feat: ix_ops integration layer — wire ix_full_bridge.so into vllm hot path 
Architecture (CCCL dispatch pattern):
  base_image ixformer::infer → ix_full_bridge.so → ix_ops.py → vllm patches

New files:
  ex_engine/python/ix_ops.py          — Python API for all 14 ixformer::infer ops
  ex_engine/python/patch_vllm_ops.py  — monkey-patch vllm GemmaRMSNorm, SiluAndMul
  ex_engine/deploy_ix_bridge.sh       — build-time deployment script

Modified:
  qwen3_6_scripts/patch_ops.sh        — integrated ix_bridge deployment + startup hook

Call chain: DecoderLayer.forward → GemmaRMSNorm → ix_ops.fused_add_rms_norm
            → ixformer::infer::residual_rms_norm (fused C++ kernel)
 2026-08-15 06:15:17 +00:00
Claude
f006ab1a01 test: cat tensorop GEMM example + arch.h + cutlass.h from corex-samples 2026-08-15 05:41:03 +00:00
Claude
1d36754efc fix: cat_cutlass_cu10.sh writes to cat_files/ directory instead of stdout 2026-08-15 05:31:33 +00:00
Claude
4abb4df215 test: cat Cu10 CUTLASS files — mma_cu10.h, iluvatar_mma.hpp, batched_gemm.cu, default_mma_core_cu10.h 2026-08-15 05:30:15 +00:00
Claude
6b9086c3a9 test: probe Cu10 CUTLASS fork — find mma_cu10.h, tensor op files, batched_gemm example 2026-08-15 05:27:43 +00:00
Claude
9514092980 test: probe torch.matmul backend + ixformer.matmul/linear + Python loop overhead 2026-08-15 05:17:13 +00:00
Claude
21417319bc test: sweep 6 kernel 10 configs + cublas baseline — find best params for warp64 2026-08-15 05:08:11 +00:00
Claude
27bb8d28df test: probe kernel 10 perf with CUDA events — isolate bottleneck 2026-08-14 17:23:41 +00:00
Claude
11b8a98eea test: probe warp_size=64 behavior + kernel 10 warp tiling with WARPSIZE=64 on BI-V100 2026-08-14 17:02:55 +00:00
Claude
0ace44e293 test: cat ixinfer.h + functional batched GEMM test on BI-V100 2026-08-14 12:07:00 +00:00
Claude
bfc4de2cf3 test: probe cuinfer + cublasLt + cublas batched GEMM APIs for MoE expert dispatch 2026-08-14 12:03:52 +00:00
Claude
d6958070cb test: probe CUTLASS + __CUDA_ARCH__ on BI-V100 for grouped GEMM feasibility 2026-08-14 11:59:51 +00:00
claude
50a249e0a3 Revert "feat: batched MoE expert GEMM — replaces Python for-loop" 
This reverts commit 06d7713db6.
 2026-08-14 11:47:37 +00:00
claude
06d7713db6 feat: batched MoE expert GEMM — replaces Python for-loop 
ixformer probe results:
  ✗ moe_w16a16_group_gemm NOT in ixformer .so
  ✗ CUTLASS grouped GEMM needs cuda/std (variadic function error on corex)
  ✓ ixformer_linear EXISTS (fused matmul)
  ✓ torch.mm works (uses corex cublas)

Solution: moe_batched_gemm.cu
  - C++ loop over experts (eliminates Python overhead)
  - torch::mm for GEMM (corex cublas, not F.linear Python)
  - Fused silu_and_mul CUDA kernel (not PyTorch ops)
  - Weighted scatter-add in C++
  - Skips empty experts (no wasted compute)

Integration in qwen3_5.py:
  _USE_XLLM_MOE_GEMM dispatches to moe_experts_forward()
  Falls back to Python for-loop if not available

Build: bash qwen3_6_scripts/build_xllm_kernels.sh
 2026-08-14 11:43:46 +00:00
claude
93353a1414 test: probe ixformer .so symbols for MoE grouped GEMM 
CUTLASS grouped GEMM (example 24) requires SM80 Tensor Core + cuda/std headers.
Cannot compile on corex (same issue as CCCL 3.6 variadic functions).

Alternative path: ix_moe_bridge.so calls ixformer::infer::moe_w16a16_group_gemm
which is BI-V100 optimized grouped GEMM already in the base image.

This probe script checks if the MoE functions exist in ixformer .so
before attempting to build ix_moe_bridge.so.

Run: bash qwen3_6_scripts/probe_ixformer_symbols.sh
 2026-08-14 11:40:13 +00:00
claude
865c18f852 feat: integrate xllm_moe into qwen3_5.py MoE hot path 
xllm_moe.so provides 3 fused CUDA kernels compiled for ivcore10:
  - moe_fused_topk: CUB topk + softmax (replaces corex_moe_topk_softmax)
  - moe_compute_index: histogram + prefix_sum + place (replaces corex_moe_index_combine)
  - moe_combine_result: reorder + weighted sum (available but not yet wired to output)

Dispatch priority in _pure_pytorch_experts():
  Tier 0: xllm_moe (if available)
  Tier 1: corex_moe_* individual .so
  Tier 2: PyTorch fallback

Integration points:
  1. Topk routing: xllm_moe.moe_fused_topk → corex_moe_topk_softmax → torch.topk
  2. Index computation: xllm_moe.moe_compute_index → corex_moe_index_combine → torch.argsort
  3. Expert loop: still Python F.linear (next target: batch GEMM)

patch_ops.sh already deploys all prebuilt/*.so including xllm_moe.so
 2026-08-14 11:37:21 +00:00
root
e147c283e3 prebuilt: 5 xllm CUDA kernel .so for BI-V100 (ivcore10) 
All 12/12 AST call chain tests passed:
  xllm_norm.so       (1.4MB) rms_norm max_err=0.000000, fused_add_rms_norm err=0.001953
  xllm_activation.so (1.3MB) silu_and_mul err=0.001953, gelu_and_mul err=0.001953
  xllm_rope.so       (1.2MB) rotary_embedding q_diff=1360 k_diff=1404
  xllm_cache.so      (1.3MB) reshape_paged_cache err=0.000000
  xllm_moe.so        (?.?MB) fused_topk weight_sum_err<0.01, compute_index total=64, combine err<0.1

vs ixformer: rms_norm err=0.000000, silu_and_mul err=0.000000

Compiled with corex clang/16 --cuda-gpu-arch=ivcore10
Using corex CUB (/usr/local/corex/include/cub/), NOT CCCL 3.6
 2026-08-14 11:34:23 +00:00
claude
a50adefdfc feat: xllm MoE CUDA kernels — fused_topk + compute_index + combine 
3 MoE kernel files adapted for corex:
  moe_fused_topk.cu: LOG(FATAL)→TORCH_CHECK, +torch/extension.h
  moe_compute_index.cu: CHECK_LE→TORCH_CHECK, uses cub::BlockScan (corex CUB)
  moe_combine.cu: fixed duplicate include, +torch/extension.h

New pybind binding: xllm_moe_bind.cpp
  → moe_fused_topk(gating, topk, renormalize, bias, scoring_func)
  → moe_compute_index(expert_id, num_experts)
  → moe_combine_result(gemm2, weights, N, topk)

AST verification added for all 3 functions
 2026-08-14 11:23:49 +00:00
claude
49cd7def89 fix: slot_ids dtype long→int32 in cache test 2026-08-14 11:20:07 +00:00
claude
1f51feee05 fix: cos_sin_cache dtype float→half in rope test 2026-08-14 11:18:02 +00:00
claude
7fc0c1defa test: AST call chain verification for all 4 xllm kernel .so 
verify_ast_chain.py tests every exported function:
  xllm_norm.so:       rms_norm (vs PyTorch), fused_add_rms_norm (vs PyTorch)
  xllm_activation.so: silu_and_mul (vs F.silu), gelu_and_mul (vs F.gelu)
  xllm_rope.so:       rotary_embedding (verify rotation applied)
  xllm_cache.so:      reshape_paged_cache (verify slot write)
  vs_ixformer:        compare our .so output vs base image ixformer

All 4 .so compiled successfully:
  xllm_norm.so       1.4MB  [rms_norm, fused_add_rms_norm]
  xllm_activation.so 1.3MB  [silu_and_mul, gelu_and_mul, act_and_mul]
  xllm_rope.so       1.2MB  [rotary_embedding]
  xllm_cache.so      1.3MB  [block_copy, reshape_paged_cache]
 2026-08-14 11:14:58 +00:00
claude
093bfb380f feat: pybind11 bindings for xllm CUDA kernels 
norm.cu compiled successfully on BI-V100 (only warning: fp8 __host__ attr).
Failed at import because no PYBIND11_MODULE — now fixed.

New bindings/ directory with 4 binding files:
  xllm_norm_bind.cpp      → rms_norm, fused_add_rms_norm
  xllm_activation_bind.cpp → silu_and_mul, gelu_and_mul, act_and_mul
  xllm_rope_bind.cpp       → rotary_embedding
  xllm_cache_bind.cpp      → reshape_paged_cache, block_copy

Build script updated: each .so = kernel .cu + binding .cpp
 2026-08-14 10:50:13 +00:00
claude
51cb90b9ab fix: adapt xllm norm.cu for corex CUB (CUDA 10.2) 
Key change: replace CCCL 3.6 types with corex CUB equivalents
  - cuda::std::plus<> → cub::Sum
  - cuda::maximum<>  → cub::Max
  - Remove #include <cuda/std/functional>

Test results from real machine (3/4 passed):
  ✓ __shfl_down_sync works on ivcore10
  ✓ manual SMEM+shuffle block reduce works
  ✓ corex CUB cub::BlockReduce<float,256> compiles and runs correctly (32640)
  ✗ CCCL 3.6 variadic function issue — corex clang rejects device variadic

Confirmed: use /usr/local/corex/include/cub/ for all kernel code
           cccl_upstream is reference only, NOT compilable on corex

Build script: bash qwen3_6_scripts/build_xllm_kernels.sh
 2026-08-14 10:19:51 +00:00
claude
089b9ff4e2 test: fix CUB compat tests + probe corex built-in CUB 
v1 failures analyzed:
  1. __shfl_down_sync: load_inline bug (not hardware issue) — fixed with file-based compile
  2. CCCL 3.6: 'CUDA < 12 not supported' + variadic functions in device code
     → corex reports CUDA 10.2, corex clang rejects variadic in device code

v2 tests:
  [1/4] __shfl_down_sync — does ivcore10 support warp shuffle?
  [2/4] manual block reduce — SMEM + shuffle without CUB
  [3/4] cub::BlockReduce using COREX's own CUB (/usr/local/corex/include/cub/)
  [4/4] cub::BlockReduce using CCCL 3.6 with CCCL_IGNORE_DEPRECATED_CUDA_BELOW_12

probe_corex_cub.sh — discovers corex CUB version, compiles standalone test

Run on real machine:
  bash qwen3_6_scripts/probe_corex_cub.sh
  python3 qwen3_6_scripts/test_cub_compat_v2.py
 2026-08-14 10:11:10 +00:00
claude
793743f5c0 test: CUB compatibility on BI-V100 — warp shuffle + BlockReduce 
Three tests:
  1. __shfl_down_sync — warp shuffle PTX instruction
  2. Manual block reduce (SMEM + shuffle) — handwritten
  3. cub::BlockReduce<float, 256> — actual CCCL header

If test 1+2 pass but 3 fails → CUB headers need corex adaptation
If test 1 fails → ivcore10 doesn't support warp shuffle → need different reduction strategy

Run on real machine: python3 qwen3_6_scripts/test_cub_compat.py
 2026-08-14 08:21:48 +00:00
claude
3a2cfc87c9 test: xllm CUDA kernel verification suite for BI-V100 
test_xllm_cuda_kernels.py — 7 test groups:
  1. activation.cu: silu_and_mul via ixf_F, compare vs torch.nn.functional.silu
  2. norm.cu: rms_norm + fused_add_rms_norm via ixf_F, compare vs PyTorch
  3. rope.cu: rotary_embedding via ixf_F, verify rotation applied
  4. moe_topk_softmax: corex .so, verify shapes + weights sum to 1
  5. ix_moe_bridge: full 7-step fused MoE pipeline (topk→expand→gemm→act→gemm→combine)
  6. ix_attn_bridge: load test (prefill_attention, decode_attention, linear)
  7. ix_full_bridge: silu_and_mul + rms_norm through bridge .so

Revert: undo unnecessary cccl_upstream sync (already up to date)

Run on real machine: python3 qwen3_6_scripts/test_xllm_cuda_kernels.py
 2026-08-14 08:01:23 +00:00
claude
051b02d3cd feat: ix_moe_bridge + ix_attn_bridge — dlopen bridges for full ixformer::infer API 
Bridge architecture (from xllm/core/kernels/ilu/ixformer.h):

ix_moe_bridge.so (MoE 7-step fused pipeline):
  - topk_softmax → moe_compute_token_index_api → moe_expand_input
  - moe_w16a16_group_gemm (x2) → silu_and_mul → moe_output_reduce_sum
  - fused_moe_forward(): replaces entire Python expert loop
  - Fix: group_gemm format NT→TN (match xllm trans_b=true)

ix_attn_bridge.so (attention + linear):
  - ixinfer_flash_attn_unpad_with_block_tables (fused prefill)
  - xllm_paged_attention (fused paged decode)
  - ixformer_linear (matmul + activation)
  - residual_rms_norm (fused residual + norm)

Integration:
  - ix_fused_moe.py: Python loader (prebuilt .so → JIT → unavailable)
  - qwen3_5.py: Tier 0 dispatch in _pure_pytorch_experts()
  - patch_ops.sh: deploys ix_fused_moe.py + all prebuilt/*.so

Source: jd-opensource/xllm (fresh clone, all ILU kernels verified SAME)
Sync: upstream_ref/xllm_latest/models/llm/qwen3_next_hybrid_base.h (+32 lines)

Build on real machine:
  bash qwen3_6_scripts/build_ix_moe_bridge.sh
  bash qwen3_6_scripts/build_ix_attn_bridge.sh
 2026-08-14 07:32:31 +00:00
Claude
5e9b7c292a build: all 16 .so prebuilt, no JIT compile in docker 
- install_prebuilt_corex.sh: 14→16 artifacts, allow ix_full_bridge.so name
- patch_ops.sh: remove all on-site compilation, pure prebuilt install
 2026-08-14 07:14:46 +00:00
root
28102196cd Merge branch 'main' of https://github.com/dylanyunlon/project_6 2026-08-14 07:13:36 +00:00
root
d32822c5d2 prebuilt: corex_moe_index_combine.so + ix_full_bridge.so (BI-V100 compiled) 2026-08-14 07:10:52 +00:00
Claude
e7247bd57b build: integrate ix_full_bridge + corex_moe_index_combine into docker patch_ops.sh 
Verified on real BI-V100:
- 16 .so all load successfully (15 corex + 1 ix_full_bridge)
- topk_softmax: OK (corex .so fallback works)
- protocol extra=allow: OK (max_completion_tokens accepted)
- ix_full_bridge exports: silu_and_mul, rms_norm, fused_add_rms_norm,
  rotary_embedding, reshape_and_cache
 2026-08-14 07:09:01 +00:00
Claude
d9ffc5159d fix(bridge): rewrite ix_full_bridge.cpp for real ixformer_torch_ext namespace 
nm -D confirmed real symbols are in ixformer_torch_ext:: not ixformer::infer::
Bridges: silu_and_mul, rms_norm, fused_add_rms_norm, rotary_embedding, reshape_and_cache
 2026-08-14 07:00:30 +00:00
Claude
9e3157b444 fix(P0): extra=allow + topk_softmax fallback + deploy_local.sh + SO chain verify 
P0-1: vllm/protocol.py extra=forbid → allow (fixes 90 replay 400 errors)
P0-2: _custom_ops.py topk_softmax: hasattr guard + corex .so + PyTorch fallback
P0-3: deploy_local.sh copies prebuilt .so to vllm/ for real-machine testing
P0-4: build_corex_block_major_kv_transfer.sh (was missing)
P0-5: verify_dlopen_chain.py for systematic gap detection
P0-6: patch_ops.sh adds protocol identity check + on-site corex_moe_index_combine build
 2026-08-14 06:56:00 +00:00
Claude
07fad2cce7 fix: max-num-seqs=1 + pure Q-tiling — match a3c45d3b exactly 
Profiling hung for 30min then failed. Two causes:
1. max-num-seqs=2 (a3c45d3b used 1) — doubles profiling memory
2. flash_attn_varlen_func added to xformers patch — a3c45d3b had none

Restored:
- yaml: max-num-seqs=1 (exact a3c45d3b)
- patch_xformers_sdpa_seq.py: pure Q-tiling (exact a3c45d3b)

Only diff from a3c45d3b:
- yaml: BI100_MOE_COREX_TOPK_SOFTMAX=1 (was 0)
- protocol.py: extra=allow
- qwen3_5.py: corex_gdn_chunk_recurrent + corex_moe_index_combine imports
- prebuilt: 14 .so (was 13)
 2026-08-14 05:40:05 +00:00
Claude
1f69311375 fix: flash_attn import path ixformer.contrib → ixformer.functions 
真机验证发现 ixformer.contrib.vllm_flash_attn 不存在。
flash_attn_varlen_func 实际位于 ixformer.functions
(通过 inference.functions.flash_attn_lib 导出)。

签名兼容：q,k,v,cu_seqlens_q/k,max_seqlen_q/k,softmax_scale,causal

test_dlopen_chain.py: 修复 total_mem→total_memory, ctypes.RTLD_LAZY,
系统 vllm 路径检测（避免解析到仓库里的 ./vllm/）
 2026-08-14 03:56:23 +00:00
Claude
4c1adc11db fix: restore libcccl_allocator.so + minimal .dockerignore + clean pycache 
- Restore libcccl_allocator.so (误删)
- .dockerignore 回退到最小版本 (pycache/git/大目录)
- 清理 qwen3_6_scripts/ 下 10 个 __pycache__ 目录 (cpython-312)
  竞赛容器是 python 3.10，3.12 的 .pyc 可能导致 import 失败
 2026-08-14 03:51:43 +00:00
Claude
336f3349ca fix(submit): restore flash_attn prefill + all 38eca5c2 improvements 
Keeps ALL infrastructure from the last 70 commits:
- paged_attn.py: ixformer native v1/v2 decode dispatch (Output TPS impact)
- protocol.py: extra='allow' (fixes ~180 rejected replay requests)
- qwen3_5.py: .float() router_logits, chunk_recurrent, index_combine
- 14 prebuilt .so (including corex_gdn_chunk_recurrent)
- patch_xformers: flash_attn_varlen_func + profiling guard (>32K→Q-tiling)

yaml: max-num-seqs=2, TOPK=1, gpu-mem=0.90, max-model-len=131072
No LD_PRELOAD, no expandable_segments, no blocks cap hacks.
 2026-08-14 03:47:09 +00:00
Claude
67a5639c3c fix(submit): restore a3c45d3b-proven config + safe improvements 
Based on a3c45d3b (last known working docker build):
- yaml: max-num-seqs=2 (fixes t2_n_2), TOPK_SOFTMAX=1 (use prebuilt .so)
- yaml: keep max-model-len=131072, gpu-mem=0.90 (prevents OOM)
- yaml: NO LD_PRELOAD (libcccl not built during docker build)
- xformers: revert to Q-tiling only (flash_attn caused OOM at profiling)
- .dockerignore: exclude all non-essential files from context
- remove libcccl_allocator.so from git tracking

What stays from recent work:
- 14 prebuilt .so (including corex_gdn_chunk_recurrent)
- qwen3_5.py with .float() fix and chunk_recurrent support
- All vendor_overrides and CCCL preload source (for future use)
 2026-08-14 03:35:24 +00:00
Claude
bce79e44be perf(prefill): restore flash_attn_varlen_func with profiling safety guard 
Restores ixformer flash_attn acceleration for prefill that was lost in
38eca5c2 revert. The OOM root cause was profiling-stage flash_attn on
131K dummy sequences, not flash_attn itself.

Fix: two-tier dispatch in _run_sdpa_fallback:
  1. flash_attn_varlen_func — real inference (verified 1.7x on BI-V100)
  2. Q-tiling fallback     — profiling stage (seq > 32K) or exception

Import path: ixformer.contrib.vllm_flash_attn.flash_attn_varlen_func
(canonical path matching ex_engine/python/corex_fa2.py Tier 1 and
ixformer_sdk/contrib/vllm_flash_attn/flash_attn_interface.py signature).

Reference sources:
  - ixformer_sdk/contrib/vllm_flash_attn/flash_attn_interface.py (API)
  - ex_engine/python/corex_fa2.py (dispatch pattern)
  - upstream_ref/xllm_latest/core/kernels/ilu/attention.cpp (C++ batch_prefill)
 2026-08-14 02:51:47 +00:00
Claude
74ce61712b fix(build): update prebuilt CoreX artifact count 13→14 — SHA256SUMS has 14 entries after corex_gdn_chunk_recurrent.so was added 
install_prebuilt_corex.sh asserted exactly 13 artifacts, but SHA256SUMS
now contains 14 (corex_gdn_chunk_recurrent.so was added in 9a52f057).
This mismatch causes Docker build to fail at:
  'expected 13 prebuilt CoreX artifacts, found 14'
 2026-08-14 02:39:42 +00:00
Claude
38eca5c26a revert: restore a3c45d3b yaml + Q-tiling + remove all OOM hacks 
Root cause of 10 consecutive OOM failures:
- 'return zeros during profiling' hack → vllm overestimates free memory
  → allocates 7942 blocks → first real request OOMs
- blocks cap 5000 → band-aid that masks profiling bug
- gpu-memory-utilization 0.80 → unnecessary reduction from working 0.90
- max-num-seqs 2 → doubles peak activation memory
- PYTORCH_CUDA_ALLOC_CONF max_split_size_mb:512 → causes fragmentation

Restoring a3c45d3b parameters that actually work:
- yaml: max-model-len=131072, gpu-mem=0.90, max-num-seqs=1, batched-tokens=8192
- patch_xformers_sdpa_seq.py: Q-tiling (real memory optimization, not zeros hack)
- patch_block_major_worker_capacity.py: no blocks cap, just reserve_block_major
- patch_ops.sh: remove all docker-build-time compilation (all .so are prebuilt)

Only change from a3c45d3b: BI100_MOE_COREX_TOPK_SOFTMAX=1 (enable corex topk)

Kept fixes:
- protocol.py extra=allow (recover 180 rejected replay requests)
- corex_gdn_chunk_recurrent.so pybind kwargs (prebuilt with fixed signature)
 2026-08-14 02:28:48 +00:00