project6-dev
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d86b39d1ae
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refactor(corex): rewrite 3 dlopen modules to use real ixformer::infer dispatch chain
corex_moe.py:
- Tier 0: ix_bridge.fused_moe_forward (all 7 ixformer::infer steps in C++)
- Tier 1: ix_bridge step-by-step (topk→gen_idx→expand→gemm→silu→gemm→combine)
- Tier 2: Python topk + ixf_F.silu_and_mul + torch.matmul expert loop
corex_gdn.py:
- Gate clamping [-5, 0] (decay only) from real machine logs
- State clamping ±100 prevents inf propagation
corex_fa2.py:
- Tier 0: ix_bridge C++ paged_attention/flash_attn
- Tier 1: ixformer.contrib.vllm_flash_attn Python
- Tier 2: ixf_F.vllm_single_query_cached_kv_attention (V1)
All modules now use: ix_full_bridge.cpp → ixformer::infer → libixattn.so
Matches comp 168 actual dispatch chain from docker log.
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2026-08-10 06:16:39 +00:00 |
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