2 Commits

Author	SHA1	Message	Date
project6-dev	d86b39d1ae	refactor(corex): rewrite 3 dlopen modules to use real ixformer::infer dispatch chain ... corex_moe.py: - Tier 0: ix_bridge.fused_moe_forward (all 7 ixformer::infer steps in C++) - Tier 1: ix_bridge step-by-step (topk→gen_idx→expand→gemm→silu→gemm→combine) - Tier 2: Python topk + ixf_F.silu_and_mul + torch.matmul expert loop corex_gdn.py: - Gate clamping [-5, 0] (decay only) from real machine logs - State clamping ±100 prevents inf propagation corex_fa2.py: - Tier 0: ix_bridge C++ paged_attention/flash_attn - Tier 1: ixformer.contrib.vllm_flash_attn Python - Tier 2: ixf_F.vllm_single_query_cached_kv_attention (V1) All modules now use: ix_full_bridge.cpp → ixformer::infer → libixattn.so Matches comp 168 actual dispatch chain from docker log.	2026-08-10 06:16:39 +00:00
project6-dev	5efb0fcc35	feat(EX): corex_fa2.py — third dlopen module from comp 168 AST chain ... Log analysis from dockerrizhi.txt (07-23 Sub168 run) reveals THREE corex modules, not two: 1. corex_gdn.py — GatedDeltaNet fused kernel (already implemented) 2. corex_moe.py — MoE routing + expert GEMM (already implemented) 3. corex_fa2.py — FlashAttention2 dispatch (NEW) corex_fa2.py handles 32/36 attention layers with three modes: :333 → FA2 packed prefill (B=2 Hq=4 Hkv=1 D=256 max_q=2048) :507 → FA2 paged chunked prefill (B=1 max_q=17 cache_blocks=2) :225 → FA2 paged decode (B=1 max_k=45455 partition=256) Wraps ixformer.contrib.vllm_flash_attn + ixf_F.vllm_single_query_cached_kv_attention. These .so files EXIST in the base image (libixattn.so). Also: wired corex_fa2 import into qwen3_5.py + deploy script.	2026-08-10 04:01:21 +00:00