Claude
36676f2d1b
data: complete SGEMM upstream from 3 repos (siboehm+wangzyon+edtallison) + xllm fused_qknorm_rope + xattention kernels
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SGEMM repos (upstream_ref/sgemm_cuda/, 41 files):
siboehm/SGEMM_CUDA: kernel 1-12, runner, CMake, cuBLAS benchmark
wangzyon/NVIDIA_SGEMM_PRACTICE: kernel 1-7 (Chinese comments), utils
edtallison/sgemm-cuda: kernel 01-09 (learning notes), Makefile
xllm kernels (ex_engine/xllm_kernels/cuda/):
fused_qknorm_rope.cu + bind — saves 128 kernel launches/fwd
xattention/ — 6 files from upstream xllm
headers: corex_compat_utils.h, topk_last_dim.cuh
ilu/CMakeLists.txt
SO_BUILD_MANIFEST.md — complete .so inventory and call chain analysis
2026-08-15 07:00:09 +00:00
claude
415fff85f1
fix: add DISPATCH_FLOATING_TYPES macro to device_utils.cuh
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DISPATCH_FLOATING_TYPES was defined in xllm/core/kernels/cuda/utils.h
which was pulled in via cuda_ops_api.h → utils.h.
Since cuda_ops_api.h was removed (glog dependency), the macro was missing.
Now defined in device_utils.cuh with include guard, available to all kernel files:
norm.cu, activation.cu, rope.cu, block_copy.cu, reshape_paged_cache.cu
2026-08-14 10:45:37 +00:00
claude
8d75652949
feat: import CUDA kernels from xllm/CCCL/FLA upstream repos
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Sources cloned and tree'd (no --depth):
- jd-opensource/xllm: ILU kernels, CUDA kernels, MoE kernels
- NVIDIA/cccl: CUB tuning/dispatch headers (block-level primitives)
- fla-org/flash-linear-attention: Triton GDN kernels
- NVIDIA/cutlass: grouped GEMM reference (read, not copied)
- Dao-AILab/flash-attention: attention kernel reference (SM80+, read only)
New CUDA kernels (from xllm, SM-agnostic, portable to BI-V100):
ex_engine/xllm_kernels/cuda/activation.cu (188 lines) — silu_and_mul, gelu
ex_engine/xllm_kernels/cuda/norm.cu (600 lines) — rms_norm, fused_add_rms_norm
ex_engine/xllm_kernels/cuda/rope.cu (258 lines) — rotary_embedding
ex_engine/xllm_kernels/cuda/block_copy.cu (209 lines) — copy_blocks, swap_blocks
ex_engine/xllm_kernels/cuda/reshape_paged_cache.cu (101 lines) — KV cache ops
ex_engine/xllm_kernels/cuda/headers/ (5 headers for compilation)
ILU bridge kernel sources (from xllm, verified SAME as upstream):
ex_engine/xllm_kernels/ilu/ (10 files, 925 lines total)
— activation.cpp, attention.cpp, fused_moe.cpp, group_gemm.cpp,
matmul.cpp, norm.cpp, rope.cpp, ilu_ops_api.h, ixformer.h, utils.h
FLA Triton GDN kernels (for GatedDeltaNet without SM90+ FlashQLA):
ex_engine/fla_kernels/gated_delta_rule/ (7 files, 2370 lines)
— chunk_fwd.py (428), chunk.py (487), wy_fast.py (409),
fused_recurrent.py (392), naive.py (161), gate.py (380)
CCCL sync (12 tuning + 14 dispatch headers updated from NVIDIA/cccl):
cccl_upstream/cub/cub/device/dispatch/tuning/ — 12 changed files synced
cccl_upstream/cub/cub/device/dispatch/ — 14 changed dispatch files synced
Compilation targets for real machine (ivcore10):
1. CUDA kernels: --cuda-gpu-arch=ivcore10 via corex clang/16
2. ILU bridges: torch.utils.cpp_extension linking ixformer .so
3. FLA kernels: Triton JIT (if Triton works on BI-V100)
2026-08-14 07:48:52 +00:00
