Claude
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6415249693
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data: port complete MoE + xllm layer call chains from upstream repos
MoE call chain from ds_vllm (vllm-project/vllm latest):
ex_engine/moe/ — 20 files, 8736 lines
- modular_kernel.py (1630 lines) — base classes for modular MoE
- experts/fused_batched_moe.py (972 lines) — NaiveBatchedExperts
- prepare_finalize/batched.py (171 lines) — token grouping by expert
- topk_weight_and_reduce.py (176 lines) — scatter-add finalize
- fused_moe.py (1740 lines) — main fused_moe dispatch
- config.py (1407 lines) — FusedMoEQuantConfig
- activation.py, utils.py, layer.py, etc.
xllm layer code (jd-opensource/xllm):
ex_engine/xllm_layers/ — 39 files, 5859 lines
- ilu/fused_moe.cpp (797 lines) — production ixformer 7-step MoE pipeline
- ilu/attention.cpp (189 lines) — paged_attention + flash_attn bridge
- npu_torch/qwen3_gated_delta_net_base.cpp (576 lines) — GDN reference
- common/rms_norm.cpp, rotary_embedding.cpp, activation.cpp, dense_mlp.cpp
xllm ILU kernels — synced 10 files to upstream (diffs from prior edits)
These are reference implementations, NOT hand-written.
Source repos: vllm-project/vllm, jd-opensource/xllm
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2026-08-15 14:26:24 +00:00 |
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claude
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8d75652949
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feat: import CUDA kernels from xllm/CCCL/FLA upstream repos
Sources cloned and tree'd (no --depth):
- jd-opensource/xllm: ILU kernels, CUDA kernels, MoE kernels
- NVIDIA/cccl: CUB tuning/dispatch headers (block-level primitives)
- fla-org/flash-linear-attention: Triton GDN kernels
- NVIDIA/cutlass: grouped GEMM reference (read, not copied)
- Dao-AILab/flash-attention: attention kernel reference (SM80+, read only)
New CUDA kernels (from xllm, SM-agnostic, portable to BI-V100):
ex_engine/xllm_kernels/cuda/activation.cu (188 lines) — silu_and_mul, gelu
ex_engine/xllm_kernels/cuda/norm.cu (600 lines) — rms_norm, fused_add_rms_norm
ex_engine/xllm_kernels/cuda/rope.cu (258 lines) — rotary_embedding
ex_engine/xllm_kernels/cuda/block_copy.cu (209 lines) — copy_blocks, swap_blocks
ex_engine/xllm_kernels/cuda/reshape_paged_cache.cu (101 lines) — KV cache ops
ex_engine/xllm_kernels/cuda/headers/ (5 headers for compilation)
ILU bridge kernel sources (from xllm, verified SAME as upstream):
ex_engine/xllm_kernels/ilu/ (10 files, 925 lines total)
— activation.cpp, attention.cpp, fused_moe.cpp, group_gemm.cpp,
matmul.cpp, norm.cpp, rope.cpp, ilu_ops_api.h, ixformer.h, utils.h
FLA Triton GDN kernels (for GatedDeltaNet without SM90+ FlashQLA):
ex_engine/fla_kernels/gated_delta_rule/ (7 files, 2370 lines)
— chunk_fwd.py (428), chunk.py (487), wy_fast.py (409),
fused_recurrent.py (392), naive.py (161), gate.py (380)
CCCL sync (12 tuning + 14 dispatch headers updated from NVIDIA/cccl):
cccl_upstream/cub/cub/device/dispatch/tuning/ — 12 changed files synced
cccl_upstream/cub/cub/device/dispatch/ — 14 changed dispatch files synced
Compilation targets for real machine (ivcore10):
1. CUDA kernels: --cuda-gpu-arch=ivcore10 via corex clang/16
2. ILU bridges: torch.utils.cpp_extension linking ixformer .so
3. FLA kernels: Triton JIT (if Triton works on BI-V100)
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2026-08-14 07:48:52 +00:00 |
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