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Author SHA1 Message Date
project_6
415ca12afc fix: group_gemm format "TN" + Layer 3 ops_api dispatch from xllm upstream 
AST chain alignment with upstream_ref/xllm/xllm/core/kernels/ilu/:

Layer 5: ixformer::infer (binary .so on device)
Layer 4: xllm_kernels/ilu/*.cpp -> calls ixformer::infer (0-diff with upstream)
Layer 3: xllm_kernels/ops_api.h+cpp + param.h (NEW from upstream 2719 lines)
         kernels/kernels.h aggregation header (NEW)
Layer 2: xllm_layers/ilu/*.cpp (0-diff with upstream)
Layer 1: ix_full_bridge_v2.cpp pybind11 bridge (FIXED)

Critical fixes in ix_full_bridge_v2.cpp:
- group_gemm format "default" -> "TN" (match upstream ilu/group_gemm.cpp)
- fused_moe_forward: pass 3D weights directly instead of .view({-1,...})
- group_gemm output_n: use tokens_per_experts.sum() per upstream convention
 2026-08-16 16:09:15 +00:00
Claude
6415249693 data: port complete MoE + xllm layer call chains from upstream repos 
MoE call chain from ds_vllm (vllm-project/vllm latest):
  ex_engine/moe/ — 20 files, 8736 lines
  - modular_kernel.py (1630 lines) — base classes for modular MoE
  - experts/fused_batched_moe.py (972 lines) — NaiveBatchedExperts
  - prepare_finalize/batched.py (171 lines) — token grouping by expert
  - topk_weight_and_reduce.py (176 lines) — scatter-add finalize
  - fused_moe.py (1740 lines) — main fused_moe dispatch
  - config.py (1407 lines) — FusedMoEQuantConfig
  - activation.py, utils.py, layer.py, etc.

xllm layer code (jd-opensource/xllm):
  ex_engine/xllm_layers/ — 39 files, 5859 lines
  - ilu/fused_moe.cpp (797 lines) — production ixformer 7-step MoE pipeline
  - ilu/attention.cpp (189 lines) — paged_attention + flash_attn bridge
  - npu_torch/qwen3_gated_delta_net_base.cpp (576 lines) — GDN reference
  - common/rms_norm.cpp, rotary_embedding.cpp, activation.cpp, dense_mlp.cpp

xllm ILU kernels — synced 10 files to upstream (diffs from prior edits)

These are reference implementations, NOT hand-written.
Source repos: vllm-project/vllm, jd-opensource/xllm
 2026-08-15 14:26:24 +00:00
dylan
e2fc3f270f fix: corex_batched_gemm use TCU OpClassTensorOp + Cu10 + float accum 
Previous version used default SIMT path (25ms).
Fixed version matches moe_cutlass_batched.cu (2.462ms):
  - ElementAccumulator = float (was half_t)
  - OpClassTensorOp (was default OpClassSimt)
  - arch::Cu10 (was default Sm61)
  - RowMajor layout (was ColumnMajor)
  - torch::sigmoid(x)*x instead of torch::silu (not in corex torch)

Also fixed bind.cpp: removed col-major transposition logic,
kernel now RowMajor so A(M,K) @ B(K,N) = C(M,N) directly.
 2026-08-15 12:35:56 +00:00
dylan
ddcfbad431 feat: pybind wrapper for CUTLASS batched GEMM → MoE decode path 
Based on verified result (issue #68):
  CUTLASS Cu10 TensorOp batched: 2.462ms (8 experts, 1 launch)
  vs 8× torch.matmul: 4.6ms (8 launches)
  vs Python F.linear loop: 10.36ms

New files:
  ex_engine/xllm_kernels/cuda/bindings/corex_batched_gemm_bind.cpp
    pybind11 wrapper: batched_gemm_fp16() + moe_decode_fused()
  ex_engine/xllm_kernels/cuda/corex_batched_gemm_kernel.cu
    CUTLASS GemmBatched<half> kernel (from cat_files/batched_gemm.cu)
  qwen3_6_scripts/build_corex_batched_gemm.sh
    Build script for BI-V100 (ivcore10)

Modified:
  qwen3_6_scripts/qwen3_5.py
    import corex_batched_gemm + _USE_COREX_BATCHED_GEMM flag
    Tier 1.5 in MoE decode: after corex_direct_routed, before corex_gather

Build on device: bash qwen3_6_scripts/build_corex_batched_gemm.sh
Output: prebuilt/corex-3.2.3-ivcore10/corex_batched_gemm.so
 2026-08-15 11:54:26 +00:00
Claude
36676f2d1b data: complete SGEMM upstream from 3 repos (siboehm+wangzyon+edtallison) + xllm fused_qknorm_rope + xattention kernels 
SGEMM repos (upstream_ref/sgemm_cuda/, 41 files):
  siboehm/SGEMM_CUDA: kernel 1-12, runner, CMake, cuBLAS benchmark
  wangzyon/NVIDIA_SGEMM_PRACTICE: kernel 1-7 (Chinese comments), utils
  edtallison/sgemm-cuda: kernel 01-09 (learning notes), Makefile

xllm kernels (ex_engine/xllm_kernels/cuda/):
  fused_qknorm_rope.cu + bind — saves 128 kernel launches/fwd
  xattention/ — 6 files from upstream xllm
  headers: corex_compat_utils.h, topk_last_dim.cuh
  ilu/CMakeLists.txt

SO_BUILD_MANIFEST.md — complete .so inventory and call chain analysis
 2026-08-15 07:00:09 +00:00
Claude
045ea5df79 feat: Cu10 TensorOp batched HGEMM via Iluvatar CUTLASS framework 
From corex-samples batched_gemm.cu, changed:
  float → half_t, OpClassSimt → OpClassTensorOp, Sm61 → Cu10
Uses __ivcorex_matrix_mad_f32x4_f16x4 via mma_cu10.h
Default config: TB<128,128,32> Warp<32,32,32> Inst<16,16,16>

Standalone test: correctness + perf for MoE decode (8 × 1x4096@4096x11008)
 2026-08-15 05:44:15 +00:00
Claude
395b3e4042 test: clean rebuild + debug output for kernel 10 correctness 2026-08-15 05:14:18 +00:00
Claude
a8ca42b59c perf: hgemm_warptiling Config B — beats cublas on MoE-sized GEMM (0.7x) 
probe_k10_configs.sh results on BI-V100:
  256x4096 @ 4096x11008:
    cublas:   10.554 ms
    Config B:  7.649 ms (0.7x cublas — FASTER)
    Config A:  2308 ms  (old broken config)

Config B: BM128 BN128 BK16 WM64 WN64 WNITER2 TM8 TN4 NT128
Root cause of Config A slowness: WN=128 WNITER=4 caused
excessive register pressure and smem bank conflicts.
 2026-08-15 05:11:32 +00:00
Claude
2b12fe687e feat: hgemm_warptiling.cu — siboehm kernel 10 ported to WARPSIZE=64 FP16 
1:1 from upstream_ref/sgemm_cuda/10_kernel_warptiling.cuh.
3 changes: WARPSIZE 32→64, float→__half, FP32 accumulator.

Launch config (confirmed by probe_warp64.sh):
  NUM_THREADS=128, 2 warps of 64
  BM=128 BN=128 BK=16 WM=64 WN=128 WNITER=4 TM=4 TN=4
  WMITER=2, WSUBM=32, WSUBN=32, threads_per_warp=64 ✓
 2026-08-14 17:05:59 +00:00
Claude
1af7e7cf48 fix: use c10::cuda::getCurrentCUDAStream().stream() for corex torch 2026-08-14 16:49:47 +00:00
Claude
3bee73207e fix: add cuda_runtime.h to hgemm_bind.cpp for cudaStream_t 2026-08-14 16:33:29 +00:00
Claude
09e5261ba6 refactor: hgemm_blocktiling.cu — strict 1:1 from siboehm kernel 6 
Only 3 changes from upstream_ref/sgemm_cuda/6_kernel_vectorize.cuh:
1. float → __half for A/B/C data and shared memory
2. float4 vectorized load → 4 scalar half loads (float4 needs 16-byte align)
3. threadResults accumulator stays float (FP32 accumulation)

Everything else identical: same shared mem layout, same indexing,
same A-transpose-while-loading, same thread tile computation.
No WARPSIZE. No cooperative_groups. No cuda::barrier.
 2026-08-14 16:24:22 +00:00
Claude
ab42fc1fd7 feat: hgemm_blocktiling.cu — FP16 GEMM kernel for MoE expert dispatch on BI-V100 
Adapted from siboehm/SGEMM_CUDA kernel 6 (vectorize + A transpose)
and wangzyon/NVIDIA_SGEMM_PRACTICE kernel 6 (mysgemm_v6).

Key design decisions:
- FP16 data with FP32 accumulation (avoid precision loss)
- No WARPSIZE dependency (safe for BI-V100 warp_size=64)
- Boundary checks for non-aligned M/N/K (MoE expert token counts vary)
- BM=128 BN=128 BK=8 TM=8 TN=8 (256 threads, fits BI-V100 128KB smem)
- A transpose in shared memory for coalesced reads

Two entry points:
1. hgemm(A, B) — standalone FP16 GEMM
2. moe_expert_gemm(input, weights, expert_counts) — MoE prefill path
   loops over experts with variable token counts

For decode (M=1), use cublasHgemmStridedBatched (confirmed working).

Upstream refs: upstream_ref/sgemm_cuda/6_kernel_vectorize.cuh
              upstream_ref/nvidia_sgemm_practice/kernel_6.cuh
 2026-08-14 16:22:00 +00:00
claude
50a249e0a3 Revert "feat: batched MoE expert GEMM — replaces Python for-loop" 
This reverts commit 06d7713db6.
 2026-08-14 11:47:37 +00:00
claude
06d7713db6 feat: batched MoE expert GEMM — replaces Python for-loop 
ixformer probe results:
  ✗ moe_w16a16_group_gemm NOT in ixformer .so
  ✗ CUTLASS grouped GEMM needs cuda/std (variadic function error on corex)
  ✓ ixformer_linear EXISTS (fused matmul)
  ✓ torch.mm works (uses corex cublas)

Solution: moe_batched_gemm.cu
  - C++ loop over experts (eliminates Python overhead)
  - torch::mm for GEMM (corex cublas, not F.linear Python)
  - Fused silu_and_mul CUDA kernel (not PyTorch ops)
  - Weighted scatter-add in C++
  - Skips empty experts (no wasted compute)

Integration in qwen3_5.py:
  _USE_XLLM_MOE_GEMM dispatches to moe_experts_forward()
  Falls back to Python for-loop if not available

Build: bash qwen3_6_scripts/build_xllm_kernels.sh
 2026-08-14 11:43:46 +00:00
claude
31d3ee99bb fix: MoE kernel include paths — device_utils.cuh + arch_condition.h 
Fixed xllm internal paths to our headers/ directory:
  kernels/cuda/device_utils.cuh → device_utils.cuh
  core/kernels/cuda/device_utils.cuh → device_utils.cuh
  core/kernels/cuda/arch_condition.h → arch_condition.h (copied)
 2026-08-14 11:31:54 +00:00
claude
df6a0f5d47 fix: remove cuda/functional from MoE topk kernels (not available on corex) 2026-08-14 11:29:19 +00:00
claude
a50adefdfc feat: xllm MoE CUDA kernels — fused_topk + compute_index + combine 
3 MoE kernel files adapted for corex:
  moe_fused_topk.cu: LOG(FATAL)→TORCH_CHECK, +torch/extension.h
  moe_compute_index.cu: CHECK_LE→TORCH_CHECK, uses cub::BlockScan (corex CUB)
  moe_combine.cu: fixed duplicate include, +torch/extension.h

New pybind binding: xllm_moe_bind.cpp
  → moe_fused_topk(gating, topk, renormalize, bias, scoring_func)
  → moe_compute_index(expert_id, num_experts)
  → moe_combine_result(gemm2, weights, N, topk)

AST verification added for all 3 functions
 2026-08-14 11:23:49 +00:00
claude
3d816cd18d fix: add ceil_div + DEVICE_INLINE to device_utils.cuh 
ceil_div<T> was in xllm utils.h (removed for glog).
DEVICE_INLINE macro also moved to shared header.
 2026-08-14 11:11:15 +00:00
claude
302aa9608a fix: block_copy.cu — DEVICE_INLINE, CHECK_EQ→TORCH_CHECK, cstdint 
Remaining glog dependencies removed:
  - DEVICE_INLINE macro defined inline
  - CHECK_EQ(a,b) → TORCH_CHECK(a == b)
  - CHECK_GT(a,b) → TORCH_CHECK(a > b)
  - #include <cstdint> for int32_t
 2026-08-14 11:06:07 +00:00
claude
900ae0b1ef fix: block_copy.cu remove utils.h (glog), CHECK→TORCH_CHECK 
3/4 kernels now compile:
  ✓ xllm_norm.so      (rms_norm, fused_add_rms_norm)
  ✓ xllm_activation.so (silu_and_mul, gelu_and_mul, act_and_mul)
  ✓ xllm_rope.so       (rotary_embedding)
  → xllm_cache.so      block_copy.cu had utils.h→glog — fixed
 2026-08-14 11:02:57 +00:00
claude
a206fc1d43 fix: activation.cu torch/extension.h + LOG(FATAL)→TORCH_CHECK, reshape_paged_cache.cu torch header 
xllm_norm.so: ✓ COMPILED AND LOADED (rms_norm, fused_add_rms_norm)

activation.cu fixes:
  - Add #include <torch/extension.h> (torch::Tensor not visible from torch/cuda.h alone)
  - Replace LOG(FATAL) with TORCH_CHECK (no glog)

reshape_paged_cache.cu:
  - Add #include <torch/extension.h>
 2026-08-14 10:52:54 +00:00
claude
093bfb380f feat: pybind11 bindings for xllm CUDA kernels 
norm.cu compiled successfully on BI-V100 (only warning: fp8 __host__ attr).
Failed at import because no PYBIND11_MODULE — now fixed.

New bindings/ directory with 4 binding files:
  xllm_norm_bind.cpp      → rms_norm, fused_add_rms_norm
  xllm_activation_bind.cpp → silu_and_mul, gelu_and_mul, act_and_mul
  xllm_rope_bind.cpp       → rotary_embedding
  xllm_cache_bind.cpp      → reshape_paged_cache, block_copy

Build script updated: each .so = kernel .cu + binding .cpp
 2026-08-14 10:50:13 +00:00
claude
415fff85f1 fix: add DISPATCH_FLOATING_TYPES macro to device_utils.cuh 
DISPATCH_FLOATING_TYPES was defined in xllm/core/kernels/cuda/utils.h
which was pulled in via cuda_ops_api.h → utils.h.
Since cuda_ops_api.h was removed (glog dependency), the macro was missing.

Now defined in device_utils.cuh with include guard, available to all kernel files:
  norm.cu, activation.cu, rope.cu, block_copy.cu, reshape_paged_cache.cu
 2026-08-14 10:45:37 +00:00
claude
0359103b9b fix: remove glog/cuda_ops_api.h dependency from all xllm CUDA kernels 
cuda_ops_api.h includes glog/logging.h and ATen/DynamicLibrary.h
which are not available in corex standalone compilation.

All kernel .cu files only need device_utils.cuh (provides namespace,
XLLM_KERNEL_ATTR macro, CUB includes, type helpers).

Fixed files:
  norm.cu, activation.cu, rope.cu, block_copy.cu, reshape_paged_cache.cu
  moe/moe_combine.cu, moe/moe_compute_index.cu, moe/moe_fused_topk.cu
 2026-08-14 10:30:10 +00:00
claude
51cb90b9ab fix: adapt xllm norm.cu for corex CUB (CUDA 10.2) 
Key change: replace CCCL 3.6 types with corex CUB equivalents
  - cuda::std::plus<> → cub::Sum
  - cuda::maximum<>  → cub::Max
  - Remove #include <cuda/std/functional>

Test results from real machine (3/4 passed):
  ✓ __shfl_down_sync works on ivcore10
  ✓ manual SMEM+shuffle block reduce works
  ✓ corex CUB cub::BlockReduce<float,256> compiles and runs correctly (32640)
  ✗ CCCL 3.6 variadic function issue — corex clang rejects device variadic

Confirmed: use /usr/local/corex/include/cub/ for all kernel code
           cccl_upstream is reference only, NOT compilable on corex

Build script: bash qwen3_6_scripts/build_xllm_kernels.sh
 2026-08-14 10:19:51 +00:00
claude
8d75652949 feat: import CUDA kernels from xllm/CCCL/FLA upstream repos 
Sources cloned and tree'd (no --depth):
  - jd-opensource/xllm: ILU kernels, CUDA kernels, MoE kernels
  - NVIDIA/cccl: CUB tuning/dispatch headers (block-level primitives)
  - fla-org/flash-linear-attention: Triton GDN kernels
  - NVIDIA/cutlass: grouped GEMM reference (read, not copied)
  - Dao-AILab/flash-attention: attention kernel reference (SM80+, read only)

New CUDA kernels (from xllm, SM-agnostic, portable to BI-V100):
  ex_engine/xllm_kernels/cuda/activation.cu    (188 lines) — silu_and_mul, gelu
  ex_engine/xllm_kernels/cuda/norm.cu          (600 lines) — rms_norm, fused_add_rms_norm
  ex_engine/xllm_kernels/cuda/rope.cu          (258 lines) — rotary_embedding
  ex_engine/xllm_kernels/cuda/block_copy.cu    (209 lines) — copy_blocks, swap_blocks
  ex_engine/xllm_kernels/cuda/reshape_paged_cache.cu (101 lines) — KV cache ops
  ex_engine/xllm_kernels/cuda/headers/         (5 headers for compilation)

ILU bridge kernel sources (from xllm, verified SAME as upstream):
  ex_engine/xllm_kernels/ilu/    (10 files, 925 lines total)
  — activation.cpp, attention.cpp, fused_moe.cpp, group_gemm.cpp,
    matmul.cpp, norm.cpp, rope.cpp, ilu_ops_api.h, ixformer.h, utils.h

FLA Triton GDN kernels (for GatedDeltaNet without SM90+ FlashQLA):
  ex_engine/fla_kernels/gated_delta_rule/  (7 files, 2370 lines)
  — chunk_fwd.py (428), chunk.py (487), wy_fast.py (409),
    fused_recurrent.py (392), naive.py (161), gate.py (380)

CCCL sync (12 tuning + 14 dispatch headers updated from NVIDIA/cccl):
  cccl_upstream/cub/cub/device/dispatch/tuning/ — 12 changed files synced
  cccl_upstream/cub/cub/device/dispatch/ — 14 changed dispatch files synced

Compilation targets for real machine (ivcore10):
  1. CUDA kernels: --cuda-gpu-arch=ivcore10 via corex clang/16
  2. ILU bridges: torch.utils.cpp_extension linking ixformer .so
  3. FLA kernels: Triton JIT (if Triton works on BI-V100)
 2026-08-14 07:48:52 +00:00
project6-dev
0b0c47fddd fix(critical): fold max_completion_tokens + max_num_seqs=2 + max_model_len=80000 + xllm_latest layer import 
Sub 655 root causes (confirmed from log analysis):
1. protocol.py: max_completion_tokens never folded into max_tokens
   → 162/881 replay requests rejected 400 (extra_forbidden)
2. max_num_seqs=1 → t2_n_2 test fails (needs n=2)
3. max_model_len=131072 → OOM crash at 62% replay, opencompass all 0

Fixes:
- protocol.py: model_validator fold_max_completion_tokens
- yaml: max_num_seqs=2, max_model_len=80000, PYTORCH_CUDA_ALLOC_CONF
- topk_softmax stays =0 (corex CUB BlockReduce incompatible on BI-V100)

xllm_latest import to ex_engine/:
- npu_torch layers: GDN(1164L), Qwen3.5 GDN, attention, fused_moe
- cuda/moe kernels: topk_softmax_kernels.cuh, moe_combine, moe_compute_index
- npu kernels: causal_conv1d, recurrent_gated_delta_rule
- model headers: qwen3_5.h, qwen3_next.h
 2026-08-13 03:19:39 +00:00