From eaca73a3905deff58f9e3cea8a6aedaf5f774f18 Mon Sep 17 00:00:00 2001
From: dylanyunlon <dogechat@163.com>
Date: Sat, 1 Aug 2026 02:08:28 +0800
Subject: [PATCH] [muh] add tuning_adjacent_difference.cuh: BI-V100 tuning
 header for adjacent_difference

Translated from CCCL cub/device/dispatch/tuning/tuning_adjacent_difference.cuh.
Uses hardware_capability dispatch instead of compute_capability.
---
 .../muh/tuning/tuning_adjacent_difference.cuh | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 muh/include/muh/tuning/tuning_adjacent_difference.cuh

diff --git a/muh/include/muh/tuning/tuning_adjacent_difference.cuh b/muh/include/muh/tuning/tuning_adjacent_difference.cuh
new file mode 100644
index 00000000..2ba75b9e
--- /dev/null
+++ b/muh/include/muh/tuning/tuning_adjacent_difference.cuh
@@ -0,0 +1,46 @@
+// muh/include/muh/tuning/tuning_adjacent_difference.cuh — BI-V100
+//
+// Mirrors: cccl_upstream/cub/cub/device/dispatch/tuning/tuning_adjacent_difference.cuh
+// CCCL: single policy for all architectures. No SM100 specialization.
+//   threads=128, items=nominal_8B_items_to_items(7, value_size), WARP_TRANSPOSE, LDG/CA
+//
+// vllm relevance: low (KV cache delta encoding, not on hot path)
+// SMEM risk: 128*items*value_size — at value_size=8, items=7, tile=7168 ≤ 49152 ✓
+
+#pragma once
+
+#include "muh/hardware.cuh"
+#include "muh/tuning/common.cuh"
+
+namespace muh::tuning::adjacent_difference {
+
+struct AdjacentDifferencePolicy {
+  int threads_per_block;
+  int items_per_thread;
+  BlockLoadAlgorithm load_algorithm;
+  CacheLoadModifier load_modifier;
+  BlockStoreAlgorithm store_algorithm;
+};
+
+// CCCL's nominal_8B_items_to_items: scale items for non-8B types
+// items = max(1, nominal_8B_items * 8 / value_type_size)
+constexpr int nominal_8B_items(int nominal, int value_size) {
+  int items = nominal * 8 / value_size;
+  return items < 1 ? 1 : items;
+}
+
+struct policy_selector {
+  int value_type_size;
+  bool may_alias;
+
+  constexpr AdjacentDifferencePolicy operator()(const hardware_capability& /*hw*/) const {
+    // CCCL uses the same policy for all architectures
+    return {128,
+            nominal_8B_items(7, value_type_size),
+            BLOCK_LOAD_WARP_TRANSPOSE,
+            may_alias ? LOAD_CA : LOAD_LDG,
+            BLOCK_STORE_WARP_TRANSPOSE};
+  }
+};
+
+} // namespace muh::tuning::adjacent_difference