From b922d694dc89fa431de8167e56103dcf8e27fca2 Mon Sep 17 00:00:00 2001 From: root Date: Sat, 15 Aug 2026 05:32:10 +0000 Subject: [PATCH] data: Cu10 CUTLASS headers from corex-samples --- cat_files/batched_gemm.cu | 345 ++ cat_files/cutlass_samples_tree.txt | 4304 +++++++++++++++++ cat_files/default_gemm.h | 383 ++ cat_files/default_gemm_configuration.h | 292 ++ cat_files/default_gemm_universal.h | 307 ++ cat_files/default_mma_core.h | 114 + cat_files/default_mma_core_cu10.h | 835 ++++ cat_files/default_mma_tensor_op.h | 148 + cat_files/gemm_batched.h | 726 +++ cat_files/gemm_universal.h | 376 ++ cat_files/iluvatar_mma.hpp | 1238 +++++ cat_files/ixinfer.h | 4058 ++++++++++++++++ cat_files/mma_cu10.h | 394 ++ cat_files/mma_tensor_op.h | 382 ++ cat_files/mma_tensor_op_policy.h | 71 + cat_files/mma_tensor_op_tile_iterator.h | 5595 +++++++++++++++++++++++ 16 files changed, 19568 insertions(+) create mode 100644 cat_files/batched_gemm.cu create mode 100644 cat_files/cutlass_samples_tree.txt create mode 100644 cat_files/default_gemm.h create mode 100644 cat_files/default_gemm_configuration.h create mode 100644 cat_files/default_gemm_universal.h create mode 100644 cat_files/default_mma_core.h create mode 100644 cat_files/default_mma_core_cu10.h create mode 100644 cat_files/default_mma_tensor_op.h create mode 100644 cat_files/gemm_batched.h create mode 100644 cat_files/gemm_universal.h create mode 100644 cat_files/iluvatar_mma.hpp create mode 100644 cat_files/ixinfer.h create mode 100644 cat_files/mma_cu10.h create mode 100644 cat_files/mma_tensor_op.h create mode 100644 cat_files/mma_tensor_op_policy.h create mode 100644 cat_files/mma_tensor_op_tile_iterator.h diff --git a/cat_files/batched_gemm.cu b/cat_files/batched_gemm.cu new file mode 100644 index 00000000..a9d8a9c6 --- /dev/null +++ b/cat_files/batched_gemm.cu @@ -0,0 +1,345 @@ +/*************************************************************************************************** + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ + +#include +#include + +#include "cutlass/cutlass.h" +#include "cutlass/layout/matrix.h" +#include "cutlass/gemm/device/gemm_batched.h" + +#pragma warning( disable : 4503) + +/* +This example demonstrates how to use cutlass to compute a batched strided gemm. +In this example, both A and B matrix are non-transpose and column major matrix +batched_C = batched_A x batched_B +As an example, matrix C can be seen as +----------------------------------------------------------- +(0,0,0) | (0,0,1) | (0,0,2) | (1,0,0) | (1,0,1) | (1,0,2) | +----------------------------------------------------------- +(0,1,0) | (0,1,1) | (0,1,2) | (1,1,0) | (1,1,1) | (1,1,2) | +----------------------------------------------------------- +(0,2,0) | (0,2,1) | (0,2,2) | (1,2,0) | (1,2,1) | (1,2,2) | +----------------------------------------------------------- +(0,3,0) | (0,3,1) | (0,3,2) | (1,3,0) | (1,3,1) | (1,3,2) | +----------------------------------------------------------- +(0,4,0) | (0,4,1) | (0,4,2) | (1,4,0) | (1,4,1) | (1,4,2) | +----------------------------------------------------------- +(0,5,0) | (0,5,1) | (0,5,2) | (1,5,0) | (1,5,1) | (1,5,2) | +----------------------------------------------------------- + batch 0 | batch 1 +where we denote each element with (batch_idx, row_idx, column_idx) +In this example, batch size is 2, M is 6 and N is 3 +The stride (batch_stride_C) between the first element of two batches is ldc * n + +matrix A can be seen as +--------------------------------------- +(0,0,0) | (0,0,1) | (1,0,0) | (1,0,1) | +--------------------------------------- +(0,1,0) | (0,1,1) | (1,1,0) | (1,1,1) | +--------------------------------------- +(0,2,0) | (0,2,1) | (1,2,0) | (1,2,1) | +--------------------------------------- +(0,3,0) | (0,3,1) | (1,3,0) | (1,3,1) | +--------------------------------------- +(0,4,0) | (0,4,1) | (1,4,0) | (1,4,1) | +--------------------------------------- +(0,5,0) | (0,5,1) | (1,5,0) | (1,5,1) | +--------------------------------------- + batch 0 | batch 1 +, where batch size is 2, M is 6 and K is 2 +The stride (batch_stride_B) between the first element of two batches is lda * k + +matrix B can be seen as +----------------------------- +(0,0,0) | (0,0,1) | (0,0,2) | +----------------------------- batch 0 +(0,1,0) | (0,1,1) | (0,1,2) | +------------------------------------- +(1,0,0) | (1,0,1) | (1,0,2) | +----------------------------- batch 1 +(1,1,0) | (1,1,1) | (1,1,2) | +----------------------------- +, where the batch size is 2, N is 3 and K is 2 +The stride (batch_stride_C) between the first element of two batches is k + + +*/ + +cudaError_t cutlass_strided_batched_sgemm( + int m, + int n, + int k, + float alpha, + float const *A, + int lda, + long long int batch_stride_A, + float const *B, + int ldb, + long long int batch_stride_B, + float *C, + int ldc, + long long int batch_stride_C, + float beta, + int batch_count) { + + using Gemm = cutlass::gemm::device::GemmBatched< + float, cutlass::layout::ColumnMajor, + float, cutlass::layout::ColumnMajor, + float, cutlass::layout::ColumnMajor + >; + + Gemm gemm_op; + + cutlass::Status status = gemm_op({ + {m, n, k}, + {A, lda}, + batch_stride_A, + {B, ldb}, + batch_stride_B, + {C, ldc}, + batch_stride_C, + {C, ldc}, + batch_stride_C, + {alpha, beta}, + batch_count + }); + + if (status != cutlass::Status::kSuccess) { + return cudaErrorUnknown; + } + + return cudaSuccess; +} + +template +cudaError_t strided_batched_gemm_nn_reference( + int m, + int n, + int k, + T alpha, + std::vector const &A, + int lda, + long long int batch_stride_A, + std::vector const &B, + int ldb, + long long int batch_stride_B, + std::vector &C, + int ldc, + long long int batch_stride_C, + T beta, + int batch_count) { + /* + strided batched gemm NN + */ + + cudaError_t result = cudaSuccess; + + if (A.size() < lda * k * batch_count) { + std::cout << "the size of A is too small" << std::endl; + return cudaErrorInvalidValue; + } + if (B.size() < ldb * n) { + std::cout << "the size of B is too small" << std::endl; + return cudaErrorInvalidValue; + } + if (C.size() < ldc * n * batch_count) { + std::cout << "the size of C is too small" << std::endl; + return cudaErrorInvalidValue; + } + + for (int batch_idx = 0; batch_idx < batch_count; batch_idx++) { + for (int n_idx = 0; n_idx < n; n_idx++) { + for (int m_idx = 0; m_idx < m; m_idx++) { + T accum = beta * C[batch_idx * batch_stride_C + n_idx * ldc + m_idx]; + for (int k_idx = 0; k_idx < k; k_idx++) { + accum += alpha + * A[batch_idx * batch_stride_A + k_idx * lda + m_idx] + * B[batch_idx * batch_stride_B + n_idx * ldb + k_idx]; + } + C[batch_idx * batch_stride_C + n_idx * ldc + m_idx] = accum; + } + } + } + + return result; +} + +int main() { + + // Arbitrary problem size + int const m = 520; + int const n = 219; + int const k = 129; + int const batch_count = 17; + + // A, B are non-transpose, column major + int const lda = m; + int const ldb = k * batch_count; + int const ldc = m; + + int const count_A = batch_count * lda * k; + int const count_B = ldb * n; + int const count_C = batch_count * ldc * n; + + // the memory is batched along K dimension + long long int batch_stride_A = static_cast(lda) * static_cast(k); + long long int batch_stride_B = static_cast(k); + long long int batch_stride_C = static_cast(ldc) * static_cast(n); + + // alpha and beta + float alpha = 1.0f; + float beta = 2.0f; + + cudaError_t result = cudaSuccess; + + // allocate the host memory + std::vector host_A(count_A); + std::vector host_B(count_B); + std::vector host_C(count_C); + std::vector result_C(count_C); + + // allocate the device memory + float *A; + float *B; + float *C; + + result = cudaMalloc(&A, count_A * sizeof(float)); + if (result != cudaSuccess) { + std::cerr << "cudaMalloc result = " << result << std::endl; + return result; + } + result = cudaMalloc(&B, count_B * sizeof(float)); + if (result != cudaSuccess) { + std::cerr << "cudaMalloc result = " << result << std::endl; + return result; + } + result = cudaMalloc(&C, count_C * sizeof(float)); + if (result != cudaSuccess) { + std::cerr << "cudaMalloc result = " << result << std::endl; + return result; + } + + // Limit range to avoid floating-point errors + int const kRange = 8; + + // fill A + for (int b_idx = 0; b_idx < batch_count; b_idx++) { + for (int col_idx = 0; col_idx < k; col_idx++) { + for (int row_idx = 0; row_idx < m; row_idx++) { + host_A[row_idx + col_idx * lda + b_idx * lda * k] = static_cast((row_idx + col_idx * lda + b_idx * lda * k) % kRange); + } + } + } + // fill B + for (int b_idx = 0; b_idx < batch_count; b_idx++) { + for (int col_idx = 0; col_idx < n; col_idx++) { + for (int row_idx = 0; row_idx < k; row_idx++) { + host_B[row_idx + col_idx * ldb + b_idx * k] = static_cast(((n + k * ldb + batch_count * k) - (row_idx + col_idx * ldb + b_idx * k)) % kRange); + } + } + } + // fill C + for (int b_idx = 0; b_idx < batch_count; b_idx++) { + for (int col_idx = 0; col_idx < n; col_idx++) { + for (int row_idx = 0; row_idx < m; row_idx++) { + host_C[row_idx + col_idx * ldc + b_idx * ldc * n] = 1.f; + } + } + } + + // ref memory + std::vector ref_A(host_A); + std::vector ref_B(host_B); + std::vector ref_C(host_C); + // copy host memory to device + result = cudaMemcpy(A, host_A.data(), count_A * sizeof(float), cudaMemcpyHostToDevice); + if (result != cudaSuccess) { + std::cerr << "cudaMemcpy result = " << result << std::endl; + return result; + } + result = cudaMemcpy(B, host_B.data(), count_B * sizeof(float), cudaMemcpyHostToDevice); + if (result != cudaSuccess) { + std::cerr << "cudaMemcpy result = " << result << std::endl; + return result; + } + result = cudaMemcpy(C, host_C.data(), count_C * sizeof(float), cudaMemcpyHostToDevice); + if (result != cudaSuccess) { + std::cerr << "cudaMemcpy result = " << result << std::endl; + return result; + } + + // run cutlass + result = cutlass_strided_batched_sgemm( + m, n, k, alpha, A, lda, batch_stride_A, B, ldb, batch_stride_B, C, ldc, batch_stride_C, + beta, batch_count); + if (result != cudaSuccess) + return result; + + // copy device memory to host + result = cudaMemcpy(result_C.data(), C, count_C * sizeof(float), cudaMemcpyDeviceToHost); + if (result != cudaSuccess) { + std::cerr << "cudaMemcpy result = " << result << std::endl; + return result; + } + + //compare with reference code + result = strided_batched_gemm_nn_reference(m, n, k, alpha, ref_A, lda, batch_stride_A, ref_B, ldb, batch_stride_B, ref_C, ldc, batch_stride_C, + beta, batch_count); + if (result != 0) + return result; + + // Expect bit-level accuracy for this simple example + if (ref_C != result_C) { + std::cout << "CUTLASS strided batched gemm does not run correctly" << std::endl; + return cudaErrorUnknown; + } + + // free memory + result = cudaFree(A); + if (result != cudaSuccess) { + std::cerr << "cudaFree result = " << result << std::endl; + return result; + } + result = cudaFree(B); + if (result != cudaSuccess) { + std::cerr << "cudaFree result = " << result << std::endl; + return result; + } + result = cudaFree(C); + if (result != cudaSuccess) { + std::cerr << "cudaFree result = " << result << std::endl; + return result; + } + + + if (result == cudaSuccess) { + std::cout << "Passed." << std::endl; + } + + // Exit. + return result == cudaSuccess ? 0 : -1; +} diff --git a/cat_files/cutlass_samples_tree.txt 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+/usr/local/corex-samples-3.2.3_x86_64/samples/cutlass/tools/util/include/cutlass/util/type_traits.h diff --git a/cat_files/default_gemm.h b/cat_files/default_gemm.h new file mode 100644 index 00000000..707d7c32 --- /dev/null +++ b/cat_files/default_gemm.h @@ -0,0 +1,383 @@ +/*************************************************************************************************** + * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ + +/*************************************************************************************************** +* Copyright (c) 2021 Iluvatar CoreX. All rights reserved. +* Copyright Declaration: This software, including all of its code and documentation, +* except for the third-party software it contains, is a copyrighted work of Shanghai Iluvatar CoreX +* Semiconductor Co., Ltd. and its affiliates ("Iluvatar CoreX") in accordance with the PRC Copyright +* Law and relevant international treaties, and all rights contained therein are enjoyed by Iluvatar +* CoreX. No user of this software shall have any right, ownership or interest in this software and +* any use of this software shall be in compliance with the terms and conditions of the End User +* License Agreement. + **************************************************************************************************/ + + +/*! \file + \brief + Default kernel-level GEMM definitions combine threadblock-scoped matrix multiply-add with + the appropriate threadblock-scoped epilogue. + + Note, CUTLASS epilogues universally target row-major outputs. Column-major outputs are + accommodated by exchanging A and B operands and assuming transposed layouts. Partial + specializations here choose 'device::GemmTransposed' to implement this functionality. +*/ + +#pragma once + +#include "cutlass/cutlass.h" + +#include "cutlass/layout/matrix.h" +#include "cutlass/numeric_types.h" +#include "cutlass/arch/mma.h" + +#include "cutlass/epilogue/threadblock/epilogue.h" +#include "cutlass/epilogue/thread/linear_combination.h" + +#include "cutlass/gemm/gemm.h" +#include "cutlass/gemm/kernel/gemm.h" +#include "cutlass/gemm/kernel/gemm_pipelined.h" +#include "cutlass/gemm/threadblock/default_mma.h" +#include "cutlass/gemm/threadblock/default_mma_core_simt.h" +#include "cutlass/gemm/threadblock/threadblock_swizzle.h" + +#include "cutlass/epilogue/threadblock/default_epilogue_simt.h" +#include "cutlass/epilogue/threadblock/default_epilogue_tensor_op.h" +#include "cutlass/transform/threadblock/predicated_tile_iterator.h" + + +//////////////////////////////////////////////////////////////////////////////// + +namespace cutlass { +namespace gemm { +namespace kernel { + +//////////////////////////////////////////////////////////////////////////////// + +template < + /// Element type for A matrix operand + typename ElementA_, + /// Layout type for A matrix operand + typename LayoutA_, + /// Access granularity of A matrix in units of elements + int kAlignmentA, + /// Element type for B matrix operand + typename ElementB_, + /// Layout type for B matrix operand + typename LayoutB_, + /// Access granularity of B matrix in units of elements + int kAlignmentB, + /// Element type for C and D matrix operands + typename ElementC_, + /// Layout type for C and D matrix operands + typename LayoutC_, + /// Element type for internal accumulation + typename ElementAccumulator, + /// Operator class tag + typename OperatorClass, + /// Tag indicating architecture to tune for + typename ArchTag, + /// Threadblock-level tile size (concept: GemmShape) + typename ThreadblockShape, + /// Warp-level tile size (concept: GemmShape) + typename WarpShape, + /// Warp-level tile size (concept: GemmShape) + typename InstructionShape, + /// Epilogue output operator + typename EpilogueOutputOp, + /// Threadblock-level swizzling operator + typename ThreadblockSwizzle, + /// Number of stages used in the pipelined mainloop + int Stages, + /// If true, kernel is configured to support serial reduction in the + /// epilogue + bool SplitKSerial, + /// Operation performed by GEMM + typename Operator> +struct DefaultGemm; + +//////////////////////////////////////////////////////////////////////////////// + +/// Partial specialization for SIMT +template < + /// Element type for A matrix operand + typename ElementA, + /// Layout type for A matrix operand + typename LayoutA, + /// Access granularity of A matrix in units of elements + int kAlignmentA, + /// Element type for B matrix operand + typename ElementB, + /// Layout type for B matrix operand + typename LayoutB, + /// Access granularity of A matrix in units of elements + int kAlignmentB, + /// Element type for C and D matrix operands + typename ElementC, + /// Element type for internal accumulation + typename ElementAccumulator, + /// Tag indicating architecture to tune for + typename ArchTag, + /// Threadblock-level tile size (concept: GemmShape) + typename ThreadblockShape, + /// Warp-level tile size (concept: GemmShape) + typename WarpShape, + /// Epilogue output operator + typename EpilogueOutputOp, + /// Threadblock-level swizzling operator + typename ThreadblockSwizzle, + /// If true, kernel is configured to support serial reduction in the epilogue + bool SplitKSerial, + /// Operation performed by GEMM + typename Operator + > +struct DefaultGemm< + ElementA, + LayoutA, + kAlignmentA, + ElementB, + LayoutB, + kAlignmentB, + ElementC, + layout::RowMajor, + ElementAccumulator, + arch::OpClassSimt, + ArchTag, + ThreadblockShape, + WarpShape, + GemmShape<1, 1, 1>, + EpilogueOutputOp, + ThreadblockSwizzle, + 2, + SplitKSerial, + Operator> { + /// Define the threadblock-scoped matrix multiply-accumulate + using Mma = typename cutlass::gemm::threadblock::DefaultMma< + ElementA, + LayoutA, + kAlignmentA, + ElementB, + LayoutB, + kAlignmentB, + ElementAccumulator, + layout::RowMajor, + arch::OpClassSimt, + arch::Sm50, + ThreadblockShape, + WarpShape, + GemmShape<1, 1, 1>, + 2, + Operator>::ThreadblockMma; + + static int const kEpilogueElementsPerAccess = EpilogueOutputOp::kCount; + static_assert(kEpilogueElementsPerAccess == 1, "simt epilogue must operate on scalars"); + + /// Define the epilogue + using Epilogue = typename cutlass::epilogue::threadblock::DefaultEpilogueSimt< + ThreadblockShape, + typename Mma::Operator, + EpilogueOutputOp, + kEpilogueElementsPerAccess + >::Epilogue; + + /// Define the kernel-level GEMM operator. + using GemmKernel = kernel::Gemm; +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Partial specialization for SIMT DP4A + +template < + /// Layout type for A matrix operand + typename LayoutA, + /// Access granularity of A matrix in units of elements + int kAlignmentA, + /// Layout type for B matrix operand + typename LayoutB, + /// Access granularity of A matrix in units of elements + int kAlignmentB, + /// Layout type for C matrix operand + typename LayoutC, + /// Element type for C and D matrix operands + typename ElementC, + /// Tag indicating architecture to tune for + typename ArchTag, + /// Element type for internal accumulation + typename ElementAccumulator, + /// Threadblock-level tile size (concept: GemmShape) + typename ThreadblockShape, + /// Warp-level tile size (concept: GemmShape) + typename WarpShape, + /// Epilogue output operator + typename EpilogueOutputOp, + /// Threadblock-level swizzling operator + typename ThreadblockSwizzle, + /// If true, kernel is configured to support serial reduction in the + /// epilogue + bool SplitKSerial, + /// Operation performed by GEMM + typename Operator> +struct DefaultGemm, + EpilogueOutputOp, ThreadblockSwizzle, 2, SplitKSerial, + Operator> { + using InstructionShape = GemmShape<1, 1, 4>; + using ElementA = int8_t; + using ElementB = int8_t; + + using OperatorClass = arch::OpClassSimt; + /// Define the threadblock-scoped matrix multiply-accumulate + using Mma = typename cutlass::gemm::threadblock::DefaultMma::ThreadblockMma; + + static int const kEpilogueElementsPerAccess = EpilogueOutputOp::kCount; + static_assert(kEpilogueElementsPerAccess == 1, "simt epilogue must operate on scalars"); + + /// Define the epilogue + using Epilogue = typename cutlass::epilogue::threadblock::DefaultEpilogueSimt< + ThreadblockShape, + typename Mma::Operator, + EpilogueOutputOp, + kEpilogueElementsPerAccess + >::Epilogue; + + /// Define the kernel-level GEMM operator. + using GemmKernel = kernel::Gemm; +}; + + +//////////////////////////////////////////////////////////////////////////////// +/// Partial specialization for BigIsland 1.0 tensor op architecture +template < + /// Element type for A matrix operand + typename ElementA, + /// Layout type for A matrix operand + typename LayoutA, + /// Access granularity of A matrix in units of elements + int kAlignmentA, + /// Element type for B matrix operand + typename ElementB, + /// Layout type for B matrix operand + typename LayoutB, + /// Access granularity of B matrix in units of elements + int kAlignmentB, + /// Element type for C and D matrix operands + typename ElementC, + /// Element type for internal accumulation + typename ElementAccumulator, + /// Tag indicating architecture to tune for + typename ArchTag, + /// Threadblock-level tile size (concept: GemmShape) + typename ThreadblockShape, + /// Warp-level tile size (concept: GemmShape) + typename WarpShape, + /// Instrcution shape + typename InstructionShape, + /// Epilogue output operator + typename EpilogueOutputOp, + /// Threadblock-level swizzling operator + typename ThreadblockSwizzle, + /// Number of stages used in the pipelined mainloop + int Stages, + /// If true, kernel is configured to support serial reduction in the epilogue + bool SplitKSerial, + /// Operation performed by GEMM + typename Operator +> +struct DefaultGemm< + ElementA, LayoutA, kAlignmentA, + ElementB, LayoutB, kAlignmentB, + ElementC, layout::RowMajor, + ElementAccumulator, + arch::OpClassTensorOp, + ArchTag, + ThreadblockShape, + WarpShape, + InstructionShape, + EpilogueOutputOp, + ThreadblockSwizzle, + Stages, + SplitKSerial, + Operator +> { + + /// Define the threadblock-scoped matrix multiply-accumulate + using Mma = typename cutlass::gemm::threadblock::DefaultMma< + ElementA, + LayoutA, + kAlignmentA, + ElementB, + LayoutB, + kAlignmentB, + ElementAccumulator, + layout::RowMajor, + arch::OpClassTensorOp, + ArchTag, + ThreadblockShape, + WarpShape, + InstructionShape, + Stages, + Operator + >::ThreadblockMma; + + static const int kPartitionsK = ThreadblockShape::kK / WarpShape::kK; + + /// FIXME(Peter Han): Probably DefaultEpiloguesTensorOp should be used here, let's see + static const int kEpilougeElementsPerAccess = EpilogueOutputOp::kCount; + + /// Define the epilogue + using Epilogue = typename cutlass::epilogue::threadblock::DefaultEpilogueTensorOp< + ThreadblockShape, + typename Mma::Operator, + EpilogueOutputOp, + kEpilougeElementsPerAccess + >::Epilogue; + + /// Define the kernel-level GEMM operator. + using GemmKernel = kernel::Gemm; +}; + + +//////////////////////////////////////////////////////////////////////////////// + +} // namespace kernel +} // namespace gemm +} // namespace cutlass diff --git a/cat_files/default_gemm_configuration.h b/cat_files/default_gemm_configuration.h new file mode 100644 index 00000000..3a44a0d5 --- /dev/null +++ b/cat_files/default_gemm_configuration.h @@ -0,0 +1,292 @@ +/*************************************************************************************************** + * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ + +/*************************************************************************************************** +* Copyright (c) 2021 Iluvatar CoreX. All rights reserved. +* Copyright Declaration: This software, including all of its code and documentation, +* except for the third-party software it contains, is a copyrighted work of Shanghai Iluvatar CoreX +* Semiconductor Co., Ltd. and its affiliates ("Iluvatar CoreX") in accordance with the PRC Copyright +* Law and relevant international treaties, and all rights contained therein are enjoyed by Iluvatar +* CoreX. No user of this software shall have any right, ownership or interest in this software and +* any use of this software shall be in compliance with the terms and conditions of the End User +* License Agreement. + **************************************************************************************************/ + +/*! \file + \brief Definitions for GEMM structures +*/ + +#pragma once + +#include "cutlass/cutlass.h" +#include "cutlass/numeric_types.h" +#include "cutlass/arch/arch.h" +#include "cutlass/arch/mma.h" + +#include "cutlass/gemm/gemm.h" +#include "cutlass/epilogue/thread/linear_combination.h" +#include "cutlass/epilogue/thread/linear_combination_clamp.h" + +//////////////////////////////////////////////////////////////////////////////// + +namespace cutlass { +namespace gemm { +namespace device { + +//////////////////////////////////////////////////////////////////////////////// + +template < + typename OperatorClass, + typename ArchTag, + typename ElementA, + typename ElementB, + typename ElementC, + typename ElementAccumulator +> +struct DefaultGemmConfiguration; + +//////////////////////////////////////////////////////////////////////////////// + +/// FIXME(Peter Han): Need to update configuration according to perf results, so +/// that could archieve good performance by default. + +template < + typename ArchTag, + typename ElementA, + typename ElementB, + typename ElementC, + typename ElementAccumulator> +struct DefaultGemmConfiguration< + arch::OpClassSimt, + ArchTag, + ElementA, + ElementB, + ElementC, + ElementAccumulator> { + + static int const kAlignmentA = 1; + static int const kAlignmentB = 1; + using ThreadblockShape = GemmShape<128, 128, 8>; + using WarpShape = GemmShape<64, 64, 8>; + using InstructionShape = GemmShape<1, 1, 1>; + static int const kStages = 2; + + using EpilogueOutputOp = epilogue::thread::LinearCombination< + ElementC, + 1, + ElementAccumulator, + ElementAccumulator + >; + + using Operator = arch::OpMultiplyAdd; +}; + +//////////////////////////////////////////////////////////////////////////////// + +template < + typename ArchTag, + typename ElementC> +struct DefaultGemmConfiguration { + + static int const kAlignmentA = 4; + static int const kAlignmentB = 4; + using ThreadblockShape = GemmShape<128, 128, 32>; + using WarpShape = GemmShape<64, 64, 32>; + using InstructionShape = GemmShape<1, 1, 4>; + static int const kStages = 2; + + using EpilogueOutputOp = epilogue::thread::LinearCombinationClamp< + ElementC, + 1, + int32_t, + float + >; + + using Operator = arch::OpMultiplyAdd; +}; + +//////////////////////////////////////////////////////////////////////////////// + +template < + typename ElementC> +struct DefaultGemmConfiguration< + arch::OpClassTensorOp, + arch::Cu10, + int8_t, + int8_t, + ElementC, + int32_t> { + + using ElementA = int8_t; + using ElementB = int8_t; + using ElementAccumulator = int32_t; + static int const kAlignmentA = MEMORY_ACCESS_SIZE / sizeof_bits::value; + static int const kAlignmentB = MEMORY_ACCESS_SIZE / sizeof_bits::value; + + using ThreadblockShape = GemmShape<256, 256, 32>; + using WarpShape = GemmShape<64, 64, 32>; + using InstructionShape = GemmShape<16, 16, 16>; + static int const kStages = 2; + + using EpilogueOutputOp = epilogue::thread::LinearCombination< + ElementC, + MEMORY_ACCESS_SIZE / sizeof_bits::value, + ElementAccumulator, + ElementAccumulator + >; + + using Operator = arch::OpMultiplyAdd; +}; + +template < + typename ElementC> +struct DefaultGemmConfiguration< + arch::OpClassTensorOp, + arch::Cu10, + uint8_t, + uint8_t, + ElementC, + uint32_t> { + + using ElementA = uint8_t; + using ElementB = uint8_t; + using ElementAccumulator = uint32_t; + static int const kAlignmentA = MEMORY_ACCESS_SIZE / sizeof_bits::value; + static int const kAlignmentB = MEMORY_ACCESS_SIZE / sizeof_bits::value; + + using ThreadblockShape = GemmShape<256, 256, 32>; + using WarpShape = GemmShape<64, 64, 32>; + using InstructionShape = GemmShape<16, 16, 16>; + static int const kStages = 2; + + using EpilogueOutputOp = epilogue::thread::LinearCombination< + ElementC, + MEMORY_ACCESS_SIZE / sizeof_bits::value, + ElementAccumulator, + ElementAccumulator + >; + + using Operator = arch::OpMultiplyAdd; +}; + +template < + typename ElementC> +struct DefaultGemmConfiguration< + arch::OpClassTensorOp, + arch::Cu10, + half_t, + half_t, + ElementC, + float> { + + using ElementA = half_t; + using ElementB = half_t; + using ElementAccumulator = float; + static int const kAlignmentA = MEMORY_ACCESS_SIZE / sizeof_bits::value; + static int const kAlignmentB = MEMORY_ACCESS_SIZE / sizeof_bits::value; + + using ThreadblockShape = GemmShape<128, 128, 32>; + using WarpShape = GemmShape<32, 32, 32>; + using InstructionShape = GemmShape<16, 16, 16>; + static int const kStages = 2; + + using EpilogueOutputOp = epilogue::thread::LinearCombination< + ElementC, + MEMORY_ACCESS_SIZE / sizeof_bits::value, + ElementAccumulator, + ElementAccumulator + >; + + using Operator = arch::OpMultiplyAdd; +}; + +template < + typename ElementC> +struct DefaultGemmConfiguration< + arch::OpClassTensorOp, + arch::Cu10, + bfloat16_t, + bfloat16_t, + ElementC, + float> { + + using ElementA = bfloat16_t; + using ElementB = bfloat16_t; + using ElementAccumulator = float; + static int const kAlignmentA = 32 / sizeof_bits::value; + static int const kAlignmentB = 32 / sizeof_bits::value; + + using ThreadblockShape = GemmShape<128, 128, 32>; + using WarpShape = GemmShape<32, 32, 32>; + using InstructionShape = GemmShape<16, 16, 16>; + static int const kStages = 2; + + using EpilogueOutputOp = epilogue::thread::LinearCombination< + ElementC, + MEMORY_ACCESS_SIZE / sizeof_bits::value, + ElementAccumulator, + ElementAccumulator + >; + + using Operator = arch::OpMultiplyAdd; +}; + +template < + typename ElementC> +struct DefaultGemmConfiguration< + arch::OpClassTensorOp, + arch::Cu10, + float, + float, + ElementC, + float> { + + using ElementA = float; + using ElementB = float; + using ElementAccumulator = float; + static int const kAlignmentA = 32 / sizeof_bits::value; + static int const kAlignmentB = 32 / sizeof_bits::value; + + using ThreadblockShape = GemmShape<128, 128, 32>; + using WarpShape = GemmShape<32, 32, 32>; + using InstructionShape = GemmShape<16, 16, 16>; + static int const kStages = 2; + + using EpilogueOutputOp = epilogue::thread::LinearCombination< + ElementC, + MEMORY_ACCESS_SIZE / sizeof_bits::value, + ElementAccumulator, + ElementAccumulator + >; + + using Operator = arch::OpMultiplyAdd; +}; + +//////////////////////////////////////////////////////////////////////////////// +} // namespace device +} // namespace gemm +} // namespace cutlass + +//////////////////////////////////////////////////////////////////////////////// diff --git a/cat_files/default_gemm_universal.h b/cat_files/default_gemm_universal.h new file mode 100644 index 00000000..1e77a06a --- /dev/null +++ b/cat_files/default_gemm_universal.h @@ -0,0 +1,307 @@ +/*************************************************************************************************** + * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ + +/*! \file + \brief + Default kernel-level GEMM definitions combine threadblock-scoped matrix multiply-add with + the appropriate threadblock-scoped epilogue. + + Note, CUTLASS epilogues universally target row-major outputs. Column-major outputs are + accommodated by exchanging A and B operands and assuming transposed layouts. Partial + specializations here choose 'device::GemmTransposed' to implement this functionality. + +*/ + +#pragma once + +#include "cutlass/cutlass.h" + +#include "cutlass/complex.h" +#include "cutlass/layout/matrix.h" +#include "cutlass/numeric_types.h" + +#include "cutlass/gemm/kernel/gemm_universal.h" +#include "cutlass/gemm/kernel/default_gemm.h" +#include "cutlass/gemm/kernel/default_gemm_complex.h" + +///////////////////////////////////////////////////////////////////////////////////////////////// + +namespace cutlass { +namespace gemm { +namespace kernel { + +///////////////////////////////////////////////////////////////////////////////////////////////// + +template < + /// Element type for A matrix operand + typename ElementA_, + /// Layout type for A matrix operand + typename LayoutA_, + /// Complex elementwise transformation on A operand + ComplexTransform TransformA, + /// Access granularity of A matrix in units of elements + int kAlignmentA, + /// Element type for B matrix operand + typename ElementB_, + /// Layout type for B matrix operand + typename LayoutB_, + /// Complex elementwise transformation on B operand + ComplexTransform TransformB, + /// Access granularity of B matrix in units of elements + int kAlignmentB, + /// Element type for C and D matrix operands + typename ElementC_, + /// Layout type for C and D matrix operands + typename LayoutC_, + /// Element type for internal accumulation + typename ElementAccumulator, + /// Operator class tag + typename OperatorClass, + /// Tag indicating architecture to tune for + typename ArchTag, + /// Threadblock-level tile size (concept: GemmShape) + typename ThreadblockShape, + /// Warp-level tile size (concept: GemmShape) + typename WarpShape, + /// Warp-level tile size (concept: GemmShape) + typename InstructionShape, + /// Epilogue output operator + typename EpilogueOutputOp, + /// Threadblock-level swizzling operator + typename ThreadblockSwizzle, + /// Number of stages used in the pipelined mainloop + int Stages, + /// Operation performed by GEMM + typename Operator, + /// + typename Enable = void + > +struct DefaultGemmUniversal; + +///////////////////////////////////////////////////////////////////////////////////////////////// +// +// Real-valued GEMM kernels +// + +template < + /// Element type for A matrix operand + typename ElementA, + /// Layout type for A matrix operand + typename LayoutA, + /// Access granularity of A matrix in units of elements + int kAlignmentA, + /// Element type for B matrix operand + typename ElementB, + /// Layout type for B matrix operand + typename LayoutB, + /// Access granularity of B matrix in units of elements + int kAlignmentB, + /// Element type for C and D matrix operands + typename ElementC, + /// Layout type for C and D matrix operands + typename LayoutC, + /// Element type for internal accumulation + typename ElementAccumulator, + /// Operator class tag + typename OperatorClass, + /// Tag indicating architecture to tune for + typename ArchTag, + /// Threadblock-level tile size (concept: GemmShape) + typename ThreadblockShape, + /// Warp-level tile size (concept: GemmShape) + typename WarpShape, + /// Instruction-level tile size (concept: GemmShape) + typename InstructionShape, + /// Epilogue output operator + typename EpilogueOutputOp, + /// Threadblock-level swizzling operator + typename ThreadblockSwizzle, + /// Number of stages used in the pipelined mainloop + int Stages, + /// Operation performed by GEMM + typename Operator> +struct DefaultGemmUniversal< + ElementA, + LayoutA, + ComplexTransform::kNone, // transform A + kAlignmentA, + ElementB, + LayoutB, + ComplexTransform::kNone, // transform B + kAlignmentB, + ElementC, + LayoutC, + ElementAccumulator, + OperatorClass, + ArchTag, + ThreadblockShape, + WarpShape, + InstructionShape, + EpilogueOutputOp, + ThreadblockSwizzle, + Stages, + Operator, + typename std::enable_if< ! cutlass::is_complex::value>::type +> { + + using DefaultGemmKernel = typename kernel::DefaultGemm< + ElementA, + LayoutA, + kAlignmentA, + ElementB, + LayoutB, + kAlignmentB, + ElementC, + LayoutC, + ElementAccumulator, + OperatorClass, + ArchTag, + ThreadblockShape, + WarpShape, + InstructionShape, + EpilogueOutputOp, + ThreadblockSwizzle, + Stages, + true, + Operator + >::GemmKernel; + + /// Define the kernel in terms of the default kernel + using GemmKernel = kernel::GemmUniversal< + typename DefaultGemmKernel::Mma, + typename DefaultGemmKernel::Epilogue, + ThreadblockSwizzle + >; +}; + +///////////////////////////////////////////////////////////////////////////////////////////////// + +// +// Complex-valued GEMM kernels +// + +template < + /// Element type for A matrix operand + typename ElementA, + /// Layout type for A matrix operand + typename LayoutA, + /// Complex elementwise transformation on A operand + ComplexTransform TransformA, + /// Access granularity of A matrix in units of elements + int kAlignmentA, + /// Element type for B matrix operand + typename ElementB, + /// Layout type for B matrix operand + typename LayoutB, + /// Complex elementwise transformation on B operand + ComplexTransform TransformB, + /// Access granularity of B matrix in units of elements + int kAlignmentB, + /// Element type for C and D matrix operands + typename ElementC, + /// Layout type for C and D matrix operands + typename LayoutC, + /// Element type for internal accumulation + typename ElementAccumulator, + /// Operator class tag + typename OperatorClass, + /// Tag indicating architecture to tune for + typename ArchTag, + /// Threadblock-level tile size (concept: GemmShape) + typename ThreadblockShape, + /// Warp-level tile size (concept: GemmShape) + typename WarpShape, + /// Warp-level tile size (concept: GemmShape) + typename InstructionShape, + /// Epilogue output operator + typename EpilogueOutputOp, + /// Threadblock-level swizzling operator + typename ThreadblockSwizzle, + /// Number of stages used in the pipelined mainloop + int Stages, + /// Operation performed by GEMM + typename Operator + > +struct DefaultGemmUniversal< + ElementA, + LayoutA, + TransformA, + kAlignmentA, + ElementB, + LayoutB, + TransformB, + kAlignmentB, + ElementC, + LayoutC, + ElementAccumulator, + OperatorClass, + ArchTag, + ThreadblockShape, + WarpShape, + InstructionShape, + EpilogueOutputOp, + ThreadblockSwizzle, + Stages, + Operator, + typename std::enable_if::value>::type +> { + + using DefaultGemmKernel = typename kernel::DefaultGemmComplex< + ElementA, + LayoutA, + ElementB, + LayoutB, + ElementC, + LayoutC, + ElementAccumulator, + OperatorClass, + ArchTag, + ThreadblockShape, + WarpShape, + InstructionShape, + EpilogueOutputOp, + ThreadblockSwizzle, + Stages, + TransformA, + TransformB, + Operator, + false + >::GemmKernel; + + /// Define the kernel in terms of the default kernel + using GemmKernel = kernel::GemmUniversal< + typename DefaultGemmKernel::Mma, + typename DefaultGemmKernel::Epilogue, + ThreadblockSwizzle + >; +}; + +///////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace kernel +} // namespace gemm +} // namespace cutlass + +///////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/cat_files/default_mma_core.h b/cat_files/default_mma_core.h new file mode 100644 index 00000000..f693c2fb --- /dev/null +++ b/cat_files/default_mma_core.h @@ -0,0 +1,114 @@ +/*************************************************************************************************** + * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ + +/*************************************************************************************************** +* Copyright (c) 2021 Iluvatar CoreX. All rights reserved. +* Copyright Declaration: This software, including all of its code and documentation, +* except for the third-party software it contains, is a copyrighted work of Shanghai Iluvatar CoreX +* Semiconductor Co., Ltd. and its affiliates ("Iluvatar CoreX") in accordance with the PRC Copyright +* Law and relevant international treaties, and all rights contained therein are enjoyed by Iluvatar +* CoreX. No user of this software shall have any right, ownership or interest in this software and +* any use of this software shall be in compliance with the terms and conditions of the End User +* License Agreement. + **************************************************************************************************/ + +/*! \file + \brief Defines basic properties needed by CTA-level GEMMs assuming expectations about data + layout of the global memory fragments, data types, and internal tile sizes. + + Partial specializations for threadblock::Mma operations targeting TensorOp instructions. +*/ + +#pragma once + +#include "cutlass/cutlass.h" +#include "cutlass/array.h" + +#include "cutlass/numeric_types.h" +#include "cutlass/matrix_shape.h" + +#include "cutlass/gemm/warp/mma.h" +#include "cutlass/gemm/threadblock/mma_pipelined.h" +#include "cutlass/gemm/threadblock/mma_singlestage.h" +#include "cutlass/gemm/threadblock/mma_preload.h" +#include "cutlass/arch/cache_operation.h" + +///////////////////////////////////////////////////////////////////////////////////////////////// + +namespace cutlass { +namespace gemm { +namespace threadblock { + +///////////////////////////////////////////////////////////////////////////////////////////////// + +/// Template defininng default matrix multiply operators inferred from threadblock tile size, +/// global memory data layout, and target math instruction. +template < + /// Shape of threadblock-scoped matrix multiply operator + typename Shape, + /// Shape of warp-level matrix multiply operator + typename WarpShape, + /// Shape of one matrix production operation (concept: GemmShape) + typename InstructionShape, + /// Element data type of A operand + typename ElementA, + /// Layout of operand A + typename LayoutA, + /// Element data type of B operand + typename ElementB, + /// Layout of operand B + typename LayoutB, + /// Data type of accumulator + typename ElementC, + /// Layout of accumulator + typename LayoutC, + /// Indicates type of math operator (arch::OpClassSimt or arch::OpClassTensorOp) + typename OperatorClass, + /// Number of stages + int Stages = 2, + /// Operation performed by MMA + typename Operator = cutlass::arch::OpMultiplyAdd, + /// Store the accumulators in row major or column major. Row major is used + /// when output layout is interleaved. + bool AccumulatorsInRowMajor = false, + /// Cache operation of operand A + cutlass::arch::CacheOperation::Kind CacheOpA = + cutlass::arch::CacheOperation::Global, + /// Cache operation of operand B + cutlass::arch::CacheOperation::Kind CacheOpB = + cutlass::arch::CacheOperation::Global, + /// per-element transformation for elements of A + ComplexTransform TransformA = ComplexTransform::kNone, + /// per-element transformation for elements of B + ComplexTransform TransformB = ComplexTransform::kNone, + bool IsComplex = false // (is_complex::value || is_complex::value) +> +struct DefaultMmaCore; + +///////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace threadblock +} // namespace gemm +} // namespace cutlass diff --git a/cat_files/default_mma_core_cu10.h b/cat_files/default_mma_core_cu10.h new file mode 100644 index 00000000..fb94d88e --- /dev/null +++ b/cat_files/default_mma_core_cu10.h @@ -0,0 +1,835 @@ +/*************************************************************************************************** + * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ + +/*************************************************************************************************** +* Copyright (c) 2021 Iluvatar CoreX. All rights reserved. +* Copyright Declaration: This software, including all of its code and documentation, +* except for the third-party software it contains, is a copyrighted work of Shanghai Iluvatar CoreX +* Semiconductor Co., Ltd. and its affiliates ("Iluvatar CoreX") in accordance with the PRC Copyright +* Law and relevant international treaties, and all rights contained therein are enjoyed by Iluvatar +* CoreX. No user of this software shall have any right, ownership or interest in this software and +* any use of this software shall be in compliance with the terms and conditions of the End User +* License Agreement. + **************************************************************************************************/ + +/*! \file + \brief Defines basic properties needed by CTA-level GEMMs assuming expectations about data + layout of the global memory fragments, data types, and internal tile sizes. + + Partial specializations for threadblock::Mma operations targeting TensorOp instructions. + + Aims at TensorOp of the first generation BigIsland. +*/ + +#pragma once + +#include "cutlass/cutlass.h" +#include "cutlass/array.h" + +#include "cutlass/numeric_types.h" +#include "cutlass/matrix_shape.h" + +#include "cutlass/transform/pitch_linear_thread_map.h" +#include "cutlass/transform/threadblock/regular_tile_access_iterator_tensor_op.h" +#include "cutlass/transform/threadblock/regular_tile_iterator_tensor_op.h" +#include "cutlass/layout/tensor_op_multiplicand.h" +#include "cutlass/layout/tensor_op_em.h" + +#include "cutlass/gemm/warp/mma_tensor_op_policy.h" +#include "cutlass/gemm/warp/mma_tensor_op.h" +#include "cutlass/gemm/warp/default_mma_tensor_op.h" +#include "cutlass/gemm/threadblock/default_mma_core.h" + +///////////////////////////////////////////////////////////////////////////////////////////////// + +namespace cutlass { +namespace gemm { +namespace threadblock { + +///////////////////////////////////////////////////////////////////////////////////////////////// +/// +/// Specialization: A: row-major, B: row-major, TT +/// +/// This uses the default warp-level operator given tile sizes +/// +template < + /// Shape of threadblock-scoped matrix multiply operator (concept: + /// GemmShape) + typename Shape_, + /// Shape of warp-level matrix multiply operator (concept: GemmShape) + typename WarpShape_, + /// Data type of A operand + typename ElementA_, + /// Data type of B operand + typename ElementB_, + /// Data type of accumulator + typename ElementC_, + /// Layout of accumulator + typename LayoutC_, + /// Stages + int Stages, + /// Operation performed by GEMM + typename Operator_> +struct DefaultMmaCore, + ElementA_, + layout::RowMajor, + ElementB_, + layout::RowMajor, + ElementC_, + LayoutC_, + arch::OpClassTensorOp, + Stages, + Operator_> { + using Shape = Shape_; + using WarpShape = WarpShape_; + using InstructionShape = GemmShape<16, 16, 16>; + using ElementA = ElementA_; + using LayoutA = layout::RowMajor; + using ElementB = ElementB_; + using LayoutB = layout::RowMajor; + using ElementC = ElementC_; + using LayoutC = LayoutC_; + using OperatorClass = arch::OpClassTensorOp; + + static int const kStages = Stages; + + /// Default Operator + using Operator = Operator_; + + /// Warp thread arrangement + using WarpThreadArrangement = layout::PitchLinearShape<16, 4>; + + /// Number of warps present + using WarpCount = GemmShape< + Shape::kM / WarpShape::kM, + Shape::kN / WarpShape::kN, + Shape::kK / WarpShape::kK + >; + + /// Don't support split K within CTA + static_assert(Shape::kK == WarpShape::kK, + "Threadblock-scoped GEMM shape K should equal warp-scoped GEMM shape K" + ); + + // Divisibility requirements + static_assert( + !(Shape::kM % WarpShape::kM) && + !(Shape::kN % WarpShape::kN) && + !(Shape::kK % WarpShape::kK), + "Threadblock-scoped GEMM should be divisible by warp-scoped GEMM size." + ); + + // Divisibility requirements + static_assert( + !(WarpShape::kM % 16) && + !(WarpShape::kN % 16) && + !(WarpShape::kK % 16), + "Threadblock-scoped GEMM should be divisible by 16." + ); + + /// Number of threads per warp + static int const kWarpSize = warp::WarpSize::value; + + /// Number of threads total + static int const kThreads = WarpCount::kCount * kWarpSize; + + /// Size of a threadblock-scoped access + static int const kAccessSizeInBits = 32; + + /// Number of A elemnts per access + static int const kElementsPerAccessA = kAccessSizeInBits / sizeof_bits::value; + + /// Number of A elemnts per access + static int const kElementsPerAccessB = kAccessSizeInBits / sizeof_bits::value; + + // + // Shared memory layouts + // + + #if BLOCK_LOAD_STORE + using SmemLayoutA = layout::TensorOpEm::value, LayoutA>; + using SmemLayoutB = layout::TensorOpEm::value, LayoutB>; + #else + using SmemLayoutA = layout::TensorOpMultiplicand::value, LayoutA>; + using SmemLayoutB = layout::TensorOpMultiplicand::value, LayoutB>; + #endif + + // + // Iterators to write to shared memory + // + + /// ThreadMap of iterator A + /// + using IteratorThreadMapA = transform::PitchLinear2DThreadTileWarpRakedThreadMap< + layout::PitchLinearShape, + kThreads, + WarpThreadArrangement, + layout::PitchLinearShape + >; + + /// Shared memory iterator to A operand + using SmemIteratorA = transform::threadblock::RegularTileIterator< + MatrixShape, + ElementA, + SmemLayoutA, + 1, + IteratorThreadMapA + >; + + /// Policy of iterator B + using IteratorThreadMapB = transform::PitchLinear2DThreadTileWarpRakedThreadMap< + layout::PitchLinearShape, + kThreads, + WarpThreadArrangement, + layout::PitchLinearShape + >; + + /// Shared memory iterator to B operand + using SmemIteratorB = transform::threadblock::RegularTileIterator< + MatrixShape, + ElementB, + SmemLayoutB, + 0, + IteratorThreadMapB + >; + + // + // Warp-level matrix multiply operator + // + + // Define the warp-level tensor op + using Policy = gemm::warp::MmaTensorOpPolicy< + arch::Mma< + gemm::GemmShape<16, 16, 16>, + NUM_THREADS_PER_WARP, + ElementA, + LayoutA, + ElementB, + LayoutB, + ElementC, + layout::RowMajor, + arch::OpMultiplyAdd + >, + MatrixShape<1, 1> + >; + + using MmaTensorOp = typename gemm::warp::DefaultMmaTensorOp< + WarpShape, + gemm::GemmShape<16, 16, 16>, + ElementA, + SmemLayoutA, + ElementB, + SmemLayoutB, + ElementC, + LayoutC, + arch::OpMultiplyAdd + >::Type; + + /// Policy used to define MmaPipelined + using MmaPolicy = MmaPolicy< + MmaTensorOp, + MatrixShape<0, 0>, + MatrixShape<0, 0>, + WarpCount::kK + >; +}; + +///////////////////////////////////////////////////////////////////////////////////////////////// +/// +/// Specialization: A: row-major, B: column-major, TN +/// +/// This uses the default warp-level operator given tile sizes +/// +template < + /// Shape of threadblock-scoped matrix multiply operator (concept: + /// GemmShape) + typename Shape_, + /// Shape of warp-level matrix multiply operator (concept: GemmShape) + typename WarpShape_, + /// Data type of A operand + typename ElementA_, + /// Data type of B operand + typename ElementB_, + /// Data type of accumulator + typename ElementC_, + /// Layout of accumulator + typename LayoutC_, + /// Stages + int Stages, + /// Operation performed by GEMM + typename Operator_> +struct DefaultMmaCore, + ElementA_, + layout::RowMajor, + ElementB_, + layout::ColumnMajor, + ElementC_, + LayoutC_, + arch::OpClassTensorOp, + Stages, + Operator_> { + using Shape = Shape_; + using WarpShape = WarpShape_; + using InstructionShape = GemmShape<16, 16, 16>; + using ElementA = ElementA_; + using LayoutA = layout::RowMajor; + using ElementB = ElementB_; + using LayoutB = layout::ColumnMajor; + using ElementC = ElementC_; + using LayoutC = LayoutC_; + using OperatorClass = arch::OpClassTensorOp; + + static int const kStages = Stages; + + /// Default Operator + using Operator = Operator_; + + /// Warp thread arrangement + using WarpThreadArrangement = layout::PitchLinearShape<16, 4>; + + /// Number of warps present + using WarpCount = GemmShape< + Shape::kM / WarpShape::kM, + Shape::kN / WarpShape::kN, + Shape::kK / WarpShape::kK + >; + + /// Don't support split K within CTA + static_assert(Shape::kK == WarpShape::kK, + "Threadblock-scoped GEMM shape K should equal warp-scoped GEMM shape K" + ); + + // Divisibility requirements + static_assert( + !(Shape::kM % WarpShape::kM) && + !(Shape::kN % WarpShape::kN) && + !(Shape::kK % WarpShape::kK), + "Threadblock-scoped GEMM should be divisible by warp-scoped GEMM size." + ); + + // Divisibility requirements + static_assert( + !(WarpShape::kM % 16) && + !(WarpShape::kN % 16) && + !(WarpShape::kK % 16), + "Threadblock-scoped GEMM should be divisible by 16." + ); + + /// Number of threads per warp + static int const kWarpSize = warp::WarpSize::value; + + /// Number of threads total + static int const kThreads = WarpCount::kCount * kWarpSize; + + /// Size of a threadblock-scoped access + static int const kAccessSizeInBits = 32; + + /// Number of A elemnts per access + static int const kElementsPerAccessA = kAccessSizeInBits / sizeof_bits::value; + + /// Number of A elemnts per access + static int const kElementsPerAccessB = kAccessSizeInBits / sizeof_bits::value; + + // + // Shared memory layouts + // + + #if BLOCK_LOAD_STORE + using SmemLayoutA = layout::TensorOpEm::value, LayoutA>; + using SmemLayoutB = layout::TensorOpMultiplicand::value, LayoutB>; + #else + using SmemLayoutA = layout::TensorOpMultiplicand::value, LayoutA>; + using SmemLayoutB = layout::TensorOpMultiplicand::value, LayoutB>; + #endif + + // + + // + // Iterators to write to shared memory + // + + /// ThreadMap of iterator A + /// + using IteratorThreadMapA = transform::PitchLinear2DThreadTileWarpRakedThreadMap< + layout::PitchLinearShape, + kThreads, + WarpThreadArrangement, + layout::PitchLinearShape + >; + + /// Shared memory iterator to A operand + using SmemIteratorA = transform::threadblock::RegularTileIterator< + MatrixShape, + ElementA, + SmemLayoutA, + 1, + IteratorThreadMapA + >; + + /// Policy of iterator B + using IteratorThreadMapB = transform::PitchLinear2DThreadTileWarpRakedThreadMap< + layout::PitchLinearShape, + kThreads, + WarpThreadArrangement, + layout::PitchLinearShape + >; + + /// Shared memory iterator to B operand + using SmemIteratorB = transform::threadblock::RegularTileIterator< + MatrixShape, + ElementB, + SmemLayoutB, + 0, + IteratorThreadMapB + >; + + // + // Warp-level matrix multiply operator + // + + // Define the warp-level tensor op + using Policy = gemm::warp::MmaTensorOpPolicy< + arch::Mma< + gemm::GemmShape<16, 16, 16>, + NUM_THREADS_PER_WARP, + ElementA, + LayoutA, + ElementB, + LayoutB, + ElementC, + layout::RowMajor, + arch::OpMultiplyAdd + >, + MatrixShape<1, 1> + >; + + using MmaTensorOp = typename gemm::warp::DefaultMmaTensorOp< + WarpShape, + gemm::GemmShape<16, 16, 16>, + ElementA, + SmemLayoutA, + ElementB, + SmemLayoutB, + ElementC, + LayoutC, + arch::OpMultiplyAdd + >::Type; + + /// Policy used to define MmaPipelined + using MmaPolicy = MmaPolicy< + MmaTensorOp, + MatrixShape<0, 0>, + MatrixShape<0, 0>, + WarpCount::kK + >; +}; + +///////////////////////////////////////////////////////////////////////////////////////////////// +/// +/// Specialization: A: column-major, B: row-major, NT +/// +/// This uses the default warp-level operator given tile sizes +/// +template < + /// Shape of threadblock-scoped matrix multiply operator (concept: + /// GemmShape) + typename Shape_, + /// Shape of warp-level matrix multiply operator (concept: GemmShape) + typename WarpShape_, + /// Data type of A operand + typename ElementA_, + /// Data type of B operand + typename ElementB_, + /// Data type of accumulator + typename ElementC_, + /// Layout of accumulator + typename LayoutC_, + /// Stages + int Stages, + /// Operation performed by GEMM + typename Operator_> +struct DefaultMmaCore, + ElementA_, + layout::ColumnMajor, + ElementB_, + layout::RowMajor, + ElementC_, + LayoutC_, + arch::OpClassTensorOp, + Stages, + Operator_> { + using Shape = Shape_; + using WarpShape = WarpShape_; + using InstructionShape = GemmShape<16, 16, 16>; + using ElementA = ElementA_; + using LayoutA = layout::ColumnMajor; + using ElementB = ElementB_; + using LayoutB = layout::RowMajor; + using ElementC = ElementC_; + using LayoutC = LayoutC_; + using OperatorClass = arch::OpClassTensorOp; + + static int const kStages = Stages; + + /// Default Operator + using Operator = Operator_; + + /// Warp thread arrangement + using WarpThreadArrangement = layout::PitchLinearShape<16, 4>; + + /// Number of warps present + using WarpCount = GemmShape< + Shape::kM / WarpShape::kM, + Shape::kN / WarpShape::kN, + Shape::kK / WarpShape::kK + >; + + /// Don't support split K within CTA + static_assert(Shape::kK == WarpShape::kK, + "Threadblock-scoped GEMM shape K should equal warp-scoped GEMM shape K" + ); + + // Divisibility requirements + static_assert( + !(Shape::kM % WarpShape::kM) && + !(Shape::kN % WarpShape::kN) && + !(Shape::kK % WarpShape::kK), + "Threadblock-scoped GEMM should be divisible by warp-scoped GEMM size." + ); + + // Divisibility requirements + static_assert( + !(WarpShape::kM % 16) && + !(WarpShape::kN % 16) && + !(WarpShape::kK % 16), + "Threadblock-scoped GEMM should be divisible by 16." + ); + + /// Number of threads per warp + static int const kWarpSize = warp::WarpSize::value; + + /// Number of threads total + static int const kThreads = WarpCount::kCount * kWarpSize; + + /// Size of a threadblock-scoped access + static int const kAccessSizeInBits = 32; + + /// Number of A elemnts per access + static int const kElementsPerAccessA = kAccessSizeInBits / sizeof_bits::value; + + /// Number of A elemnts per access + static int const kElementsPerAccessB = kAccessSizeInBits / sizeof_bits::value; + + // + // Shared memory layouts + // + + #if BLOCK_LOAD_STORE + using SmemLayoutA = layout::TensorOpMultiplicand::value, LayoutA>; + using SmemLayoutB = layout::TensorOpEm::value, LayoutB>; + #else + using SmemLayoutA = layout::TensorOpMultiplicand::value, LayoutA>; + using SmemLayoutB = layout::TensorOpMultiplicand::value, LayoutB>; + #endif + + // + // Iterators to write to shared memory + // + + /// ThreadMap of iterator A + /// + using IteratorThreadMapA = transform::PitchLinear2DThreadTileWarpRakedThreadMap< + layout::PitchLinearShape, + kThreads, + WarpThreadArrangement, + layout::PitchLinearShape + >; + + /// Shared memory iterator to A operand + using SmemIteratorA = transform::threadblock::RegularTileIterator< + MatrixShape, + ElementA, + SmemLayoutA, + 1, + IteratorThreadMapA + >; + + /// Policy of iterator B + using IteratorThreadMapB = transform::PitchLinear2DThreadTileWarpRakedThreadMap< + layout::PitchLinearShape, + kThreads, + WarpThreadArrangement, + layout::PitchLinearShape + >; + + /// Shared memory iterator to B operand + using SmemIteratorB = transform::threadblock::RegularTileIterator< + MatrixShape, + ElementB, + SmemLayoutB, + 0, + IteratorThreadMapB + >; + + // + // Warp-level matrix multiply operator + // + + // Define the warp-level tensor op + using Policy = gemm::warp::MmaTensorOpPolicy< + arch::Mma< + gemm::GemmShape<16, 16, 16>, + NUM_THREADS_PER_WARP, + ElementA, + LayoutA, + ElementB, + LayoutB, + ElementC, + layout::RowMajor, + arch::OpMultiplyAdd + >, + MatrixShape<1, 1> + >; + + using MmaTensorOp = typename gemm::warp::DefaultMmaTensorOp< + WarpShape, + gemm::GemmShape<16, 16, 16>, + ElementA, + SmemLayoutA, + ElementB, + SmemLayoutB, + ElementC, + LayoutC, + arch::OpMultiplyAdd + >::Type; + + /// Policy used to define MmaPipelined + using MmaPolicy = MmaPolicy< + MmaTensorOp, + MatrixShape<0, 0>, + MatrixShape<0, 0>, + WarpCount::kK + >; +}; + +///////////////////////////////////////////////////////////////////////////////////////////////// +/// +/// Specialization: A: column-major, B: column-major, NN +/// +/// This uses the default warp-level operator given tile sizes +/// +template < + /// Shape of threadblock-scoped matrix multiply operator (concept: + /// GemmShape) + typename Shape_, + /// Shape of warp-level matrix multiply operator (concept: GemmShape) + typename WarpShape_, + /// Data type of A operand + typename ElementA_, + /// Data type of B operand + typename ElementB_, + /// Data type of accumulator + typename ElementC_, + /// Layout of accumulator + typename LayoutC_, + /// Stages + int Stages, + /// Operation performed by GEMM + typename Operator_> +struct DefaultMmaCore, + ElementA_, + layout::ColumnMajor, + ElementB_, + layout::ColumnMajor, + ElementC_, + LayoutC_, + arch::OpClassTensorOp, + Stages, + Operator_> { + using Shape = Shape_; + using WarpShape = WarpShape_; + using InstructionShape = GemmShape<16, 16, 16>; + using ElementA = ElementA_; + using LayoutA = layout::ColumnMajor; + using ElementB = ElementB_; + using LayoutB = layout::ColumnMajor; + using ElementC = ElementC_; + using LayoutC = LayoutC_; + using OperatorClass = arch::OpClassTensorOp; + + static int const kStages = Stages; + + /// Default Operator + using Operator = Operator_; + + /// Warp thread arrangement + using WarpThreadArrangement = layout::PitchLinearShape<16, 4>; + + /// Number of warps present + using WarpCount = GemmShape< + Shape::kM / WarpShape::kM, + Shape::kN / WarpShape::kN, + Shape::kK / WarpShape::kK + >; + + /// Don't support split K within CTA + static_assert(Shape::kK == WarpShape::kK, + "Threadblock-scoped GEMM shape K should equal warp-scoped GEMM shape K" + ); + + // Divisibility requirements + static_assert( + !(Shape::kM % WarpShape::kM) && + !(Shape::kN % WarpShape::kN) && + !(Shape::kK % WarpShape::kK), + "Threadblock-scoped GEMM should be divisible by warp-scoped GEMM size." + ); + + // Divisibility requirements + static_assert( + !(WarpShape::kM % 16) && + !(WarpShape::kN % 16) && + !(WarpShape::kK % 16), + "Threadblock-scoped GEMM should be divisible by 16." + ); + + /// Number of threads per warp + static int const kWarpSize = warp::WarpSize::value; + + /// Number of threads total + static int const kThreads = WarpCount::kCount * kWarpSize; + + /// Size of a threadblock-scoped access + static int const kAccessSizeInBits = 32; + + /// Number of A elemnts per access + static int const kElementsPerAccessA = kAccessSizeInBits / sizeof_bits::value; + + /// Number of A elemnts per access + static int const kElementsPerAccessB = kAccessSizeInBits / sizeof_bits::value; + + // + // Shared memory layouts + // + using SmemLayoutA = layout::TensorOpMultiplicand::value, LayoutA>; + using SmemLayoutB = layout::TensorOpMultiplicand::value, LayoutB>; + + // + + // + // Iterators to write to shared memory + // + + /// ThreadMap of iterator A + /// + using IteratorThreadMapA = transform::PitchLinear2DThreadTileWarpRakedThreadMap< + layout::PitchLinearShape, + kThreads, + WarpThreadArrangement, + layout::PitchLinearShape + >; + + /// Shared memory iterator to A operand + using SmemIteratorA = transform::threadblock::RegularTileIterator< + MatrixShape, + ElementA, + SmemLayoutA, + 1, + IteratorThreadMapA + >; + + /// Policy of iterator B + using IteratorThreadMapB = transform::PitchLinear2DThreadTileWarpRakedThreadMap< + layout::PitchLinearShape, + kThreads, + WarpThreadArrangement, + layout::PitchLinearShape + >; + + /// Shared memory iterator to B operand + using SmemIteratorB = transform::threadblock::RegularTileIterator< + MatrixShape, + ElementB, + SmemLayoutB, + 0, + IteratorThreadMapB + >; + + // + // Warp-level matrix multiply operator + // + + // Define the warp-level tensor op + using Policy = gemm::warp::MmaTensorOpPolicy< + arch::Mma< + gemm::GemmShape<16, 16, 16>, + NUM_THREADS_PER_WARP, + ElementA, + LayoutA, + ElementB, + LayoutB, + ElementC, + layout::RowMajor, + arch::OpMultiplyAdd + >, + MatrixShape<1, 1> + >; + + using MmaTensorOp = typename gemm::warp::DefaultMmaTensorOp< + WarpShape, + gemm::GemmShape<16, 16, 16>, + ElementA, + SmemLayoutA, + ElementB, + SmemLayoutB, + ElementC, + LayoutC, + arch::OpMultiplyAdd + >::Type; + + /// Policy used to define MmaPipelined + using MmaPolicy = MmaPolicy< + MmaTensorOp, + MatrixShape<0, 0>, + MatrixShape<0, 0>, + WarpCount::kK + >; +}; + +///////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace threadblock +} // namespace gemm +} // namespace cutlass + +///////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/cat_files/default_mma_tensor_op.h b/cat_files/default_mma_tensor_op.h new file mode 100644 index 00000000..f315fecc --- /dev/null +++ b/cat_files/default_mma_tensor_op.h @@ -0,0 +1,148 @@ +/*************************************************************************************************** + * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ + +/*************************************************************************************************** +* Copyright (c) 2021 Iluvatar CoreX. All rights reserved. +* Copyright Declaration: This software, including all of its code and documentation, +* except for the third-party software it contains, is a copyrighted work of Shanghai Iluvatar CoreX +* Semiconductor Co., Ltd. and its affiliates ("Iluvatar CoreX") in accordance with the PRC Copyright +* Law and relevant international treaties, and all rights contained therein are enjoyed by Iluvatar +* CoreX. No user of this software shall have any right, ownership or interest in this software and +* any use of this software shall be in compliance with the terms and conditions of the End User +* License Agreement. + **************************************************************************************************/ + +/*! \file + \brief Default warp-level GEMM operators selected by data type, size, and layouts of operands. +*/ + +#pragma once + +#include "cutlass/cutlass.h" +#include "cutlass/gemm/warp/mma_tensor_op.h" + +namespace cutlass { +namespace gemm { +namespace warp { + +///////////////////////////////////////////////////////////////////////////////////////////////// + +template < + /// Size of the Gemm problem - concept: gemm::GemmShape<> + typename WarpShape_, + /// Shape of one matrix production operation (concept: GemmShape) + typename InstructionShape_, + /// Data type of A elements + typename ElementA_, + /// Layout of A matrix (concept: MatrixLayout) + typename LayoutA_, + /// Data type of B elements + typename ElementB_, + /// Layout of B matrix (concept: MatrixLayout) + typename LayoutB_, + /// Element type of C matrix + typename ElementC_, + /// Layout of C matrix (concept: MatrixLayout) + typename LayoutC_, + /// Operator describing the tensor operation + typename Operator_ = arch::OpMultiplyAdd, + /// Number of partitions along K dimension + int PartitionsK = 1, + /// Store the accumulators in row major or column major. + bool AccumulatorsInRowMajor = true> +struct DefaultMmaTensorOp; + +///////////////////////////////////////////////////////////////////////////////////////////////// + +/// Partial specialization for m-by-n-by-kgroup +template < + /// Shape of one matrix production operation (concept: GemmShape) + typename WarpShape_, + /// Data type of A elements + typename ElementA, + /// Layout of A matrix (concept: MatrixLayout) + typename LayoutA, + /// Data type of B elements + typename ElementB, + /// Layout of B matrix (concept: MatrixLayout) + typename LayoutB, + /// Element type of C matrix + typename ElementC, + /// Layout of C matrix (concept: MatrixLayout) + typename LayoutC, + /// Number of partitions along K dimension + int PartitionsK, + /// Store the accumulators in row major or column major. + bool AccumulatorsInRowMajor> +struct DefaultMmaTensorOp< + WarpShape_, + GemmShape<16, 16, 16>, + ElementA, + LayoutA, + ElementB, + LayoutB, + ElementC, + LayoutC, + arch::OpMultiplyAdd, + PartitionsK, + AccumulatorsInRowMajor> { + + /// Warp shape + using Shape = WarpShape_; + + using Policy = cutlass::gemm::warp::MmaTensorOpPolicy< + cutlass::arch::Mma, + 64, + ElementA, + LayoutA, + ElementB, + LayoutB, + ElementC, + LayoutC, + arch::OpMultiplyAdd>, + cutlass::MatrixShape<1, 1> >; + + // Define the warp-level tensor op + using Type = cutlass::gemm::warp::MmaTensorOp< + WarpShape_, + ElementA, + LayoutA, + ElementB, + LayoutB, + ElementC, + LayoutC, + Policy, + PartitionsK, + AccumulatorsInRowMajor>; +}; + +///////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace warp +} // namespace gemm +} // namespace cutlass + +///////////////////////////////////////////////////////////////////////////////////////////////// + diff --git a/cat_files/gemm_batched.h b/cat_files/gemm_batched.h new file mode 100644 index 00000000..c37210e8 --- /dev/null +++ b/cat_files/gemm_batched.h @@ -0,0 +1,726 @@ +/*************************************************************************************************** + * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ + +/*************************************************************************************************** +* Copyright (c) 2021 Iluvatar CoreX. All rights reserved. +* Copyright Declaration: This software, including all of its code and documentation, +* except for the third-party software it contains, is a copyrighted work of Shanghai Iluvatar CoreX +* Semiconductor Co., Ltd. and its affiliates ("Iluvatar CoreX") in accordance with the PRC Copyright +* Law and relevant international treaties, and all rights contained therein are enjoyed by Iluvatar +* CoreX. No user of this software shall have any right, ownership or interest in this software and +* any use of this software shall be in compliance with the terms and conditions of the End User +* License Agreement. + **************************************************************************************************/ + +/*! \file + \brief Template for a pipelined GEMM kernel. Does not compute batching or support split-K. +*/ + +#pragma once + +#include "cutlass/cutlass.h" +#include "cutlass/numeric_types.h" +#include "cutlass/arch/arch.h" +#include "cutlass/device_kernel.h" + +#include "cutlass/gemm/threadblock/threadblock_swizzle.h" +#include "cutlass/gemm/kernel/gemm_batched.h" + +#include "cutlass/gemm/kernel/default_gemm.h" +#include "cutlass/gemm/device/default_gemm_configuration.h" + +//////////////////////////////////////////////////////////////////////////////// + +namespace cutlass { +namespace gemm { +namespace device { + +//////////////////////////////////////////////////////////////////////////////// + +/*! Gemm device-level operator. This is an interface to efficient CUTLASS GEMM kernels that may + be invoked from host code. + + The contributions of this class are: + + 1. At compile time, it maps data types and high-level structural parameters onto + specific CUTLASS components. + + 2. At runtime, it maps logical arguments to GEMM problems to kernel parameters. + + 3. At runtime, it launches kernels on the device. + + The intent is to provide a convenient mechanism for interacting with most plausible GEMM + configurations for each supported architecture. Consequently, not all parameters are exposed + to the top-level interface. Rather, sensible defaults at each level of the CUTLASS hierarchy + are selected to tradeoff simplicity of the interface with flexibility. We expect + most configurations to be specified at this level. Applications with more exotic requirements + may construct their kernels of interest using CUTLASS components at the threadblock, warp, + and thread levels of abstraction. + + CUTLASS exposes computations using the functor design pattern in which objects compose some + internal state with an overloaded function call operator. This enables decoupling of + initialization from execution, possibly reducing overhead during steady state phases of + application execution. + + CUTLASS device-level operators expose an Arguments structure encompassing each logical + input to the computation. This is distinct from the kernel-level Params structure pattern + which contains application-specific precomputed state needed by the device code. + + Example of a CUTLASS GEMM operator implementing the functionality of cuBLAS's SGEMM NN + is as follows: + + // + // Instantiate the CUTLASS GEMM operator. + // + + cutlass::gemm::device::Gemm< + float, + cutlass::layout::ColumnMajor, + float, + cutlass::layout::ColumnMajor, + float, + cutlass::layout::ColumnMajor + > gemm_op; + + // + // Launch the GEMM operation on the device + // + + cutlass::Status status = gemm_op({ + {m, n, k}, // GemmCoord problem_size, + {A, lda}, // TensorRef ref_A, + {B, ldb}, // TensorRef ref_B, + {C, ldc}, // TensorRef ref_C, + {D, ldd}, // TensorRef ref_D, + {alpha, beta} // EpilogueOutputOp::Params epilogue_op_params + }); + + + A simplified view of the template is listed below. + + template < + /// Element type for A matrix operand + typename ElementA, + + /// Layout type for A matrix operand + typename LayoutA, + + /// Element type for B matrix operand + typename ElementB, + + /// Layout type for B matrix operand + typename LayoutB, + + /// Element type for C and D matrix operands + typename ElementC, + + /// Layout type for C and D matrix operands + typename LayoutC, + + /// Element type for internal accumulation + typename ElementAccumulator, + + /// Operator class tag + typename OperatorClass, + + /// Tag indicating architecture to tune for. This is the minimum SM that + /// supports the intended feature. The device kernel can be built + /// targeting any SM larger than this number. + typename ArchTag, + + /// Threadblock-level tile size (concept: GemmShape) + typename ThreadblockShape, + + /// Warp-level tile size (concept: GemmShape) + typename WarpShape, + + /// Warp-level tile size (concept: GemmShape) + typename InstructionShape, + + /// Epilogue output operator + typename EpilogueOutputOp, + + /// Threadblock-level swizzling operator + typename ThreadblockSwizzle, + + /// Number of stages used in the pipelined mainloop + int Stages + > + class Gemm; +*/ +template < + /// Element type for A matrix operand + typename ElementA_, + /// Layout type for A matrix operand + typename LayoutA_, + /// Element type for B matrix operand + typename ElementB_, + /// Layout type for B matrix operand + typename LayoutB_, + /// Element type for C and D matrix operands + typename ElementC_, + /// Layout type for C and D matrix operands + typename LayoutC_, + /// Element type for internal accumulation + typename ElementAccumulator_ = ElementC_, + /// Operator class tag + typename OperatorClass_ = arch::OpClassSimt, + /// Tag indicating architecture to tune for + typename ArchTag_ = arch::Sm61, + /// Threadblock-level tile size (concept: GemmShape) + typename ThreadblockShape_ = typename DefaultGemmConfiguration< + OperatorClass_, ArchTag_, ElementA_, ElementB_, ElementC_, + ElementAccumulator_>::ThreadblockShape, + /// Warp-level tile size (concept: GemmShape) + typename WarpShape_ = typename DefaultGemmConfiguration< + OperatorClass_, ArchTag_, ElementA_, ElementB_, ElementC_, + ElementAccumulator_>::WarpShape, + /// Instruction-level tile size (concept: GemmShape) + typename InstructionShape_ = typename DefaultGemmConfiguration< + OperatorClass_, ArchTag_, ElementA_, ElementB_, ElementC_, + ElementAccumulator_>::InstructionShape, + /// Epilogue output operator + typename EpilogueOutputOp_ = typename DefaultGemmConfiguration< + OperatorClass_, ArchTag_, ElementA_, ElementB_, ElementC_, + ElementAccumulator_>::EpilogueOutputOp, + /// Threadblock-level swizzling operator + typename ThreadblockSwizzle_ = threadblock::GemmBatchedIdentityThreadblockSwizzle, + /// Number of stages used in the pipelined mainloop + int Stages = + DefaultGemmConfiguration::kStages, + /// Access granularity of A matrix in units of elements + int AlignmentA = + DefaultGemmConfiguration::kAlignmentA, + /// Access granularity of B matrix in units of elements + int AlignmentB = + DefaultGemmConfiguration::kAlignmentB, + /// Operation performed by GEMM + typename Operator_ = typename DefaultGemmConfiguration< + OperatorClass_, ArchTag_, ElementA_, ElementB_, ElementC_, + ElementAccumulator_>::Operator +> +class GemmBatched { + public: + + using ElementA = ElementA_; + using LayoutA = LayoutA_; + using TensorRefA = TensorRef; + using ElementB = ElementB_; + using LayoutB = LayoutB_; + using TensorRefB = TensorRef; + using ElementC = ElementC_; + using LayoutC = LayoutC_; + using TensorRefC = TensorRef; + using TensorRefD = TensorRef; + using ElementAccumulator = ElementAccumulator_; + using OperatorClass = OperatorClass_; + using ArchTag = ArchTag_; + using ThreadblockShape = ThreadblockShape_; + using WarpShape = WarpShape_; + using InstructionShape = InstructionShape_; + using EpilogueOutputOp = EpilogueOutputOp_; + using ThreadblockSwizzle = ThreadblockSwizzle_; + static int const kStages = Stages; + static int const kAlignmentA = AlignmentA; + static int const kAlignmentB = AlignmentB; + static int const kAlignmentC = EpilogueOutputOp::kCount; + using Operator = Operator_; + + /// Define the kernel + using DefaultGemmKernel = typename kernel::DefaultGemm< + ElementA, + LayoutA, + kAlignmentA, + ElementB, + LayoutB, + kAlignmentB, + ElementC, + LayoutC, + ElementAccumulator, + OperatorClass, + ArchTag, + ThreadblockShape, + WarpShape, + InstructionShape, + EpilogueOutputOp, + ThreadblockSwizzle, + kStages, + false, + Operator + >::GemmKernel; + + using GemmKernel = kernel::GemmBatched; + + /// Argument structure + struct Arguments { + + // + // Data members + // + + GemmCoord problem_size; + TensorRef ref_A; + int64_t stride_A; + TensorRef ref_B; + int64_t stride_B; + TensorRef ref_C; + int64_t stride_C; + TensorRef ref_D; + int64_t stride_D; + typename EpilogueOutputOp::Params epilogue; + int batch_count; + + // + // Methods + // + + /// Default ctor + CUTLASS_HOST_DEVICE + Arguments() { } + + /// Constructs an Arguments structure + CUTLASS_HOST_DEVICE + Arguments( + GemmCoord problem_size_, + TensorRef ref_A_, + int64_t stride_A_, + TensorRef ref_B_, + int64_t stride_B_, + TensorRef ref_C_, + int64_t stride_C_, + TensorRef ref_D_, + int64_t stride_D_, + typename EpilogueOutputOp::Params epilogue_, + int batch_count_ + ): + problem_size(problem_size_), + ref_A(ref_A_), + stride_A(stride_A_), + ref_B(ref_B_), + stride_B(stride_B_), + ref_C(ref_C_), + stride_C(stride_C_), + ref_D(ref_D_), + stride_D(stride_D_), + epilogue(epilogue_), + batch_count(batch_count_) { } + }; + +private: + + /// Kernel parameters object + typename GemmKernel::Params params_; + +public: + + /// Constructs the GEMM. + GemmBatched() { } + + /// Determines whether the GEMM can execute the given problem. + static Status can_implement(Arguments const &args) { + + if (!TensorRef_aligned(args.ref_A, kAlignmentA) || (args.stride_A % kAlignmentA)) { + return Status::kErrorMisalignedOperand; + } + + if (!TensorRef_aligned(args.ref_B, kAlignmentB) || (args.stride_B % kAlignmentB)) { + return Status::kErrorMisalignedOperand; + } + + if (!TensorRef_aligned(args.ref_C, kAlignmentC) || (args.stride_C % kAlignmentC)) { + return Status::kErrorMisalignedOperand; + } + + if (!TensorRef_aligned(args.ref_D, kAlignmentC) || (args.stride_D % kAlignmentC)) { + return Status::kErrorMisalignedOperand; + } + + if ((args.problem_size.m() % kAlignmentA) || (args.problem_size.k() % kAlignmentA) || + (args.problem_size.n() % kAlignmentB) || (args.problem_size.k() % kAlignmentB) || + (args.problem_size.m() % kAlignmentC) || (args.problem_size.n() % kAlignmentC)) { + + return Status::kErrorMisalignedOperand; + } + + return Status::kSuccess; + } + + /// Gets the workspace size + static size_t get_workspace_size(Arguments const &args) { + return 0; + } + + /// Initializes GEMM state from arguments. + Status initialize(Arguments const &args, void *workspace = nullptr, cudaStream_t stream = nullptr) { + + // Determine grid shape + ThreadblockSwizzle threadblock_swizzle; + + cutlass::gemm::GemmCoord grid_shape = threadblock_swizzle.get_tiled_shape( + args.problem_size, + {ThreadblockShape::kM, ThreadblockShape::kN, ThreadblockShape::kK}, + args.batch_count); + + // Initialize the Params structure + params_ = typename GemmKernel::Params{ + args.problem_size, + grid_shape, + args.ref_A.non_const_ref(), + args.stride_A, + args.ref_B.non_const_ref(), + args.stride_B, + args.ref_C.non_const_ref(), + args.stride_C, + args.ref_D, + args.stride_D, + args.epilogue, + args.batch_count + }; + + return Status::kSuccess; + } + + /// Lightweight update given a subset of arguments + Status update(Arguments const &args, void *workspace = nullptr) { + + params_.ref_A.reset(args.ref_A.non_const_ref().data()); + params_.ref_B.reset(args.ref_B.non_const_ref().data()); + params_.ref_C.reset(args.ref_C.non_const_ref().data()); + params_.ref_D.reset(args.ref_D.data()); + + return Status::kSuccess; + } + + /// Runs the kernel using initialized state. + Status run(cudaStream_t stream = nullptr) { + + ThreadblockSwizzle threadblock_swizzle; + + dim3 grid = threadblock_swizzle.get_grid_shape(params_.grid_tiled_shape); + // XXX(Peter Han): prealod needs double warps in z direction + dim3 block(GemmKernel::kThreadCount, 1, kStages ? 1 : 2); + + cudaError_t result; + + int smem_size = int(sizeof(typename GemmKernel::SharedStorage)); + /// cudaFuncSetAttribute isn't supported under CUDA-8.0 + // if (smem_size >= (48 << 10)) { + // result = cudaFuncSetAttribute(Kernel, + // cudaFuncAttributeMaxDynamicSharedMemorySize, + // smem_size); + + // if (result != cudaSuccess) { + // return Status::kErrorInternal; + // } + + // result = cudaFuncSetAttribute( + // Kernel, + // cudaFuncAttributePreferredSharedMemoryCarveout, 100); + + // if (result != cudaSuccess) { + // return Status::kErrorInternal; + // } + // } + + cutlass::Kernel<<>>(params_); + + result = cudaGetLastError(); + + return result == cudaSuccess ? Status::kSuccess : Status::kErrorInternal; + } + + /// Runs the kernel using initialized state. + Status operator()(cudaStream_t stream = nullptr) { + return run(stream); + } + + /// Runs the kernel using initialized state. + Status operator()( + Arguments const &args, + void *workspace = nullptr, + cudaStream_t stream = nullptr) { + + Status status = initialize(args, workspace, stream); + + if (status == Status::kSuccess) { + status = run(stream); + } + + return status; + } +}; + +//////////////////////////////////////////////////////////////////////////////// + +/// Parital specialization for column-major output exchanges problem size and operand. +template < + /// Element type for A matrix operand + typename ElementA_, + /// Layout type for A matrix operand + typename LayoutA_, + /// Element type for B matrix operand + typename ElementB_, + /// Layout type for B matrix operand + typename LayoutB_, + /// Element type for C and D matrix operands + typename ElementC_, + /// Element type for internal accumulation + typename ElementAccumulator_, + /// Operator class tag + typename OperatorClass_, + /// Tag indicating architecture to tune for + typename ArchTag_, + /// Threadblock-level tile size (concept: GemmShape) + typename ThreadblockShape_, + /// Warp-level tile size (concept: GemmShape) + typename WarpShape_, + /// Warp-level tile size (concept: GemmShape) + typename InstructionShape_, + /// Epilogue output operator + typename EpilogueOutputOp_, + /// Threadblock-level swizzling operator + typename ThreadblockSwizzle_, + /// Number of stages used in the pipelined mainloop + int Stages, + /// Access granularity of A matrix in units of elements + int AlignmentA, + /// Access granularity of B matrix in units of elements + int AlignmentB, + typename Operator_ +> +class GemmBatched< + ElementA_, + LayoutA_, + ElementB_, + LayoutB_, + ElementC_, + layout::ColumnMajor, + ElementAccumulator_, + OperatorClass_, + ArchTag_, + ThreadblockShape_, + WarpShape_, + InstructionShape_, + EpilogueOutputOp_, + ThreadblockSwizzle_, + Stages, + AlignmentA, + AlignmentB, + Operator_ +> { +public: + + using ElementA = ElementA_; + using LayoutA = LayoutA_; + using TensorRefA = TensorRef; + using ElementB = ElementB_; + using LayoutB = LayoutB_; + using TensorRefB = TensorRef; + using ElementC = ElementC_; + using LayoutC = layout::ColumnMajor; + using TensorRefC = TensorRef; + using TensorRefD = TensorRef; + using ElementAccumulator = ElementAccumulator_; + using OperatorClass = OperatorClass_; + using ArchTag = ArchTag_; + using ThreadblockShape = ThreadblockShape_; + using WarpShape = WarpShape_; + using InstructionShape = InstructionShape_; + using EpilogueOutputOp = EpilogueOutputOp_; + using ThreadblockSwizzle = ThreadblockSwizzle_; + static int const kStages = Stages; + + static int const kAlignmentA = AlignmentA; + static int const kAlignmentB = AlignmentB; + static int const kAlignmentC = EpilogueOutputOp::kCount; + static bool const kSplitKSerial = false; + + // + using UnderlyingOperator = GemmBatched< + ElementB, + typename layout::LayoutTranspose::type, + ElementA, + typename layout::LayoutTranspose::type, + ElementC, + layout::RowMajor, + ElementAccumulator, + OperatorClass, + ArchTag, + ThreadblockShape, + WarpShape, + InstructionShape, + EpilogueOutputOp, + ThreadblockSwizzle, + Stages, + kAlignmentB, + kAlignmentA + >; + + using UnderlyingArguments = typename UnderlyingOperator::Arguments; + using GemmKernel = typename UnderlyingOperator::GemmKernel; + + /// Argument structure + struct Arguments { + + // + // Data members + // + + GemmCoord problem_size; + TensorRef ref_A; + int64_t stride_A; + TensorRef ref_B; + int64_t stride_B; + TensorRef ref_C; + int64_t stride_C; + TensorRef ref_D; + int64_t stride_D; + typename EpilogueOutputOp::Params epilogue; + int batch_count; + + // + // Methods + // + + /// Default ctor + CUTLASS_HOST_DEVICE + Arguments() { } + + /// Constructs an Arguments structure + CUTLASS_HOST_DEVICE + Arguments( + GemmCoord problem_size_, + TensorRef ref_A_, + int64_t stride_A_, + TensorRef ref_B_, + int64_t stride_B_, + TensorRef ref_C_, + int64_t stride_C_, + TensorRef ref_D_, + int64_t stride_D_, + typename EpilogueOutputOp::Params epilogue_, + int batch_count_ + ): + problem_size(problem_size_), + ref_A(ref_A_), + stride_A(stride_A_), + ref_B(ref_B_), + stride_B(stride_B_), + ref_C(ref_C_), + stride_C(stride_C_), + ref_D(ref_D_), + stride_D(stride_D_), + epilogue(epilogue_), + batch_count(batch_count_) { } + }; + +private: + + UnderlyingOperator underlying_operator_; + +public: + + /// Constructs the GEMM. + GemmBatched() { } + + /// Helper to construct a transposed equivalent for the underying GEMM operator + static UnderlyingArguments to_underlying_arguments(Arguments const &args) { + return UnderlyingArguments( + {args.problem_size.n(), args.problem_size.m(), args.problem_size.k()}, + {args.ref_B.data(), args.ref_B.stride(0)}, + args.stride_B, + {args.ref_A.data(), args.ref_A.stride(0)}, + args.stride_A, + {args.ref_C.data(), args.ref_C.stride(0)}, + args.stride_C, + {args.ref_D.data(), args.ref_D.stride(0)}, + args.stride_D, + args.epilogue, + args.batch_count + ); + } + + /// Determines whether the GEMM can execute the given problem. + static Status can_implement(Arguments const &args) { + + return UnderlyingOperator::can_implement(to_underlying_arguments(args)); + } + + /// Gets the workspace size + static size_t get_workspace_size(Arguments const &args) { + + return UnderlyingOperator::get_workspace_size(to_underlying_arguments(args)); + } + + /// Initializes GEMM state from arguments. + Status initialize(Arguments const &args, void *workspace = nullptr, cudaStream_t stream = nullptr) { + + return underlying_operator_.initialize(to_underlying_arguments(args), workspace); + } + + /// Lightweight update given a subset of arguments + Status update(Arguments const &args, void *workspace = nullptr) { + + return underlying_operator_.update(to_underlying_arguments(args), workspace); + } + + /// Runs the kernel using initialized state. + Status run(cudaStream_t stream = nullptr) { + + return underlying_operator_.run(stream); + } + + /// Runs the kernel using initialized state. + Status operator()(cudaStream_t stream = nullptr) { + return run(stream); + } + + /// Runs the kernel using initialized state. + Status operator()( + Arguments const &args, + void *workspace = nullptr, + cudaStream_t stream = nullptr) { + + Status status = initialize(args, workspace, stream); + + if (status == Status::kSuccess) { + status = run(stream); + } + + return status; + } + +}; + +//////////////////////////////////////////////////////////////////////////////// + +} // namespace device +} // namespace gemm +} // namespace cutlass + +//////////////////////////////////////////////////////////////////////////////// diff --git a/cat_files/gemm_universal.h b/cat_files/gemm_universal.h new file mode 100644 index 00000000..8ea1f47f --- /dev/null +++ b/cat_files/gemm_universal.h @@ -0,0 +1,376 @@ +/*************************************************************************************************** + * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ +/*! \file + \brief +*/ + +#pragma once + +#include "cutlass/cutlass.h" +#include "cutlass/numeric_types.h" +#include "cutlass/arch/arch.h" +#include "cutlass/device_kernel.h" + +#include "cutlass/gemm/gemm.h" +#include "cutlass/gemm/threadblock/threadblock_swizzle.h" +#include "cutlass/gemm/kernel/gemm_universal.h" + +#include "cutlass/gemm/kernel/default_gemm_universal.h" +#include "cutlass/gemm/device/default_gemm_configuration.h" +#include "cutlass/gemm/device/gemm_universal_base.h" + +//////////////////////////////////////////////////////////////////////////////// + +namespace cutlass { +namespace gemm { +namespace device { + +///////////////////////////////////////////////////////////////////////////////////////////////// + +/*! + The universal GEMM accommodates serial reductions, parallel reductions, batched strided, and + batched array variants. +*/ +template < + /// Element type for A matrix operand + typename ElementA_, + /// Layout type for A matrix operand + typename LayoutA_, + /// Element type for B matrix operand + typename ElementB_, + /// Layout type for B matrix operand + typename LayoutB_, + /// Element type for C and D matrix operands + typename ElementC_, + /// Layout type for C and D matrix operands + typename LayoutC_, + /// Element type for internal accumulation + typename ElementAccumulator_ = ElementC_, + /// Operator class tag + typename OperatorClass_ = arch::OpClassSimt, + /// Tag indicating architecture to tune for. This is the minimum SM that + /// supports the intended feature. The device kernel can be built + /// targeting any SM larger than this number. + typename ArchTag_ = arch::Sm61, + /// Threadblock-level tile size (concept: GemmShape) + typename ThreadblockShape_ = typename DefaultGemmConfiguration< + OperatorClass_, ArchTag_, ElementA_, ElementB_, ElementC_, + ElementAccumulator_>::ThreadblockShape, + /// Warp-level tile size (concept: GemmShape) + typename WarpShape_ = typename DefaultGemmConfiguration< + OperatorClass_, ArchTag_, ElementA_, ElementB_, ElementC_, + ElementAccumulator_>::WarpShape, + /// Instruction-level tile size (concept: GemmShape) + typename InstructionShape_ = typename DefaultGemmConfiguration< + OperatorClass_, ArchTag_, ElementA_, ElementB_, ElementC_, + ElementAccumulator_>::InstructionShape, + /// Epilogue output operator + typename EpilogueOutputOp_ = typename DefaultGemmConfiguration< + OperatorClass_, ArchTag_, ElementA_, ElementB_, ElementC_, + ElementAccumulator_>::EpilogueOutputOp, + /// Threadblock-level swizzling operator + typename ThreadblockSwizzle_ = threadblock::GemmIdentityThreadblockSwizzle<>, + /// Number of stages used in the pipelined mainloop + int Stages = + DefaultGemmConfiguration::kStages, + /// Access granularity of A matrix in units of elements + int AlignmentA = + DefaultGemmConfiguration::kAlignmentA, + /// Access granularity of B matrix in units of elements + int AlignmentB = + DefaultGemmConfiguration::kAlignmentB, + /// Operation performed by GEMM + typename Operator_ = typename DefaultGemmConfiguration< + OperatorClass_, ArchTag_, ElementA_, ElementB_, ElementC_, + ElementAccumulator_>::Operator, + /// Complex elementwise transformation on A operand + ComplexTransform TransformA = ComplexTransform::kNone, + /// Complex elementwise transformation on B operand + ComplexTransform TransformB = ComplexTransform::kNone +> +class GemmUniversal : + GemmUniversalBase< + typename kernel::DefaultGemmUniversal< + ElementA_, + LayoutA_, + TransformA, + AlignmentA, + ElementB_, + LayoutB_, + TransformB, + AlignmentB, + ElementC_, + LayoutC_, + ElementAccumulator_, + OperatorClass_, + ArchTag_, + ThreadblockShape_, + WarpShape_, + InstructionShape_, + EpilogueOutputOp_, + ThreadblockSwizzle_, + Stages, + Operator_ + >::GemmKernel + > { + + public: + + using ElementAccumulator = ElementAccumulator_; + using OperatorClass = OperatorClass_; + using ArchTag = ArchTag_; + using ThreadblockShape = ThreadblockShape_; + using WarpShape = WarpShape_; + using InstructionShape = InstructionShape_; + using EpilogueOutputOp = EpilogueOutputOp_; + using ThreadblockSwizzle = ThreadblockSwizzle_; + using Operator = Operator_; + static int const kStages = Stages; + static int const kAlignmentA = AlignmentA; + static int const kAlignmentB = AlignmentB; + static int const kAlignmentC = EpilogueOutputOp::kCount; + static ComplexTransform const kTransformA = TransformA; + static ComplexTransform const kTransformB = TransformB; + + using Base = GemmUniversalBase< + typename kernel::DefaultGemmUniversal< + ElementA_, + LayoutA_, + TransformA, + AlignmentA, + ElementB_, + LayoutB_, + TransformB, + AlignmentB, + ElementC_, + LayoutC_, + ElementAccumulator_, + OperatorClass_, + ArchTag_, + ThreadblockShape_, + WarpShape_, + InstructionShape_, + EpilogueOutputOp_, + ThreadblockSwizzle_, + Stages, + Operator_ + >::GemmKernel + >; + + using Arguments = typename Base::Arguments; + using GemmKernel = typename Base::GemmKernel; +}; + +//////////////////////////////////////////////////////////////////////////////// + +/// Parital specialization for column-major output exchanges problem size and operand. +template < + /// Element type for A matrix operand + typename ElementA_, + /// Layout type for A matrix operand + typename LayoutA_, + /// Element type for B matrix operand + typename ElementB_, + /// Layout type for B matrix operand + typename LayoutB_, + /// Element type for C and D matrix operands + typename ElementC_, + /// Element type for internal accumulation + typename ElementAccumulator_, + /// Operator class tag + typename OperatorClass_, + /// Tag indicating architecture to tune for. This is the minimum SM that + /// supports the intended feature. The device kernel can be built + /// targeting any SM larger than this number. + typename ArchTag_, + /// Threadblock-level tile size (concept: GemmShape) + typename ThreadblockShape_, + /// Warp-level tile size (concept: GemmShape) + typename WarpShape_, + /// Instruction-level tile size (concept: GemmShape) + typename InstructionShape_, + /// Epilogue output operator + typename EpilogueOutputOp_, + /// Threadblock-level swizzling operator + typename ThreadblockSwizzle_, + /// Number of stages used in the pipelined mainloop + int Stages, + /// Access granularity of A matrix in units of elements + int AlignmentA, + /// Access granularity of B matrix in units of elements + int AlignmentB, + /// Operation performed by GEMM + typename Operator_, + /// Complex elementwise transformation on A operand + ComplexTransform TransformA, + /// Complex elementwise transformation on B operand + ComplexTransform TransformB> +class GemmUniversal { + public: + + using ElementA = ElementA_; + using LayoutA = LayoutA_; + using TensorRefA = TensorRef; + using ElementB = ElementB_; + using LayoutB = LayoutB_; + using TensorRefB = TensorRef; + using ElementC = ElementC_; + using LayoutC = layout::ColumnMajor; + using TensorRefC = TensorRef; + using TensorRefD = TensorRef; + using ElementAccumulator = ElementAccumulator_; + using OperatorClass = OperatorClass_; + using ArchTag = ArchTag_; + using ThreadblockShape = ThreadblockShape_; + using WarpShape = WarpShape_; + using InstructionShape = InstructionShape_; + using EpilogueOutputOp = EpilogueOutputOp_; + using ThreadblockSwizzle = ThreadblockSwizzle_; + using Operator = Operator_; + static int const kStages = Stages; + static int const kAlignmentA = AlignmentA; + static int const kAlignmentB = AlignmentB; + static ComplexTransform const kTransformA = TransformA; + static ComplexTransform const kTransformB = TransformB; + + using UnderlyingOperator = typename GemmUniversal< + ElementB, + typename layout::LayoutTranspose::type, + ElementA, + typename layout::LayoutTranspose::type, + ElementC, + layout::RowMajor, + ElementAccumulator, + OperatorClass, + ArchTag, + ThreadblockShape, + WarpShape, + InstructionShape, + EpilogueOutputOp, + ThreadblockSwizzle, + Stages, + kAlignmentB, + kAlignmentA, + Operator, + kTransformB, + kTransformA + >::Base; + + using GemmKernel = typename UnderlyingOperator::GemmKernel; + static int const kAlignmentC = EpilogueOutputOp::kCount; + + /// Argument structure + using Arguments = typename UnderlyingOperator::Arguments; + +private: + + UnderlyingOperator underlying_operator_; + +public: + + /// Constructs the GEMM. + GemmUniversal() { } + + /// Helper to construct a transposed equivalent for the underying GEMM operator + static Arguments to_underlying_arguments(Arguments const &args) { + return args.transposed_problem(); + } + + /// Determines whether the GEMM can execute the given problem. + static Status can_implement(Arguments const &args) { + + return UnderlyingOperator::can_implement(to_underlying_arguments(args)); + } + + /// Gets the workspace size + static size_t get_workspace_size(Arguments const &args) { + + return UnderlyingOperator::get_workspace_size(to_underlying_arguments(args)); + } + + /// Computes the grid shape + static dim3 get_grid_shape(Arguments const &args) { + return UnderlyingOperator::get_grid_shape(to_underlying_arguments(args)); + } + + /// Computes the maximum number of active blocks per multiprocessor + static int maximum_active_blocks(int smem_capacity = -1) { + return UnderlyingOperator::maximum_active_blocks(smem_capacity); + } + + /// Initializes GEMM state from arguments. + Status initialize(Arguments const &args, void *workspace = nullptr, cudaStream_t stream = nullptr) { + + return underlying_operator_.initialize(to_underlying_arguments(args), workspace, stream); + } + + /// Lightweight update given a subset of arguments + Status update(Arguments const &args, void *workspace = nullptr) { + + return underlying_operator_.update(to_underlying_arguments(args), workspace); + } + + /// Runs the kernel using initialized state. + Status run(cudaStream_t stream = nullptr) { + + return underlying_operator_.run(stream); + } + + /// Runs the kernel using initialized state. + Status operator()(cudaStream_t stream = nullptr) { + return run(stream); + } + + /// Runs the kernel using initialized state. + Status operator()( + Arguments const &args, + void *workspace = nullptr, + cudaStream_t stream = nullptr) { + + Status status = initialize(args, workspace, stream); + + if (status == Status::kSuccess) { + status = run(stream); + } + + return status; + } +}; + +//////////////////////////////////////////////////////////////////////////////// + +} // namespace device +} // namespace gemm +} // namespace cutlass + +//////////////////////////////////////////////////////////////////////////////// diff --git a/cat_files/iluvatar_mma.hpp b/cat_files/iluvatar_mma.hpp new file mode 100644 index 00000000..cda0ebb6 --- /dev/null +++ b/cat_files/iluvatar_mma.hpp @@ -0,0 +1,1238 @@ +/* Copyright 2019 Iluvatar-CoreX - All Rights Reserved + * Unauthorized copying of this file, via any medium is strictly prohibited + * Proprietary and confidential + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE + * DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if !defined(__CUDA_INCLUDE_COMPILER_INTERNAL_HEADERS__) +#if defined(_MSC_VER) +#pragma message("crt/iluvatar_mma.h is an internal header file and must not be used directly. Please use mma.h instead.") +#else +#warning "crt/iluvatar_mma.h is an internal header file and must not be used directly. Please use mma.h instead." +#endif +#define __CUDA_INCLUDE_COMPILER_INTERNAL_HEADERS__ +#define __UNDEF_CUDA_INCLUDE_COMPILER_INTERNAL_HEADERS_CUDA_MMA_H__ +#endif + +#if !defined(__ILUVATAR_MMA_HPP__) +#define __ILUVATAR_MMA_HPP__ + +#include + +#define __CUDA_MMA_DEVICE_DECL__ static __device__ __inline__ + +#if defined(__cplusplus) && defined(__CUDACC__) + +#if !defined(__CUDA_ARCH__) || defined(__ILUVATAR__) + +#if !defined(__CUDA_ARCH__) || defined(__ivcore10__) +#define __BI__ 1 +#endif +#if !defined(__CUDA_ARCH__) || defined(__ivcore11__) +#define __MR__ 1 +#endif + +namespace nvcuda { +namespace wmma { + + /// Convert tile internal coordinate to offset relative to origin of current tile + template + __device__ __inline__ + int64_t CoordToOffset(int row, int column); + + template <> + __device__ __inline__ + int64_t CoordToOffset<32, layout_t::mem_row_major>(int row, int column) { + return row * 16 + column; + } + + template <> + __device__ __inline__ + int64_t CoordToOffset<16, layout_t::mem_row_major>(int row, int column) { + int const i = column / 16; + int const c = column % 16; + int const r = row / 2; + + return (i * 256 + r / 4 * 128) + ((r * 32 + c * 2 + (row & 1) + i * 64) & 127); + } + + template <> + __device__ __inline__ + int64_t CoordToOffset<8, layout_t::mem_row_major>(int row, int column) { + int const i = column / 16; + int const c = column % 16; + int const r = row / 4; + return i * 256 + ((r * 64 + c * 4 + (row & 3) + 64 * i) & 255); + } + + template <> + __device__ __inline__ + int64_t CoordToOffset<32, layout_t::mem_col_major>(int row, int column) { + return ((column >> 2) & 3) * 64 + (row & 3) * 16 + (((row >> 2) & 3) ^ ((column >> 2) & 3)) * 4 + (column & 3); + } + + template <> + __device__ __inline__ + int64_t CoordToOffset<16, layout_t::mem_col_major>(int row, int column) { + int const r = row >> 1; + return (column >> 2) * 128 + (r & 3) * 32 + ((r >> 3) ^ (column >> 3)) * 16 + + ((r >> 2 & 1) ^ (column >> 2 & 1)) * 8 + (column & 3) * 2 + (row & 1); + } + + template <> + __device__ __inline__ + int64_t CoordToOffset<8, layout_t::mem_col_major>(int row, int column) { + int const r = row >> 2; + return (column >> 2) * 256 + (r & 3) * 64 + ((r >> 2) ^ (column / 4)) * 16 + + (column & 3) * 4 + (row & 3); + } + + template + __CUDA_MMA_DEVICE_DECL__ void __imma_ld_col_b8(MatrixType* a, const PtrType* p) { + int laneId = __ivcorex_lane_id(); + + for (int quarter_tile = 0; quarter_tile < 4; quarter_tile++) { + int row = (laneId / 16) * 4 + 16 * quarter_tile; + int column = laneId % 16; + int offset = CoordToOffset<8, layout_t::mem_col_major>(row, column); + a[quarter_tile] = *((int*)(p + offset)); + } + } + + template + __CUDA_MMA_DEVICE_DECL__ void __imma_ld_row_b8(MatrixType* a, const PtrType* p) { + int laneId = __ivcorex_lane_id(); + + for (int quarter_tile = 0; quarter_tile < 4; quarter_tile++) { + int row = (laneId / 16) * 4; + int column = laneId % 16 + 16 * quarter_tile; + int offset = CoordToOffset<8, layout_t::mem_row_major>(row, column); + a[quarter_tile] = *((int*)(p + offset)); + } + } + + template + __CUDA_MMA_DEVICE_DECL__ void __imma_ld_row_b32(MatrixType* a, const PtrType* p) { + int laneId = __ivcorex_lane_id(); + + for(int quarter_tile = 0; quarter_tile < 4; quarter_tile++) { + int row = laneId / 16 + 4 * quarter_tile; + int column = laneId % 16; + int offset = CoordToOffset<32, layout_t::mem_row_major>(row, column); + a[quarter_tile] = *(p + offset); + } + } + + // + // Load functions for frags of A, B, C, D: I8, I8, I32, I32 + // + /*************************************************  + Function:       load_matrix_sync_tcu + Description:    load data from slb to matrix a and b with row and col major + Input:          a destionation fragment + p source address in slb + WarpMIndex M direction's tcu position in a block area + WarpNIndex N direction's tcu position in a block area + WarpKIndex K direction's tcu position in a block area + *************************************************/ + template + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync_tcu(FragmentARowB8& a, const void* p, unsigned WarpMIndex, unsigned WarpKIndex) { + unsigned SLBaTCUIndex = WarpMIndex * a.getBlockKloopCnt() * 2 + WarpKIndex * 2; + const unsigned TCUEmStride = 64; + unsigned SLBaTCUOffset = SLBaTCUIndex * TCUEmStride; + a[0] = *((unsigned int*)p + SLBaTCUOffset + a.getRowEMOffset(SLBaTCUIndex % 4)); + a[1] = *((unsigned int*)p + SLBaTCUOffset + a.getRowEMOffset((SLBaTCUIndex + 1) % 4) + TCUEmStride); + } + +template + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync_tcu(FragmentAColB8& a, const void* p, unsigned WarpMIndex, unsigned WarpKIndex) { + const unsigned TCUEmStrideX4 = 256; + const unsigned WarpEmStride = TCUEmStrideX4 * 4; + unsigned SLBaWarpMIndex = (WarpMIndex / 4) * WarpEmStride; + unsigned SLBaTCUOffset = SLBaWarpMIndex + ((2 * WarpKIndex) % (a.getBlockKloopCnt() * 2) * TCUEmStrideX4); + a[0] = *((unsigned int*)p + SLBaTCUOffset + a.getColEMOffset(WarpMIndex % 4)); + a[1] = *((unsigned int*)p + SLBaTCUOffset + a.getColEMOffset(WarpMIndex % 4) + TCUEmStrideX4); + } + +template + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync_tcu(FragmentBRowB8& a, const void* p, unsigned WarpNIndex, unsigned WarpKIndex) { + unsigned SLBbTCUIndex = WarpKIndex * 2 * a.getBlockNloopCnt() + WarpNIndex; + const unsigned TCUEmStride = 64; + int SLBbTCUOffset = SLBbTCUIndex * TCUEmStride; + a[0] = *((unsigned int*)p + SLBbTCUOffset + a.getRowEMOffset(SLBbTCUIndex % 4)); + a[1] = *((unsigned int*)p + SLBbTCUOffset + TCUEmStride * a.getBlockNloopCnt() + a.getRowEMOffset((SLBbTCUIndex + a.getBlockNloopCnt()) % 4)); + } + +template + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync_tcu(FragmentBColB8& a, const void* p, unsigned WarpNIndex, unsigned WarpKIndex) { + unsigned SLBbTCUIndex = WarpNIndex * a.getBlockKloopCnt() * 2 + WarpKIndex * 2; + const unsigned TCUEmStrideX4 = 256; + unsigned SLBbTCUOffset = SLBbTCUIndex / 4 * TCUEmStrideX4; + a[0] = *((unsigned int*)p + SLBbTCUOffset + a.getColEMOffset(SLBbTCUIndex % 4)); + a[1] = *((unsigned int*)p + SLBbTCUOffset + a.getColEMOffset((SLBbTCUIndex + 1) % 4)); + } + +/*****************************************************/ + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed char* p, unsigned ldm) { + __imma_ld_row_b8(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed char* p, unsigned ldm) { + __imma_ld_col_b8(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed int* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + __imma_ld_row_b32(&(a.x[0]), p); + } + +#ifdef __BI__ + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed char* p, unsigned ldm) { + __imma_ld_col_b8(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed char* p, unsigned ldm) { + __imma_ld_row_b8(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed int* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + + for (int tile_row = 0; tile_row < 4; tile_row++) { + for (int tile_column = 0; tile_column < 4; tile_column++) { + int tile_num = 4 * tile_row + tile_column; + const signed int* ptr = p + 16 * 16 * tile_num; + __imma_ld_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + } +#endif /* __BI__ */ + +#ifdef __MR__ + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed char* p, unsigned ldm) { + for(int tile_num = 0; tile_num < 2; tile_num++) { + const signed char* ptr = p + 16 * 64 * tile_num; + __imma_ld_col_b8(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed char* p, unsigned ldm) { + for(int tile_num = 0; tile_num < 2; tile_num++) { + const signed char* ptr = p + 16 * 64 * tile_num; + __imma_ld_row_b8(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed int* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + + for (int tile_row = 0; tile_row < 4; tile_row++) { + for (int tile_column = 0; tile_column < 4; tile_column++) { + int tile_num = 4 * tile_row + tile_column; + const signed int* ptr = p + 16 * 16 * tile_num; + __imma_ld_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + } +#endif /* __MR__ */ + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed char* p, unsigned ldm) { + __imma_ld_row_b8(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed char* p, unsigned ldm) { + for (int tile_num = 0; tile_num < 4; tile_num++) { + const signed char* ptr = p + 16 * 64 * tile_num; + __imma_ld_row_b8(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed int* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_num = 0; tile_num < 4; tile_num++) { + const signed int* ptr = p + 16 * 16 * tile_num; + __imma_ld_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed char* p, unsigned ldm) { + for (int tile_num = 0; tile_num < 4; tile_num++) { + const signed char* ptr = p + 16 * 64 * tile_num; + __imma_ld_col_b8(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed char* p, unsigned ldm) { + __imma_ld_col_b8(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const signed int* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + + for (int tile_num = 0; tile_num < 4; tile_num++) { + const signed int* ptr = p + 16 * 16 * tile_num; + __imma_ld_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + + // + // Load functions for frags of A, B, C, D: U8, U8, U32, U32 + // + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned char* p, unsigned ldm) { + __imma_ld_row_b8(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned char* p, unsigned ldm) { + __imma_ld_col_b8(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned int* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + __imma_ld_row_b32(&(a.x[0]), p); + } + +#ifdef __BI__ + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned char* p, unsigned ldm) { + __imma_ld_col_b8(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned char* p, unsigned ldm) { + __imma_ld_row_b8(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned int* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + + for (int tile_row = 0; tile_row < 4; tile_row++) { + for (int tile_column = 0; tile_column < 4; tile_column++) { + int tile_num = 4 * tile_row + tile_column; + const unsigned int* ptr = p + 16 * 16 * tile_num; + __imma_ld_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + } +#endif /* __BI__ */ + +#ifdef __MR__ + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned char* p, unsigned ldm) { + for(int tile_num = 0; tile_num < 2; tile_num++) { + const unsigned char* ptr = p + 16 * 64 * tile_num; + __imma_ld_col_b8(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned char* p, unsigned ldm) { + for(int tile_num = 0; tile_num < 2; tile_num++) { + const unsigned char* ptr = p + 16 * 64 * tile_num; + __imma_ld_row_b8(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned int* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + + for (int tile_row = 0; tile_row < 4; tile_row++) { + for (int tile_column = 0; tile_column < 4; tile_column++) { + int tile_num = 4 * tile_row + tile_column; + const unsigned int* ptr = p + 16 * 16 * tile_num; + __imma_ld_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + } +#endif /* __MR__ */ + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned char* p, unsigned ldm) { + __imma_ld_row_b8(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned char* p, unsigned ldm) { + for (int tile_num = 0; tile_num < 4; tile_num++) { + const unsigned char* ptr = p + 16 * 64 * tile_num; + __imma_ld_row_b8(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned int* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_num = 0; tile_num < 4; tile_num++) { + const unsigned int* ptr = p + 16 * 16 * tile_num; + __imma_ld_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned char* p, unsigned ldm) { + for (int tile_num = 0; tile_num < 4; tile_num++) { + const unsigned char* ptr = p + 16 * 64 * tile_num; + __imma_ld_col_b8(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned char* p, unsigned ldm) { + __imma_ld_col_b8(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const unsigned int* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_num = 0; tile_num < 4; tile_num++) { + const unsigned int* ptr = p + 16 * 16 * tile_num; + __imma_ld_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + + template + __CUDA_MMA_DEVICE_DECL__ void __hmma_ld_row_b16(MatrixType* a, const PtrType* p) { + int laneId = __ivcorex_lane_id(); + + for (int quarter_tile = 0; quarter_tile < 4; quarter_tile++) { + int row = (laneId / 16) * 2 + 8 * (quarter_tile % 2); + int column = laneId % 16 + 16 * (quarter_tile / 2); + int offset = CoordToOffset<16, layout_t::mem_row_major>(row, column); + a[quarter_tile] = *((unsigned int*)(p + offset)); + } + } + + template + __CUDA_MMA_DEVICE_DECL__ void __hmma_ld_col_b16(MatrixType* a, const PtrType* p) { + int laneId = __ivcorex_lane_id(); + + for (int quarter_tile = 0; quarter_tile < 4; quarter_tile++) { + int row = (laneId / 16) * 2 + 8 * quarter_tile; + int column = laneId % 16; + int offset = CoordToOffset<16, layout_t::mem_col_major>(row, column); + a[quarter_tile] = *((unsigned int*)(p + offset)); + } + } + + // + // Load functions for frags of A, B, C, D: F16, F16, F32, F32 + // + + /*************************************************  + Function:       load_matrix_sync_tcu + Description:    load data from slb to matrix a and b with row and col major + Input:          a destionation fragment + p source address in slb + WarpMIndex M direction's tcu position in a block area + WarpNIndex N direction's tcu position in a block area + WarpKIndex K direction's tcu position in a block area + *************************************************/ + template + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync_tcu(FragmentARowB16& a, const void* p, unsigned WarpMIndex, unsigned WarpKIndex) { + int laneId = __ivcorex_lane_id(); + unsigned SLBaTCUIndex = WarpMIndex * a.getBlockKloopCnt() + WarpKIndex; + unsigned RowEmOffset = (SLBaTCUIndex & 1) ? (laneId ^ 0x20) : laneId; + const unsigned TCUEmStride = 128; + int SLBbTCUOffset = SLBaTCUIndex * TCUEmStride; + a[0] = *((unsigned int*)p + SLBbTCUOffset + RowEmOffset); + a[1] = *((unsigned int*)p + SLBbTCUOffset + RowEmOffset + 64); + } + +template + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync_tcu(FragmentAColB16& a, const void* p, unsigned WarpMIndex, unsigned WarpKIndex) { + unsigned SLBaTCUIndex = WarpMIndex / 2 * a.getBlockKloopCnt() + WarpKIndex; + const unsigned TCUEmStrideX2 = 256; + unsigned SLBbTCUOffset = SLBaTCUIndex * TCUEmStrideX2; + unsigned EmIdx = (WarpMIndex & 1) * 2; + a[0] = *((unsigned int*)p + SLBbTCUOffset + a.getColEMOffset(EmIdx % 4)); + a[1] = *((unsigned int*)p + SLBbTCUOffset + a.getColEMOffset((EmIdx + 1) % 4)); + } +template + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync_tcu(FragmentBRowB16& a, const void* p, unsigned WarpNIndex, unsigned WarpKIndex) { + int laneId = __ivcorex_lane_id(); + unsigned SLBbTCUIndex = WarpKIndex * a.getBlockNloopCnt() + WarpNIndex; + unsigned RowEmOffset = (SLBbTCUIndex & 1) ? (laneId ^ 0x20) : laneId; + const unsigned TCUEmStride = 128; + int SLBbTCUOffset = SLBbTCUIndex * TCUEmStride; + a[0] = *((unsigned int*)p + SLBbTCUOffset + RowEmOffset); + a[1] = *((unsigned int*)p + SLBbTCUOffset + RowEmOffset + 64); + } + +template + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync_tcu(FragmentBColB16& a, const void* p, unsigned WarpNIndex, unsigned WarpKIndex) { + unsigned SLBbTCUIndex = WarpKIndex / 2 * a.getBlockNloopCnt() + WarpNIndex; + const unsigned TCUEmStrideX2 = 256; + unsigned SLBbTCUOffset = SLBbTCUIndex * TCUEmStrideX2; + unsigned EmIdx = (WarpKIndex & 1) * 2; + a[0] = *((unsigned int*)p + SLBbTCUOffset + a.getColEMOffset(EmIdx % 4)); + a[1] = *((unsigned int*)p + SLBbTCUOffset + a.getColEMOffset((EmIdx + 1) % 4)); + } + +/*****************************************************/ + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const __half* p, unsigned ldm) { + __hmma_ld_row_b16(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const __half* p, unsigned ldm) { + __hmma_ld_col_b16(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const float* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + __imma_ld_row_b32(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const __half* p, unsigned ldm) { + __hmma_ld_col_b16(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const __half* p, unsigned ldm) { + __hmma_ld_row_b16(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const float* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_row = 0; tile_row < 2; tile_row++) { + for (int tile_column = 0; tile_column < 2; tile_column++) { + int tile_num = 2 * tile_row + tile_column; + const float* ptr = p + 16 * 16 * tile_num; + __imma_ld_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const __half* p, unsigned ldm) { + __hmma_ld_row_b16(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const __half* p, unsigned ldm) { + for (int tile_num = 0; tile_num < 2; tile_num++) { + const __half* ptr = p + 16 * 32 * tile_num; + __hmma_ld_row_b16(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const float* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_num = 0; tile_num < 2; tile_num++) { + const float* ptr = p + 16 * 16 * tile_num; + __imma_ld_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const __half* p, unsigned ldm) { + for (int tile_num = 0; tile_num < 2; tile_num++) { + const __half* ptr = p + 16 * 32 * tile_num; + __hmma_ld_col_b16(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const __half* p, unsigned ldm) { + __hmma_ld_col_b16(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const float* p, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_num = 0; tile_num < 2; tile_num++) { + const float* ptr = p + 16 * 16 * tile_num; + __imma_ld_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + + // + // Load functions for frags of A, B, C, D: F32, F32, F32, F32 + // + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const float* p, unsigned ldm) { + __imma_ld_row_b32(&(a.x[0]), p); + } + + template + __CUDA_MMA_DEVICE_DECL__ void __imma_ld_col_b32(MatrixType* a, const PtrType* p) { + int laneId = __ivcorex_lane_id(); + + for(int quarter_tile = 0; quarter_tile < 4; quarter_tile++) { + int row = laneId / 16 + 4 * quarter_tile; + int column = laneId % 16; + int offset = CoordToOffset<32, layout_t::mem_col_major>(row, column); + a[quarter_tile] = *(p + offset); + } + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const float* p, unsigned ldm) { + __imma_ld_col_b32(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const float* p, unsigned ldm) { + __imma_ld_row_b32(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const float* p, unsigned ldm) { + __imma_ld_col_b32(&(a.x[0]), p); + } + + __CUDA_MMA_DEVICE_DECL__ void load_matrix_sync(fragment& a, const float* p, unsigned ldm, layout_t layout) { + if (layout == mem_row_major) + __imma_ld_row_b32(&(a.x[0]), p); + } + + template + __CUDA_MMA_DEVICE_DECL__ void __imma_st_row_b32(const MatrixType* a, PtrType* p) { + int laneId = __ivcorex_lane_id(); + + for(int quarter_tile = 0; quarter_tile < 4; quarter_tile++) { + int row = laneId / 16 + 4 * quarter_tile; + int column = laneId % 16; + int offset = CoordToOffset<32, layout_t::mem_row_major>(row, column); + *(p + offset) = a[quarter_tile]; + } + } + + // + // Store functions for frags of A, B, C, D: I8, I8, I32, I32 + // + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(signed int* p, const fragment& a, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + __imma_st_row_b32(&(a.x[0]), p); + } + +#ifdef __BI__ + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(signed int* p, const fragment& a, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_row = 0; tile_row < 4; tile_row++) { + for (int tile_column = 0; tile_column < 4; tile_column++) { + int tile_num = 4 * tile_row + tile_column; + signed int* ptr = p + 16 * 16 * tile_num; + __imma_st_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + } +#endif /* __BI__ */ + +#ifdef __MR__ + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(signed int* p, const fragment& a, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_row = 0; tile_row < 4; tile_row++) { + for (int tile_column = 0; tile_column < 4; tile_column++) { + int tile_num = 4 * tile_row + tile_column; + signed int* ptr = p + 16 * 16 * tile_num; + __imma_st_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + } +#endif /* __MR__ */ + + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(signed int* p, const fragment& a, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_num = 0; tile_num < 4; tile_num++) { + signed int* ptr = p + 16 * 16 * tile_num; + __imma_st_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(signed int* p, const fragment& a, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_num = 0; tile_num < 4; tile_num++) { + signed int* ptr = p + 16 * 16 * tile_num; + __imma_st_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + + // + // Store functions for frags of A, B, C, D: U8, U8, U32, U32 + // + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(unsigned int* p, const fragment& a, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + __imma_st_row_b32(&(a.x[0]), p); + } + +#ifdef __BI__ + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(unsigned int* p, const fragment& a, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_row = 0; tile_row < 4; tile_row++) { + for (int tile_column = 0; tile_column < 4; tile_column++) { + int tile_num = 4 * tile_row + tile_column; + unsigned int* ptr = p + 16 * 16 * tile_num; + __imma_st_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + } +#endif /* __BI__ */ + +#ifdef __MR__ + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(unsigned int* p, const fragment& a, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_row = 0; tile_row < 4; tile_row++) { + for (int tile_column = 0; tile_column < 4; tile_column++) { + int tile_num = 4 * tile_row + tile_column; + unsigned int* ptr = p + 16 * 16 * tile_num; + __imma_st_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + } +#endif /* __MR__ */ + + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(unsigned int* p, const fragment& a, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_num = 0; tile_num < 4; tile_num++) { + unsigned int* ptr = p + 16 * 16 * tile_num; + __imma_st_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(unsigned int* p, const fragment& a, unsigned ldm, layout_t layout) { + assert(layout == mem_row_major && "mem_col_major not supported for accumulator!"); + for (int tile_num = 0; tile_num < 4; tile_num++) { + unsigned int* ptr = p + 16 * 16 * tile_num; + __imma_st_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + + // + // Store functions for frags of A, B, C, D: F16, F16, F32, F32 + // + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(float *p, const fragment& a, unsigned ldm, layout_t layout) { + if (layout == mem_row_major) { + __imma_st_row_b32(&(a.x[0]), p); + } + } + + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(float *p, const fragment& a, unsigned ldm, layout_t layout) { + if (layout == mem_row_major) { + for (int tile_row = 0; tile_row < 2; tile_row++) { + for (int tile_column = 0; tile_column < 2; tile_column++) { + int tile_num = 2 * tile_row + tile_column; + float* ptr = p + 16 * 16 * tile_num; + __imma_st_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + } + } + + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(float *p, const fragment& a, unsigned ldm, layout_t layout) { + if (layout == mem_row_major){ + for (int tile_num = 0; tile_num < 2; tile_num++) { + float* ptr = p + 16 * 16 * tile_num; + __imma_st_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + } + + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(float *p, const fragment& a, unsigned ldm, layout_t layout) { + if (layout == mem_row_major) { + for (int tile_num = 0; tile_num < 2; tile_num++) { + float* ptr = p + 16 * 16 * tile_num; + __imma_st_row_b32(&(a.x[tile_num * 4]), ptr); + } + } + } + + // + // Store functions for frags of A, B, C, D: F32, F32, F32, F32 + // + __CUDA_MMA_DEVICE_DECL__ void store_matrix_sync(float *p, const fragment& a, unsigned ldm, layout_t layout) { + if (layout == mem_row_major) + __imma_st_row_b32(&(a.x[0]), p); + } + + // + // MMA functions for A, B, C, D: I8, I8, I32, I32 + // +#ifdef __MR__ + template + __CUDA_MMA_DEVICE_DECL__ void mma_sync_tcu(fragmentIx& d, const FragmentARowB8& a, const FragmentBColB8& b, const fragmentIx& c) { + *((v4i32*)&d) = __ivcorex_matrix_mad_i32x4_i8x8(*(v2i32*)&a, *(v2i32*)&b, *(v4i32*)&c); + } + + template + __CUDA_MMA_DEVICE_DECL__ void mma_sync_tcu(fragmentIx& d, const FragmentAColB8& a, const FragmentBRowB8& b, const fragmentIx& c) { + *((v4i32*)&d) = __ivcorex_matrix_mad_i32x4_i8x8(*(v2i32*)&a, *(v2i32*)&b, *(v4i32*)&c); + } + + template + __CUDA_MMA_DEVICE_DECL__ void mma_sync_tcu(fragmentIx& d, const FragmentARowB8& a, const FragmentBRowB8& b, const fragmentIx& c) { + *((v4i32*)&d) = __ivcorex_matrix_mad_i32x4_i8x8(*(v2i32*)&a, *(v2i32*)&b, *(v4i32*)&c); + } + + template + __CUDA_MMA_DEVICE_DECL__ void mma_sync_tcu(fragmentIx& d, const FragmentAColB8& a, const FragmentBColB8& b, const fragmentIx& c) { + *((v4i32*)&d) = __ivcorex_matrix_mad_i32x4_i8x8(*(v2i32*)&a, *(v2i32*)&b, *(v4i32*)&c); + } +#endif /* __MR__ */ + + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { +#ifdef __BI__ + /** + * A: A0A1A2A3 B: B0 + * B1 + * B2 + * B3 + * + */ + // A0 * B0 + A1 * B1 + A2 * B2 + A3 * B3 + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_i32x4_i8x4(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x))), reinterpret_cast(c.x)); + + for (int tile_num = 1; tile_num < 4; tile_num++) { + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_i32x4_i8x4(*(reinterpret_cast(&(a.x)) + tile_num), *(reinterpret_cast(&(b.x)) + tile_num), reinterpret_cast(d.x)); + } +#endif /* __BI__ */ + +#ifdef __MR__ + /** + * A: A0A1 B: B0 + * B1 + * + */ + // A0 * B0 + A1 * B1 + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_i32x4_i8x8(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x))), reinterpret_cast(c.x)); + + for (int tile_num = 1; tile_num < 2; tile_num++) { + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_i32x4_i8x8(*(reinterpret_cast(&(a.x)) + tile_num), *(reinterpret_cast(&(b.x)) + tile_num), reinterpret_cast(d.x)); + } +#endif /* __MR__ */ + } + +#ifdef __BI__ + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { + /* + A: A0 B: B0B1B2B3 + A1 + A2 + A3 + */ + for (int row_tile = 0; row_tile < 4; row_tile++) { + for (int column_tile = 0; column_tile < 4; column_tile++) { + *(reinterpret_cast(&(d.x)) + 4 * row_tile + column_tile) = __ivcorex_matrix_mad_i32x4_i8x4(*(reinterpret_cast(&(a.x)) + row_tile), *(reinterpret_cast(&(b.x)) + column_tile), *(reinterpret_cast(&(c.x)) + 4 * row_tile + column_tile)); + } + } + } +#endif /* __BI__ */ + +#ifdef __MR__ + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { + /* + A: A0 B: B0B1B2B3 C: C0C1C2C3 + A1 C4C5C6C7 + A2 C8C9C10C11 + A3 C12C13C14C15 + */ + v2i32 a_tile, b_tile; + int a_start_vreg, b_start_vreg; + for (int row_tile = 0; row_tile < 4; row_tile++) { + a_start_vreg = row_tile; + a_tile[0] = *(reinterpret_cast(&(a.x)) + a_start_vreg); + a_tile[1] = *(reinterpret_cast(&(a.x)) + 4 + a_start_vreg); + + + for (int column_tile = 0; column_tile < 4; column_tile++) { + b_start_vreg = column_tile; + b_tile[0] = *(reinterpret_cast(&(b.x)) + b_start_vreg); + b_tile[1] = *(reinterpret_cast(&(b.x)) + 4 + b_start_vreg); + + *(reinterpret_cast(&(d.x)) + 4 * row_tile + column_tile) = __ivcorex_matrix_mad_i32x4_i8x8(reinterpret_cast(a_tile), reinterpret_cast(b_tile), *(reinterpret_cast(&(c.x)) + 4 * row_tile + column_tile)); + } + } +} +#endif /* __MR__ */ + + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { +#ifdef __BI__ + /* + A: A0A1A2A3 B: B0B1B2B3 C: C0C1C2C3 + B4B5B6B7 + B8B9B10B11 + B12B13B14B15 + */ + // A0 * B0 + A1 * B4 + A2 * B8 + A3 * B12 + // A0 * B1 + A1 * B5 + A2 * B9 + A3 * B13 + // A0 * B2 + A1 * B6 + A2 * B10 + A3 * B14 + // A0 * B3 + A1 * B7 + A2 * B11 + A3 * B15 + for (int start_tile = 0; start_tile < 4; start_tile++) { + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_i32x4_i8x4(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x)) + start_tile), *(reinterpret_cast(&(c.x)) + start_tile)); + } + + for (int start_tile = 0; start_tile < 4; start_tile++) { + for (int tile_step = 1; tile_step < 4; tile_step++) { + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_i32x4_i8x4(*(reinterpret_cast(&(a.x)) + tile_step), *(reinterpret_cast(&(b.x)) + start_tile + 4 * tile_step), *(reinterpret_cast(&(d.x)) + start_tile)); + } + } +#endif /* __BI__ */ + +#ifdef __MR__ + /* + A: A0A1 B: B0B1B2B3 C: C0C1C2C3 + B4B5B6B7 + */ + // A0 * B0 + A1 * B4 + // A0 * B1 + A1 * B5 + // A0 * B2 + A1 * B6 + // A0 * B3 + A1 * B7 + v2i32 b_tile; + int start_vreg = 0; + + for (int start_tile = 0; start_tile < 4; start_tile++) { + start_vreg = start_tile; + b_tile[0] = *(reinterpret_cast(&(b.x)) + start_vreg); + b_tile[1] = *(reinterpret_cast(&(b.x)) + 4 + start_vreg); + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_i32x4_i8x8(reinterpret_cast(a.x), reinterpret_cast(b_tile), *(reinterpret_cast(&(c.x)) + start_tile)); + } + + for (int start_tile = 0; start_tile < 4; start_tile++) { + start_vreg = 8 + start_tile; + b_tile[0] = *(reinterpret_cast(&(b.x)) + start_vreg); + b_tile[1] = *(reinterpret_cast(&(b.x)) + 4 + start_vreg); + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_i32x4_i8x8(*(reinterpret_cast(&(a.x)) + 1), reinterpret_cast(b_tile), *(reinterpret_cast(&(d.x)) + start_tile)); + } +#endif /* __MR__ */ + } + + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { +#ifdef __BI__ + /* + A: A0 A4 A8 A12 B: B0 C: C0 + A1 A5 A9 A13 B1 C1 + A2 A6 A10 A14 B2 C2 + A3 A7 A11 A15 B3 C3 + + */ + // A0 * B0 + A4 * B1 + A8 * B2 + A12 * B3 + // A1 * B0 + A5 * B1 + A9 * B2 + A13 * B3 + // A2 * B0 + A6 * B1 + A10 * B2 + A14 * B3 + // A3 * B0 + A7 * B1 + A11 * B2 + A15 * B3 + for (int start_tile = 0; start_tile < 4; start_tile++) { + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_i32x4_i8x4(*(reinterpret_cast(&(a.x)) + start_tile), *(reinterpret_cast(&(b.x))), *(reinterpret_cast(&(c.x)) + start_tile)); + } + + for (int start_tile = 0; start_tile < 4; start_tile++) { + for (int tile_step = 1; tile_step < 4; tile_step++) { + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_i32x4_i8x4(*(reinterpret_cast(&(a.x)) + start_tile + 4 * tile_step), *(reinterpret_cast(&(b.x)) + tile_step), *(reinterpret_cast(&(d.x)) + start_tile)); + } + } +#endif /* __BI__ */ + +#ifdef __MR__ + /* + A: A0 A4 B: B0 C: C0 + A1 A5 B1 C1 + A2 A6 C2 + A3 A7 C3 + + */ + // A0 * B0 + A4 * B1 + // A1 * B0 + A5 * B1 + // A2 * B0 + A6 * B1 + // A3 * B0 + A7 * B1 + v2i32 a_tile; + int start_vreg = 0; + + for (int start_tile = 0; start_tile < 4; start_tile++) { + start_vreg = start_tile; + a_tile[0] = *(reinterpret_cast(&(a.x)) + start_vreg); + a_tile[1] = *(reinterpret_cast(&(a.x)) + 4 + start_vreg); + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_i32x4_i8x8(reinterpret_cast(a_tile), reinterpret_cast(b.x), *(reinterpret_cast(&(c.x)) + start_tile)); + } + + for (int start_tile = 0; start_tile < 4; start_tile++) { + start_vreg = 8 + start_tile; + a_tile[0] = *(reinterpret_cast(&(a.x)) + start_vreg); + a_tile[1] = *(reinterpret_cast(&(a.x)) + 4 + start_vreg); + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_i32x4_i8x8(reinterpret_cast(a_tile), *(reinterpret_cast(&(b.x)) + 1), *(reinterpret_cast(&(d.x)) + start_tile)); + } +#endif /* __MR__ */ + } + + // + // MMA functions for A, B, C, D: U8, U8, U32, U32 + // + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { +#ifdef __BI__ + /** + * A: A0A1A2A3 B: B0 + * B1 + * B2 + * B3 + * + */ + // A0 * B0 + A1 * B1 + A2 * B2 + A3 * B3 + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_u32x4_u8x4(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x))), reinterpret_cast(c.x)); + + for (int tile_num = 1; tile_num < 4; tile_num++) { + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_u32x4_u8x4(*(reinterpret_cast(&(a.x)) + tile_num), *(reinterpret_cast(&(b.x)) + tile_num), reinterpret_cast(d.x)); + } +#endif /* __BI__ */ + +#ifdef __MR__ + /** + * A: A0A1 B: B0 + * B1 + * + */ + // A0 * B0 + A1 * B1 + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_u32x4_u8x8(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x))), reinterpret_cast(c.x)); + + for (int tile_num = 1; tile_num < 2; tile_num++) { + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_u32x4_u8x8(*(reinterpret_cast(&(a.x)) + tile_num), *(reinterpret_cast(&(b.x)) + tile_num), reinterpret_cast(d.x)); + } +#endif /* __MR__ */ + } + +#ifdef __BI__ + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { + /* + A: A0 B: B0B1B2B3 + A1 + A2 + A3 + */ + for (int row_tile = 0; row_tile < 4; row_tile++) { + for (int column_tile = 0; column_tile < 4; column_tile++) { + *(reinterpret_cast(&(d.x)) + 4 * row_tile + column_tile) = __ivcorex_matrix_mad_i32x4_i8x4(*(reinterpret_cast(&(a.x)) + row_tile), *(reinterpret_cast(&(b.x)) + column_tile), *(reinterpret_cast(&(c.x)) + 4 * row_tile + column_tile)); + } + } + } +#endif /* __BI__ */ + +#ifdef __MR__ + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { + /* + A: A0 B: B0B1B2B3 C: C0C1C2C3 + A1 C4C5C6C7 + A2 C8C9C10C11 + A3 C12C13C14C15 + */ + v2i32 a_tile, b_tile; + int a_start_vreg, b_start_vreg; + for (int row_tile = 0; row_tile < 4; row_tile++) { + a_start_vreg = row_tile; + a_tile[0] = *(reinterpret_cast(&(a.x)) + a_start_vreg); + a_tile[1] = *(reinterpret_cast(&(a.x)) + 4 + a_start_vreg); + + + for (int column_tile = 0; column_tile < 4; column_tile++) { + b_start_vreg = column_tile; + b_tile[0] = *(reinterpret_cast(&(b.x)) + b_start_vreg); + b_tile[1] = *(reinterpret_cast(&(b.x)) + 4 + b_start_vreg); + + *(reinterpret_cast(&(d.x)) + 4 * row_tile + column_tile) = __ivcorex_matrix_mad_i32x4_i8x8(reinterpret_cast(a_tile), reinterpret_cast(b_tile), *(reinterpret_cast(&(c.x)) + 4 * row_tile + column_tile)); + } + } +} +#endif /* __MR__ */ + + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { +#ifdef __BI__ + /* + A: A0A1A2A3 B: B0B1B2B3 C: C0C1C2C3 + B4B5B6B7 + B8B9B10B11 + B12B13B14B15 + */ + // A0 * B0 + A1 * B4 + A2 * B8 + A3 * B12 + // A0 * B1 + A1 * B5 + A2 * B9 + A3 * B13 + // A0 * B2 + A1 * B6 + A2 * B10 + A3 * B14 + // A0 * B3 + A1 * B7 + A2 * B11 + A3 * B15 + for (int start_tile = 0; start_tile < 4; start_tile++) { + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_u32x4_u8x4(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x)) + start_tile), *(reinterpret_cast(&(c.x)) + start_tile)); + } + + for (int start_tile = 0; start_tile < 4; start_tile++) { + for (int tile_step = 1; tile_step < 4; tile_step++) { + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_u32x4_u8x4(*(reinterpret_cast(&(a.x)) + tile_step), *(reinterpret_cast(&(b.x)) + start_tile + 4 * tile_step), *(reinterpret_cast(&(d.x)) + start_tile)); + } + } +#endif /* __BI__ */ + +#ifdef __MR__ + /* + A: A0A1 B: B0B1B2B3 C: C0C1C2C3 + B4B5B6B7 + */ + // A0 * B0 + A1 * B4 + // A0 * B1 + A1 * B5 + // A0 * B2 + A1 * B6 + // A0 * B3 + A1 * B7 + v2i32 b_tile; + int start_vreg = 0; + + for (int start_tile = 0; start_tile < 4; start_tile++) { + start_vreg = start_tile; + b_tile[0] = *(reinterpret_cast(&(b.x)) + start_vreg); + b_tile[1] = *(reinterpret_cast(&(b.x)) + 4 + start_vreg); + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_u32x4_u8x8(reinterpret_cast(a.x), reinterpret_cast(b_tile), *(reinterpret_cast(&(c.x)) + start_tile)); + } + + for (int start_tile = 0; start_tile < 4; start_tile++) { + start_vreg = 8 + start_tile; + b_tile[0] = *(reinterpret_cast(&(b.x)) + start_vreg); + b_tile[1] = *(reinterpret_cast(&(b.x)) + 4 + start_vreg); + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_u32x4_u8x8(*(reinterpret_cast(&(a.x)) + 1), reinterpret_cast(b_tile), *(reinterpret_cast(&(d.x)) + start_tile)); + } +#endif /* __MR__ */ + } + + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { +#ifdef __BI__ + /* + A: A0 A4 A8 A12 B: B0 C: C0 + A1 A5 A9 A13 B1 C1 + A2 A6 A10 A14 B2 C2 + A3 A7 A11 A15 B3 C3 + + */ + // A0 * B0 + A4 * B1 + A8 * B2 + A12 * B3 + // A1 * B0 + A5 * B1 + A9 * B2 + A13 * B3 + // A2 * B0 + A6 * B1 + A10 * B2 + A14 * B3 + // A3 * B0 + A7 * B1 + A11 * B2 + A15 * B3 + for (int start_tile = 0; start_tile < 4; start_tile++) { + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_u32x4_u8x4(*(reinterpret_cast(&(a.x)) + start_tile), *(reinterpret_cast(&(b.x))), *(reinterpret_cast(&(c.x)) + start_tile)); + } + + for (int start_tile = 0; start_tile < 4; start_tile++) { + for (int tile_step = 1; tile_step < 4; tile_step++) { + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_u32x4_u8x4(*(reinterpret_cast(&(a.x)) + start_tile + 4 * tile_step), *(reinterpret_cast(&(b.x)) + tile_step), *(reinterpret_cast(&(d.x)) + start_tile)); + } + } +#endif /* __BI__ */ + +#ifdef __MR__ + /* + A: A0 A4 B: B0 C: C0 + A1 A5 B1 C1 + A2 A6 C2 + A3 A7 C3 + + */ + // A0 * B0 + A4 * B1 + // A1 * B0 + A5 * B1 + // A2 * B0 + A6 * B1 + // A3 * B0 + A7 * B1 + v2i32 a_tile; + int start_vreg = 0; + + for (int start_tile = 0; start_tile < 4; start_tile++) { + start_vreg = start_tile; + a_tile[0] = *(reinterpret_cast(&(a.x)) + start_vreg); + a_tile[1] = *(reinterpret_cast(&(a.x)) + 4 + start_vreg); + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_u32x4_u8x8(reinterpret_cast(a_tile), reinterpret_cast(b.x), *(reinterpret_cast(&(c.x)) + start_tile)); + } + + for (int start_tile = 0; start_tile < 4; start_tile++) { + start_vreg = 8 + start_tile; + a_tile[0] = *(reinterpret_cast(&(a.x)) + start_vreg); + a_tile[1] = *(reinterpret_cast(&(a.x)) + 4 + start_vreg); + *(reinterpret_cast(&(d.x)) + start_tile) = __ivcorex_matrix_mad_u32x4_u8x8(reinterpret_cast(a_tile), *(reinterpret_cast(&(b.x)) + 1), *(reinterpret_cast(&(d.x)) + start_tile)); + } +#endif /* __MR__ */ + } + + // + // MMA functions for A, B, C, D: F16, F16, F32, F32 + // +template + __CUDA_MMA_DEVICE_DECL__ void mma_sync_tcu(fragmentIx& d, const FragmentARowB16& a, const FragmentBColB16& b, const fragmentIx& c) { + *((v4f32*)&d) = __ivcorex_matrix_mad_f32x4_f16x4(*(v4f16*)&a, *(v4f16*)&b, *(v4f32*)&c); + } + +template + __CUDA_MMA_DEVICE_DECL__ void mma_sync_tcu(fragmentIx& d, const FragmentAColB16& a, const FragmentBRowB16& b, const fragmentIx& c) { + *((v4f32*)&d) = __ivcorex_matrix_mad_f32x4_f16x4(*(v4f16*)&a, *(v4f16*)&b, *(v4f32*)&c); + } + +template + __CUDA_MMA_DEVICE_DECL__ void mma_sync_tcu(fragmentIx& d, const FragmentARowB16& a, const FragmentBRowB16& b, const fragmentIx& c) { + *((v4f32*)&d) = __ivcorex_matrix_mad_f32x4_f16x4(*(v4f16*)&a, *(v4f16*)&b, *(v4f32*)&c); + } + +template + __CUDA_MMA_DEVICE_DECL__ void mma_sync_tcu(fragmentIx& d, const FragmentAColB16& a, const FragmentBColB16& b, const fragmentIx& c) { + *((v4f32*)&d) = __ivcorex_matrix_mad_f32x4_f16x4(*(v4f16*)&a, *(v4f16*)&b, *(v4f32*)&c); + } + + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { + + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_f32x4_f16x4(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x))), reinterpret_cast(c.x)); + + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_f32x4_f16x4(*(reinterpret_cast(&(a.x)) + 1), *(reinterpret_cast(&(b.x)) + 1), reinterpret_cast(d.x)); + } + + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { + /** + * A: A0 B: B0B1 + * A1 + */ + for (int row_tile = 0; row_tile < 2; row_tile++) { + for (int column_tile = 0; column_tile < 2; column_tile++) { + *(reinterpret_cast(&(d.x)) + 2 * row_tile + column_tile) = __ivcorex_matrix_mad_f32x4_f16x4(*(reinterpret_cast(&(a.x)) + row_tile), *(reinterpret_cast(&(b.x)) + column_tile), *(reinterpret_cast(&(c.x)) + 2 * row_tile + column_tile)); + } + } + } + + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { + /* + A: A0A1 B: B0B1 a.x[0] a.x[2] + ------- B0 => ------ B1 => ------- + B2B3 a.x[1] a.x[3] + */ + // A0 * B0 + A1 * B2 + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_f32x4_f16x4(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x))), reinterpret_cast(c.x)); + + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_f32x4_f16x4(*(reinterpret_cast(&(a.x)) + 1), *(reinterpret_cast(&(b.x)) + 2), *(reinterpret_cast(&(c.x)))); + + // A0 * B1 + A1 * B3 + *(reinterpret_cast(&(d.x)) + 1) = __ivcorex_matrix_mad_f32x4_f16x4(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x)) + 1), *(reinterpret_cast(&(c.x)) + 1)); + + *(reinterpret_cast(&(d.x)) + 1) = __ivcorex_matrix_mad_f32x4_f16x4(*(reinterpret_cast(&(a.x)) + 1), *(reinterpret_cast(&(b.x)) + 3), *(reinterpret_cast(&(d.x)) + 1)); + } + + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { + /* + A: |A0|A2| B: |B0| a.x[0] a.x[2] C: C0 + ------- ---- A0 => ------ A1 => ------- -- + |A1|A3| |B1| a.x[1] a.x[3] C1 + + */ + // A0 * B0 + A2 * B1 + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_f32x4_f16x4(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x))), reinterpret_cast(c.x)); + + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_f32x4_f16x4(*(reinterpret_cast(&(a.x)) + 2), *(reinterpret_cast(&(b.x)) + 1), *(reinterpret_cast(&(d.x)))); + + // A1 * B0 + A3 * B1 + *(reinterpret_cast(&(d.x)) + 1) = __ivcorex_matrix_mad_f32x4_f16x4(*(reinterpret_cast(&(a.x)) + 1), *(reinterpret_cast(&(b.x))), *(reinterpret_cast(&(c.x)) + 1)); + + *(reinterpret_cast(&(d.x)) + 1) = __ivcorex_matrix_mad_f32x4_f16x4(*(reinterpret_cast(&(a.x)) + 3), *(reinterpret_cast(&(b.x)) + 1), *(reinterpret_cast(&(d.x)) + 1)); + } + + // + // MMA functions for A, B, C, D: F32, F32, F32, F32 + // + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_f32x4_f32x4(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x))), *(reinterpret_cast(&(c.x)))); + } + + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_f32x4_f32x4(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x))), *(reinterpret_cast(&(c.x)))); + } + + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_f32x4_f32x4(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x))), *(reinterpret_cast(&(c.x)))); + } + + __CUDA_MMA_DEVICE_DECL__ void mma_sync(fragment& d, const fragment& a, const fragment& b, const fragment& c) { + *(reinterpret_cast(&(d.x))) = __ivcorex_matrix_mad_f32x4_f32x4(*(reinterpret_cast(&(a.x))), *(reinterpret_cast(&(b.x))), *(reinterpret_cast(&(c.x)))); + } +}; +}; + +#undef __DEF_IF_HOST +#undef __BI__ +#undef __MR__ +#undef __CUDA_MMA_DEVICE_DECL__ +#endif /* !__CUDA_ARCH__ || __ILUVATAR__ */ + +#endif /* __cplusplus && __CUDACC__ */ + +#endif /* __ILUVATAR_MMA_HPP__ */ + +#if defined(__UNDEF_CUDA_INCLUDE_COMPILER_INTERNAL_HEADERS_CUDA_MMA_H__) +#undef __CUDA_INCLUDE_COMPILER_INTERNAL_HEADERS__ +#undef __UNDEF_CUDA_INCLUDE_COMPILER_INTERNAL_HEADERS_CUDA_MMA_H__ +#endif \ No newline at end of file diff --git a/cat_files/ixinfer.h b/cat_files/ixinfer.h new file mode 100644 index 00000000..b4e1de2a --- /dev/null +++ b/cat_files/ixinfer.h @@ -0,0 +1,4058 @@ +/** + * @brief Libinfer the fast cuda library for inference. + * @file ixinfer.h + */ + +#pragma GCC visibility push(default) +#if !defined(CUINFER_H_) +#define CUINFER_H_ + +/// Libinfer version major = 7. +#define CUINFER_MAJOR 7 +/// Libinfer version minor = 6. +#define CUINFER_MINOR 6 +/// Libinfer version patchlevel = 5. +#define CUINFER_PATCHLEVEL 5 + +/// Libinfer version = ::CUINFER_MAJOR * 1000 + ::CUINFER_MINOR * 100 + +/// ::CUINFER_PATCHLEVEL +#define CUINFER_VERSION \ + (CUINFER_MAJOR * 1000 + CUINFER_MINOR * 100 + CUINFER_PATCHLEVEL) + +/// Libinfer priv version major = 3. +#define CUINFER_PRIV_MAJOR 3 +/// Libinfer priv version minor = 3. +#define CUINFER_PRIV_MINOR 3 +/// Libinfer priv version patch = 0. +#define CUINFER_PRIV_PATCH 0 + +/// Libinfer priv version = ::CUINFER_PRIV_MAJOR * 1000 + ::CUINFER_PRIV_MINOR * +/// 100 + ::CUINFER_PRIV_PATCH +#define CUINFER_PRIV_VERSION \ + (CUINFER_PRIV_MAJOR * 1000 + CUINFER_PRIV_MINOR * 100 + CUINFER_PRIV_PATCH) + +#include +#include +#include + +#ifndef CUINFERWINAPI +#ifdef _WIN32 +#define CUINFERWINAPI __stdcall +#else +#define CUINFERWINAPI +#endif +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +struct cuinferContext; +/// @brief ::cuinferHandle_t is a point of struct to store ixinfer internal +/// info, e.g stream info. +/// @details The ::cuinferHandle_t is used in many cuinfer APIs. It must be +/// created with ::cuinferCreate before use and be destroyed after use by +/// ::cuinferDestroy. +/// @see ::cuinferCreate, ::cuinferDestroy +typedef struct cuinferContext *cuinferHandle_t; + +/// @brief Return current cuinfer version. +/// @return ::CUINFER_VERSION +size_t CUINFERWINAPI cuinferGetVersion(void); + +/// Returns CUDA Runtime version statically linked against cuinfer. +size_t CUINFERWINAPI cuinferGetCudartVersion(void); + +/// Infer return status. +typedef enum { + CUINFER_STATUS_SUCCESS = 0, ///< Success. Everything goes well. + CUINFER_STATUS_NOT_INITIALIZED = 1, ///< Nullptr or struct not initilized. + CUINFER_STATUS_ALLOC_FAILED = 2, ///< Memory allocation falied. + CUINFER_STATUS_BAD_PARAM = + 3, ///< Bad parameters or bad combination of parameters. + CUINFER_STATUS_INTERNAL_ERROR = + 4, ///< Internal error, which should not happen. Should be fixed. + CUINFER_STATUS_INVALID_VALUE = 5, ///< Invalid single value. + CUINFER_STATUS_ARCH_MISMATCH = + 6, ///< Libinfer is built for specific target, i.e. MR. Runing MR code on + ///< BI will raise this error. + CUINFER_STATUS_MAPPING_ERROR = 7, ///< Not used. + CUINFER_STATUS_EXECUTION_FAILED = 8, ///< Cuda api execution failed. + CUINFER_STATUS_NOT_SUPPORTED = 9, ///< Under development or not supported. + CUINFER_STATUS_LICENSE_ERROR = 10, ///< License error. + CUINFER_STATUS_RUNTIME_PREREQUISITE_MISSING = 11, ///< Not used. + CUINFER_STATUS_RUNTIME_IN_PROGRESS = 12, ///< Not used. + CUINFER_STATUS_RUNTIME_FP_OVERFLOW = 13, ///< Not used. +} cuinferStatus_t; + +/// @brief Return human-readable error messages. +/// @param[in] status The status to inspect. +/// @return Explaination to the status. +const char *CUINFERWINAPI cuinferGetErrorString(cuinferStatus_t status); + +#ifndef __LIBRARY_TYPES_H__ + +/// Library property types. +typedef enum libraryPropertyType_t { + MAJOR_VERSION, + MINOR_VERSION, + PATCH_LEVEL, +} libraryPropertyType; + +#endif + +/// @brief Get libraryPropertyType. +/// @param[in] type Library property type to query. +/// @param[out] value Correspond return value. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_NOT_SUPPORTED If out of range. +cuinferStatus_t CUINFERWINAPI cuinferGetProperty(libraryPropertyType type, + int *value); + +/// @brief Create a libinfer handle. +/// @note This handle use the default \p cudaStream_t 0, which is synchroized +/// before and after other all other cuda operations. Use ::cuinferSetStream to +/// custom cuinfer stream to interleave compute and memory operations. +/// @note ::cuinferDestroy should be used to destoy a \p handle. +/// @param[out] handle The pointer to handle. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p handle is null. +/// * ::CUINFER_STATUS_ALLOC_FAILED If alloc failed. +cuinferStatus_t CUINFERWINAPI cuinferCreate(cuinferHandle_t *handle); + +/// @brief Destroy a libinfer handle. +/// @param[in] handle The handle to destory. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_INTERNAL_ERROR If internal error happened. +cuinferStatus_t CUINFERWINAPI cuinferDestroy(cuinferHandle_t handle); + +/// @brief Set a \p cudaStream_t to a \p handle. +/// @details All operation associated with this \p handle will use this p +/// @param[in] handle The target ::cuinferHandle_t. +/// @param[in] streamId The new \p cudaStream_t to put. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If handle is null. +/// * ::CUINFER_STATUS_INTERNAL_ERROR If internal error happened. +cuinferStatus_t CUINFERWINAPI cuinferSetStream(cuinferHandle_t handle, + cudaStream_t streamId); + +/// @brief Get a \p cudaStream_t corresponding to a \p handle. +/// @param[in] handle The target ::cuinferHandle_t. +/// @param[out] streamId The \p cudaStream_t to get. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If handle is null. +/// * ::CUINFER_STATUS_INTERNAL_ERROR If internal error happened. +cuinferStatus_t CUINFERWINAPI cuinferGetStream(cuinferHandle_t handle, + cudaStream_t *streamId); + +/// @brief Pointer to tensor descriptions. +/// @details Contains tensor ::cuinferTensorFormat_t, strides and dimensions +/// infos. +/// @see ::cuinferCreateTensorDescriptor, ::cuinferDestroyTensorDescriptor, +/// ::cuinferSetTensor4dDescriptor, ::cuinferSetTensor4dDescriptorEx, +/// ::cuinferSetTensorNdDescriptor, ::cuinferSetTensorNdDescriptorEx, +/// ::cuinferGetTensor4dDescriptor, ::cuinferGetTensorNdDescriptor and +/// ::cuinferGetTensorSizeInBytes. +typedef struct cuinferTensorStruct *cuinferTensorDescriptor_t; + +/// @brief Pointer to convolution descriptions. +/// @details Contains padding, stride, dilation, ::cuinferConvolutionMode_t, +/// ::cuinferDataType_t, ::cuinferMathType_t and group_count infos. +/// @see ::cuinferCreateConvolutionDescriptor, +/// ::cuinferDestroyConvolutionDescriptor, ::cuinferSetConvolutionGroupCount, +/// ::cuinferSetConvolution2dDescriptor, ::cuinferSetConvolutionNdDescriptor, +/// ::cuinferGetConvolutionMathType, ::cuinferGetConvolutionGroupCount, +/// ::cuinferGetConvolution2dDescriptor, +/// ::cuinferGetConvolution2dForwardOutputDim, +/// ::cuinferGetConvolutionNdDescriptor and +/// ::cuinferGetConvolutionNdForwardOutputDim. +typedef struct cuinferConvolutionStruct *cuinferConvolutionDescriptor_t; + +/// @brief Pointer to pooling layer descriptions. +/// @details Contains ::cuinferPoolingMode_t, ::cuinferNanPropagation_t, +/// window_dim, padding and stride infos. +/// @see ::cuinferCreatePoolingDescriptor, ::cuinferDestroyPoolingDescriptor, +/// ::cuinferSetPooling2dDescriptor, ::cuinferSetPoolingNdDescriptor, +/// ::cuinferGetPooling2dDescriptor, ::cuinferGetPoolingNdDescriptor, +/// ::cuinferGetPoolingNdForwardOutputDim and +/// ::cuinferGetPooling2dForwardOutputDim. +typedef struct cuinferPoolingStruct *cuinferPoolingDescriptor_t; + +/// @brief Pointer to filter tensor descriptions. +/// @details Contains ::cuinferDataType_t, ::cuinferTensorFormat_t and +/// dimentions infos. +/// @see ::cuinferCreateFilterDescriptor, ::cuinferDestroyFilterDescriptor, +/// ::cuinferSetFilter4dDescriptor, ::cuinferSetFilterNdDescriptor, +/// ::cuinferGetFilter4dDescriptor and ::cuinferGetFilterNdDescriptor. +typedef struct cuinferFilterStruct *cuinferFilterDescriptor_t; + +/// @brief Pointer to LRN(Learning Resource Network) descriptions. +/// @details Contains LRN's \p n, \p alpha, \p beta ane \p k infos. +/// @see ::cuinferCreateLRNDescriptor, ::cuinferDestroyLRNDescriptor, +/// ::cuinferSetLRNDescriptor and ::cuinferGetLRNDescriptor. +typedef struct cuinferLRNStruct *cuinferLRNDescriptor_t; + +/// @brief Pointer to activation descriptions. +/// @details Contains ::cuinferActivationMode_t, ::cuinferNanPropagation_t and +/// coef infos. +/// @note The coef can mean different param in different +/// ::cuinferActivationMode_t, i.e. ceiling for clipped RELU, alpha for ELU. +/// @see ::cuinferCreateActivationDescriptor, +/// ::cuinferDestroyActivationDescriptor, ::cuinferSetActivationDescriptor and +/// ::cuinferGetActivationDescriptor. +typedef struct cuinferActivationStruct *cuinferActivationDescriptor_t; + +/// @brief Pointer to reduce tensor descriptions. +/// @details Contains ::cuinferReduceTensorOp_t, ::cuinferDataType_t, +/// ::cuinferNanPropagation_t, ::cuinferReduceTensorIndices_t and +/// ::cuinferIndicesType_t infos. +/// @see ::cuinferCreateReduceTensorDescriptor, +/// ::cuinferCreateReduceTensorDescriptor and +/// ::cuinferSetReduceTensorDescriptor. +typedef struct cuinferReduceTensorStruct *cuinferReduceTensorDescriptor_t; + +/// @brief Pointer to CTC(Connectionist temporal classification) loss +/// descriptions. +/// @details Contains ::cuinferDataType_t, ::cuinferLossNormalizationMode_t and +/// ::cuinferNanPropagation_t. +/// @see ::cuinferCreateCTCLossDescriptor, ::cuinferDestroyCTCLossDescriptor, +/// ::cuinferSetCTCLossDescriptor, ::cuinferSetCTCLossDescriptorEx, +/// ::cuinferGetCTCLossDescriptor and ::cuinferGetCTCLossDescriptorEx. +typedef struct cuinferCTCLossStruct *cuinferCTCLossDescriptor_t; + +/// Libinfer data types. +typedef enum { + CUINFER_DATA_FLOAT = 0, ///< 32-bit ieee float type. + CUINFER_DATA_DOUBLE = 1, ///< 64-bit ieee double float type. + CUINFER_DATA_HALF = 2, ///< 16-bit ieee half float type. + CUINFER_DATA_INT8 = 3, ///< 8-bit signed integer type. + CUINFER_DATA_INT32 = 4, ///< 32-bit signed integer type. + CUINFER_DATA_INT8x4 = 5, ///< 4x8-bit signed integer type. Aligned to 4 bytes. + CUINFER_DATA_UINT8 = 6, ///< 8-bit unsigned integer type. + CUINFER_DATA_UINT8x4 = + 7, ///< 4x8-bit unsigned integer type. Aligned to 4 bytes. + CUINFER_DATA_INT8x32 = + 8, ///< 32x8-bit signed integer type. Aligned to 32 bytes. + CUINFER_DATA_BFLOAT16 = 9, ///< Google's brain floating point. 16-bit. +} cuinferDataType_t; + +/// Libinfer math type. +typedef enum { + CUINFER_DEFAULT_MATH = 0, ///< Default math type. + CUINFER_TENSOR_OP_MATH = 1, ///< Perffer to use tensor op. + CUINFER_TENSOR_OP_MATH_ALLOW_CONVERSION = 2, ///< Not used. +} cuinferMathType_t; + +/// @brief Libinfer propagate NaN(not a number) option. @details +/// ::cuinferNanPropagation_t is used to indicate if a float number result in +/// NaN(Not a Number) should be propagate nan or not (0 will be propagated +/// instead).This setting is only useful for float type computation. This is +/// used in setting ::cuinferReduceTensorDescriptor_t, +/// ::cuinferPoolingDescriptor_t, ::cuinferActivationDescriptor_t, +/// ::cuinferRNNDescriptor_t and ::cuinferCTCLossDescriptor_t. +typedef enum { + CUINFER_NOT_PROPAGATE_NAN = 0, ///< \p 0 will be propagating for \p NaN and \p + ///< Inf values in float types. + CUINFER_PROPAGATE_NAN = + 1, ///< \p NaN and \p Inf will be propagating in float types. +} cuinferNanPropagation_t; + +/// Is algorithm result determinstic(same input always produce same outputs). +typedef enum { + CUINFER_NON_DETERMINISTIC = 0, ///< Same input may poduce different outputs. + ///< Due to data race, i.e. atomic operations. + CUINFER_DETERMINISTIC = 1, ///< Same input always produce same outputs. +} cuinferDeterminism_t; + +/// Maximum supported number of tensor dimensions. +#define CUINFER_DIM_MAX 8 + +/// @brief Create an instance of a generic Tensor descriptor. +/// @note ::cuinferDestroyTensorDescriptor should be called after use. +/// @param[out] tensorDesc Pointer to store ::cuinferTensorDescriptor_t. +cuinferStatus_t CUINFERWINAPI +cuinferCreateTensorDescriptor(cuinferTensorDescriptor_t *tensorDesc); + +/// @brief Tensor format stored in memory. +/// @details +/// * ::CUINFER_TENSOR_NCHW tensor runs faster in CPUs. +/// * ::CUINFER_TENSOR_NHWC tensor runs faster in GPUs. +/// * ::CUINFER_TENSOR_NCHW_VECT_C split dim C and run faster in both. +typedef enum { + CUINFER_TENSOR_NCHW = 0, + ///< Elements are stored in batch, channel, depth(3d only), height and + ///< weight order(higher to lower). + CUINFER_TENSOR_NHWC = + 1, ///< Elements are stored in batch, depth(3d only), + ///< height, weight and channel order(higher to lower). + CUINFER_TENSOR_NCHW_VECT_C = 2, + ///< Elements are stored in batch, channel / 4, depth(3d only), height, + ///< weight, 4 order(higher to lower), where channel is split by 4 into 2 + ///< parts. +} cuinferTensorFormat_t; + +/// @brief Setup params for ::cuinferTensorDescriptor_t. +/// @param[out] tensorDesc Pointer to target ::cuinferTensorDescriptor_t. +/// @param[in] format Tensor format. +/// @param[in] dataType Tensor data type. +/// @param[in] n Tensor batch size. +/// @param[in] c Tensor channel size. +/// @param[in] h Tensor height. +/// @param[in] w Tensor width. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If param out of range or \p tensorDesc is null +/// or c is not multiple of 4 in ::CUINFER_TENSOR_NCHW_VECT_C. +cuinferStatus_t CUINFERWINAPI cuinferSetTensor4dDescriptor( + cuinferTensorDescriptor_t tensorDesc, cuinferTensorFormat_t format, + cuinferDataType_t dataType, int n, int c, int h, int w); + +/// @brief Setup params for ::cuinferTensorDescriptor_t. +/// @param[out] tensorDesc Pointer to target ::cuinferTensorDescriptor_t. +/// @param[in] dataType Tensor data type. +/// @param[in] n Tensor batch size. +/// @param[in] c Tensor channel size. +/// @param[in] h Tensor height. +/// @param[in] w Tensor width. +/// @param[in] nStride Stride of batch. +/// @param[in] cStride Stride of channel. +/// @param[in] hStride Stride of height. +/// @param[in] wStride Stride of width. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If param out of range or \p tensorDesc is null. +cuinferStatus_t CUINFERWINAPI cuinferSetTensor4dDescriptorEx( + cuinferTensorDescriptor_t tensorDesc, cuinferDataType_t dataType, int n, + int c, int h, int w, int nStride, int cStride, int hStride, int wStride); + +/// @brief Return params for ::cuinferTensorDescriptor_t. +/// @param[in] tensorDesc Pointer to target ::cuinferTensorDescriptor_t. +/// @param[out] dataType Tensor data type. +/// @param[out] n Tensor batch size. +/// @param[out] c Tensor channel size. +/// @param[out] h Tensor height. +/// @param[out] w Tensor width. +/// @param[out] nStride Stride of batch. +/// @param[out] cStride Stride of channel. +/// @param[out] hStride Stride of height. +/// @param[out] wStride Stride of width. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p tensorDesc is null. +cuinferStatus_t CUINFERWINAPI cuinferGetTensor4dDescriptor( + const cuinferTensorDescriptor_t tensorDesc, cuinferDataType_t *dataType, + int *n, int *c, int *h, int *w, int *nStride, int *cStride, int *hStride, + int *wStride); + +/// @brief Setup params for 2d/3d ::cuinferTensorDescriptor_t. +/// @details The input order(dim0/stride0, dim1/stride1, ...) is batch, channel, +/// depth(3d only), height and weight. +/// @note The ::CUINFER_TENSOR_NHWC format may change the strides. +/// @note Can not set ::CUINFER_TENSOR_NCHW_VECT_C format. +/// @see ::cuinferTensorFormat_t, ::cuinferSetTensorNdDescriptorEx +/// @param[out] tensorDesc Pointer to target ::cuinferTensorDescriptor_t. +/// @param[in] dataType Tensor data type. +/// @param[in] nbDims Number of dimensions. 4 for 2d conv and 5 for 3d conv. +/// @param[in] dimA Size of each dimension.Nchw for 2d and ncdhw for 3d. +/// @param[in] strideA Stride of each dimension. Nchw for 2d and ncdhw for 3d. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_NOT_SUPPORTED If \p nbDims not in range[4, +/// ::CUINFER_DIM_MAX]. +/// * ::CUINFER_STATUS_BAD_PARAM If \p tensorDesc is null or invalid dims. +cuinferStatus_t CUINFERWINAPI cuinferSetTensorNdDescriptor( + cuinferTensorDescriptor_t tensorDesc, cuinferDataType_t dataType, + int nbDims, const int dimA[], const int strideA[]); + +/// @brief Setup params for 2d/3d ::cuinferTensorDescriptor_t. +/// @details The input order(dim0/stride0, dim1/stride1, ...) is batch, channel, +/// depth(3d only), height and weight. +/// @note Strides is set according to \p format and \p nbDims. +/// @see ::cuinferTensorFormat_t, ::cuinferSetTensorNdDescriptor +/// @param[out] tensorDesc Pointer to target ::cuinferTensorDescriptor_t. +/// @param[in] format Tensor format. +/// @param[in] dataType Tensor data type. +/// @param[in] nbDims Number of dimensions. 4 for 2d conv and 5 for 3d conv. +/// @param[in] dimA Size of each dimension.Nchw for 2d and ncdhw for 3d. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_NOT_SUPPORTED If \p nbDims not in range[4, +/// ::CUINFER_DIM_MAX]. +/// * ::CUINFER_STATUS_BAD_PARAM If \p tensorDesc is null or invalid dims. +cuinferStatus_t CUINFERWINAPI cuinferSetTensorNdDescriptorEx( + cuinferTensorDescriptor_t tensorDesc, cuinferTensorFormat_t format, + cuinferDataType_t dataType, int nbDims, const int dimA[]); + +/// @brief Return params for 2d/3d ::cuinferTensorDescriptor_t. +/// @details The output order(dim0/stride0, dim1/stride1, ...) is batch, +/// channel, depth(3d only), height and weight. +/// @see cuinferSetTensorNdDescriptor +/// @param[in] tensorDesc Pointer to target ::cuinferTensorDescriptor_t. +/// @param[out] nbDimsRequested Not used. @todo \p nbDimsRequested not used. +/// @param[out] dataType Tensor data type. +/// @param[out] nbDims Number of dimensions. 4 for 2d conv and 5 for 3d conv. +/// @param[out] dimA Size of each dimension.Nchw for 2d and ncdhw for 3d. +/// @param[out] strideA Stride of each dimension. Nchw for 2d and ncdhw for 3d. +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p tensorDesc is null. +cuinferStatus_t CUINFERWINAPI cuinferGetTensorNdDescriptor( + const cuinferTensorDescriptor_t tensorDesc, int nbDimsRequested, + cuinferDataType_t *dataType, int *nbDims, int dimA[], int strideA[]); + +/// @brief Returns psysical space needed by a tensor. +/// @note The psysical space needed can be slightly larger than logical space +/// due to stride sittings(padding). +/// @param[in] tensorDesc Pointer to target ::cuinferTensorDescriptor_t. +/// @param[out] size Result size in bytes. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p tensorDesc is null. +cuinferStatus_t CUINFERWINAPI cuinferGetTensorSizeInBytes( + const cuinferTensorDescriptor_t tensorDesc, size_t *size); + +/// Destroy an instance of Tensor4d descriptor + +/// @brief Destroy an instance of ::cuinferTensorDescriptor_t. +/// @param[in] tensorDesc Pointer to target ::cuinferTensorDescriptor_t. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_INTERNAL_ERROR +cuinferStatus_t CUINFERWINAPI +cuinferDestroyTensorDescriptor(cuinferTensorDescriptor_t tensorDesc); + +/// @brief Tensor layout conversion helper y = alpha * x + beta * y. +/// @param[in] handle The libinfer handle. +/// @param[in] alpha Pointer to scaling factor in host memory. Type is always +/// float for now. +/// @param[in] xDesc Meta info of tensor x. +/// @param[in] x Input tensor data. +/// @param[in] beta Pointer to scaling factor in host memory. Type is always +/// float for now. +/// @param[in] yDesc Meta info of tensor y. +/// @param[in,out] y Input and output tensor data. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If bad params. +/// * ::CUINFER_STATUS_INTERNAL_ERROR If internal error happened. +/// * ::CUINFER_STATUS_NOT_SUPPORTED If algo not supported. +cuinferStatus_t CUINFERWINAPI cuinferTransformTensor( + cuinferHandle_t handle, const void *alpha, + const cuinferTensorDescriptor_t xDesc, const void *x, const void *beta, + const cuinferTensorDescriptor_t yDesc, void *y); + +/// @brief Add two Tensor. C = alpha * A + beta * C. +/// @todo difference to ::cuinferTransformTensor? +/// @param[in] handle The libinfer handle. +/// @param[in] alpha Pointer to scaling factor in host memory. Type is always +/// float for now. +/// @param[in] aDesc The tensor descripter of A. +/// @param[in] A Const pointer to tensor data A. +/// @param[in] beta Pointer to scaling factor in host memory. Type is always +/// float for now. +/// @param[in] cDesc The tensor descripter of C. +/// @param[in,out] C Input and output tensor data C. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If bad params. +/// * ::CUINFER_STATUS_INTERNAL_ERROR If internal error happened. +/// * ::CUINFER_STATUS_NOT_SUPPORTED If algo not supported. +cuinferStatus_t CUINFERWINAPI cuinferAddTensor( + cuinferHandle_t handle, const void *alpha, + const cuinferTensorDescriptor_t aDesc, const void *A, const void *beta, + const cuinferTensorDescriptor_t cDesc, void *C); + +/// Libinfer ReduceTensor op type. +typedef enum { + CUINFER_REDUCE_TENSOR_ADD = 0, ///< Addition. + CUINFER_REDUCE_TENSOR_MUL = 1, ///< Multiplication. + CUINFER_REDUCE_TENSOR_MIN = 2, ///< Minimum. + CUINFER_REDUCE_TENSOR_MAX = 3, ///< Maximum. + CUINFER_REDUCE_TENSOR_AMAX = 4, ///< Argmax. The index of Maximum element. + CUINFER_REDUCE_TENSOR_AVG = 5, ///< Average. \f$ \frac{\sum{x}}{n} \f$ + CUINFER_REDUCE_TENSOR_NORM1 = 6, ///< Absolute-value norm. \f$ \sum{|x|} \f$ + CUINFER_REDUCE_TENSOR_NORM2 = 7, ///< Euclidean norm. \f$ \sqrt{\sum{x^2}} \f$ + CUINFER_REDUCE_TENSOR_MUL_NO_ZEROS = + 8, ///< Multiplication only to valid values. +} cuinferReduceTensorOp_t; + +/// Not used. +typedef enum { + CUINFER_REDUCE_TENSOR_NO_INDICES = 0, + CUINFER_REDUCE_TENSOR_FLATTENED_INDICES = 1, +} cuinferReduceTensorIndices_t; + +/// Not used. +typedef enum { + CUINFER_32BIT_INDICES = 0, + CUINFER_64BIT_INDICES = 1, + CUINFER_16BIT_INDICES = 2, + CUINFER_8BIT_INDICES = 3, +} cuinferIndicesType_t; + +/// @brief Create a ::cuinferReduceTensorDescriptor_t. +/// @param[out] reduceTensorDesc Pointer to ::cuinferReduceTensorDescriptor_t. +/// @return +/// * ::CUINFER_STATUS_SUCCESS if success. +/// * ::CUINFER_STATUS_ALLOC_FAILED if malloc failed. +cuinferStatus_t CUINFERWINAPI cuinferCreateReduceTensorDescriptor( + cuinferReduceTensorDescriptor_t *reduceTensorDesc); + +/// @brief Set a ::cuinferReduceTensorDescriptor_t. +/// Not used. +/// @param[out] reduceTensorDesc The target ::cuinferReduceTensorDescriptor_t. +/// @param[in] reduceTensorOp The resuce tensor Op. +/// @param[in] reduceTensorCompType The reduce tensor compute type. +/// @param[in] reduceTensorNanOpt The reduce tensor op NaN propgation setting. +/// @param[in] reduceTensorIndices Not used. +/// @param[in] reduceTensorIndicesType Not used. +/// @return +/// * ::CUINFER_STATUS_SUCCESS if success. +/// * ::CUINFER_STATUS_BAD_PARAM if \p reduceTensorDesc is null or bad param. +cuinferStatus_t CUINFERWINAPI cuinferSetReduceTensorDescriptor( + cuinferReduceTensorDescriptor_t reduceTensorDesc, + cuinferReduceTensorOp_t reduceTensorOp, + cuinferDataType_t reduceTensorCompType, + cuinferNanPropagation_t reduceTensorNanOpt, + cuinferReduceTensorIndices_t reduceTensorIndices, + cuinferIndicesType_t reduceTensorIndicesType); + +/// @todo Not used? +cuinferStatus_t CUINFERWINAPI cuinferReduceTensor( + cuinferHandle_t handle, + const cuinferReduceTensorDescriptor_t reduceTensorDesc, void *indices, + size_t indicesSizeInBytes, void *workspace, size_t workspaceSizeInBytes, + const void *alpha, const cuinferTensorDescriptor_t aDesc, const void *A, + const void *beta, const cuinferTensorDescriptor_t cDesc, void *C); + +/// @brief Convolution mode. @details They do the same computation while data +/// layout is different. +typedef enum { + /// Convolution. Take 2d for example \f$ + /// y[i,j]=\sum{x[i,j]w[\mathrm{height}-1-i,\mathrm{weight}-1-j]} \f$. + CUINFER_CONVOLUTION = 0, + /// Cross correlation. Take 2d for example \f$ y[i,j]=\sum{x[i,j]w[i,j]} \f$. + CUINFER_CROSS_CORRELATION = 1, +} cuinferConvolutionMode_t; + +/// @brief Create a ::cuinferFilterDescriptor_t. +/// @param[out] filterDesc The descriptor for the filter created. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_ALLOC_FAILED If allocation failed. +cuinferStatus_t CUINFERWINAPI +cuinferCreateFilterDescriptor(cuinferFilterDescriptor_t *filterDesc); + +/// @brief Set a 4d ::cuinferFilterDescriptor_t. +/// @param[out] filterDesc The pointer to target ::cuinferFilterDescriptor_t. +/// @param[in] dataType The data type of the filter. +/// @param[in] format The format of the filter. +/// @param[in] k Number of filters. +/// @param[in] c Number of input channels. +/// @param[in] h Filter height. +/// @param[in] w Filter weight. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If invalid param. +cuinferStatus_t CUINFERWINAPI cuinferSetFilter4dDescriptor( + cuinferFilterDescriptor_t filterDesc, cuinferDataType_t dataType, + cuinferTensorFormat_t format, int k, int c, int h, int w); + +/// @brief Get info form 4d ::cuinferFilterDescriptor_t. +/// @param[in] filterDesc The pointer to target ::cuinferFilterDescriptor_t. +/// @param[out] dataType The data type of the filter. +/// @param[out] format The format of the filter. +/// @param[out] k Number of filters. +/// @param[out] c Number of input channels. +/// @param[out] h Filter height. +/// @param[out] w Filter weight. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p filterDesc is null. +cuinferStatus_t CUINFERWINAPI cuinferGetFilter4dDescriptor( + const cuinferFilterDescriptor_t filterDesc, cuinferDataType_t *dataType, + cuinferTensorFormat_t *format, int *k, int *c, int *h, int *w); + +/// @brief Set a ::cuinferFilterDescriptor_t. +/// @see ::cuinferGetFilter4dDescriptor +/// @param[out] filterDesc The pointer to target ::cuinferFilterDescriptor_t. +/// @param[in] dataType The datatype of the filter. +/// @param[in] format The format of the filter. +/// @param[in] nbDims Number of dimensions, 4 or 5. +/// @param[in] filterDimA Starting from index 0; k, c, h, w for 4d and k, c, d, +/// h, w for 5d. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p filterDesc is null or bad params. +/// * ::CUINFER_STATUS_NOT_SUPPORTED If type is not supported. +cuinferStatus_t CUINFERWINAPI cuinferSetFilterNdDescriptor( + cuinferFilterDescriptor_t filterDesc, cuinferDataType_t dataType, + cuinferTensorFormat_t format, int nbDims, const int filterDimA[]); + +/// @brief Get info from a ::cuinferFilterDescriptor_t. +/// @see ::cuinferGetFilter4dDescriptor +/// @param[in] filterDesc The pointer to target ::cuinferFilterDescriptor_t. +/// @param[out] nbDimsRequested Not used. +/// @param[out] dataType The datatype of the filter. +/// @param[out] format The format of the filter. +/// @param[out] nbDims Number of dimensions, 4 or 5. +/// @param[out] filterDimA Starting from index 0; k, c, h, w for 4d and k, c, d, +/// h, w for 5d. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p filterDesc is null. +cuinferStatus_t CUINFERWINAPI cuinferGetFilterNdDescriptor( + const cuinferFilterDescriptor_t filterDesc, int nbDimsRequested, + cuinferDataType_t *dataType, ///< image data type + cuinferTensorFormat_t *format, int *nbDims, int filterDimA[]); + +/// @brief Return bytes used by a ::cuinferFilterDescriptor_t. +/// @param[in] filterDesc The pointer to target ::cuinferFilterDescriptor_t. +/// @param[out] size The pysical size in bytes. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p filterDesc is null. +cuinferStatus_t CUINFERWINAPI cuinferGetFilterSizeInBytes( + const cuinferFilterDescriptor_t filterDesc, size_t *size); + +/// @brief Destopy a ::cuinferFilterDescriptor_t after use. +/// @see ::cuinferCreateFilterDescriptor +/// @param[in] filterDesc The pointer to target ::cuinferFilterDescriptor_t. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +cuinferStatus_t CUINFERWINAPI +cuinferDestroyFilterDescriptor(cuinferFilterDescriptor_t filterDesc); + +/// @brief Create an instance of ::cuinferConvolutionDescriptor_t. +/// @param[out] convDesc The pointer to store ::cuinferConvolutionDescriptor_t. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_ALLOC_FAILED If allocation failed. +cuinferStatus_t CUINFERWINAPI +cuinferCreateConvolutionDescriptor(cuinferConvolutionDescriptor_t *convDesc); + +/// @brief Set the \p mathType for a ::cuinferConvolutionDescriptor_t. +/// @param[out] convDesc The target ::cuinferConvolutionDescriptor_t. +/// @param[in] mathType The target ::cuinferMathType_t. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p convDesc is null. +cuinferStatus_t CUINFERWINAPI cuinferSetConvolutionMathType( + cuinferConvolutionDescriptor_t convDesc, cuinferMathType_t mathType); + +/// @brief Get the \p mathType for a ::cuinferConvolutionDescriptor_t. +/// @param[in] convDesc The target ::cuinferConvolutionDescriptor_t. +/// @param[out] mathType The target ::cuinferMathType_t. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p convDesc is null. +cuinferStatus_t CUINFERWINAPI cuinferGetConvolutionMathType( + cuinferConvolutionDescriptor_t convDesc, cuinferMathType_t *mathType); + +/// @brief Set the \p groupCount for a ::cuinferConvolutionDescriptor_t. +/// @param[out] convDesc The target ::cuinferConvolutionDescriptor_t. +/// @param[in] groupCount The target group count. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p convDesc is null. +cuinferStatus_t CUINFERWINAPI cuinferSetConvolutionGroupCount( + cuinferConvolutionDescriptor_t convDesc, int groupCount); + +/// @brief Get the \p groupCount for a ::cuinferConvolutionDescriptor_t. +/// @param[in] convDesc The target ::cuinferConvolutionDescriptor_t. +/// @param[out] groupCount The target group count. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p convDesc is null. +cuinferStatus_t CUINFERWINAPI cuinferGetConvolutionGroupCount( + cuinferConvolutionDescriptor_t convDesc, int *groupCount); + +/// @brief Set a 2d ::cuinferConvolutionDescriptor_t. +/// @param[out] convDesc The target ::cuinferConvolutionDescriptor_t. +/// @param[in] pad_h The padding of data in height. +/// @param[in] pad_w The padding of data in weight. +/// @param[in] u The stride in filter in height. +/// @param[in] v The stride in filter in weight. +/// @param[in] dilation_h The filter dilation in height. +/// @param[in] dilation_w The filter dilation in weight. +/// @param[in] mode The convolution mode. +/// @param[in] computeType The datatype in compute. Can be different to input +/// and output datatype. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If param is not valid. +cuinferStatus_t CUINFERWINAPI cuinferSetConvolution2dDescriptor( + cuinferConvolutionDescriptor_t convDesc, int pad_h, int pad_w, int u, int v, + int dilation_h, int dilation_w, cuinferConvolutionMode_t mode, + cuinferDataType_t computeType); + +/// @brief Return the info from a 2d ::cuinferConvolutionDescriptor_t. +/// @param[in] convDesc The target ::cuinferConvolutionDescriptor_t. +/// @param[out] pad_h The padding of data in height. +/// @param[out] pad_w The padding of data in weight. +/// @param[out] u The stride in filter in height. +/// @param[out] v The stride in filter in weight. +/// @param[out] dilation_h The filter dilation in height. +/// @param[out] dilation_w The filter dilation in weight. +/// @param[out] mode The convolution mode. +/// @param[out] computeType The datatype in compute. Can be different to input +/// and output datatype. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If param is \p convDesc is null. +cuinferStatus_t CUINFERWINAPI cuinferGetConvolution2dDescriptor( + const cuinferConvolutionDescriptor_t convDesc, int *pad_h, int *pad_w, + int *u, int *v, int *dilation_h, int *dilation_w, + cuinferConvolutionMode_t *mode, cuinferDataType_t *computeType); + +/// Helper function to return the dimensions of the output tensor given a +/// convolution descriptor + +/// @brief Helper function to calculate the result dimensions given a +/// ::cuinferConvolutionDescriptor_t and input ::cuinferTensorDescriptor_t. +/// @param[in] convDesc The conv descriptor. +/// @param[in] inputTensorDesc The input tensor descriptor. +/// @param[in] filterDesc The filter descriptor. +/// @param[out] n The batch number of result tensor. +/// @param[out] c The number of channels of result tensor. +/// @param[out] h The height of result tensor. +/// @param[out] w The weight of result tensor. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If param is \p convDesc is null or invalid +/// conbination of params in \p convDesc, \p inputTensorDesc and \p filterDesc. +cuinferStatus_t CUINFERWINAPI cuinferGetConvolution2dForwardOutputDim( + const cuinferConvolutionDescriptor_t convDesc, + const cuinferTensorDescriptor_t inputTensorDesc, + const cuinferFilterDescriptor_t filterDesc, int *n, int *c, int *h, int *w); + +/// @brief Set a 2d or 3d ::cuinferConvolutionDescriptor_t. +/// @param[out] convDesc The target ::cuinferConvolutionDescriptor_t. +/// @param[in] arrayLength The input array length, 2 for 2d, 3 for 3d. +/// @param[in] padA The input padding array. Height, weight for 2d; depth, +/// height, weight for 3d. +/// @param[in] filterStrideA The filter stride array. Height, weight for 2d; +/// depth, height, weight for 3d. +/// @param[in] dilationA The filter dilation array. Height, weight for 2d; +/// depth, height, weight for 3d. +/// @param[in] mode The convolution mode. +/// @param[in] computeType The datatype in compute. Can be different to input +/// and output datatype. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If param is \p convDesc is null or invalid +/// conbination of params in \p convDesc, \p inputTensorDesc and \p filterDesc. +cuinferStatus_t CUINFERWINAPI cuinferSetConvolutionNdDescriptor( + cuinferConvolutionDescriptor_t convDesc, int arrayLength, const int padA[], + const int filterStrideA[], const int dilationA[], + cuinferConvolutionMode_t mode, cuinferDataType_t computeType); + +/// @brief Set a 2d or 3d ::cuinferConvolutionDescriptor_t. +/// @param[in] convDesc The target ::cuinferConvolutionDescriptor_t. +/// @param[in] arrayLengthRequested Not used. +/// @param[out] arrayLength The array length. 2 for 2d and 3 for 3d. +/// @param[out] padA The input padding array. Height, weight for 2d; depth, +/// height, weight for 3d. +/// @param[out] strideA The filter stride array. Height, weight for 2d; +/// depth, height, weight for 3d. +/// @param[out] dilationA The filter dilation array. Height, weight for 2d; +/// depth, height, weight for 3d. +/// @param[out] mode The convolution mode. +/// @param[out] computeType The datatype in compute. Can be different to input +/// and output datatype. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If param is \p convDesc is null or invalid +/// conbination of params in \p convDesc, \p inputTensorDesc and \p filterDesc. +cuinferStatus_t CUINFERWINAPI cuinferGetConvolutionNdDescriptor( + const cuinferConvolutionDescriptor_t convDesc, int arrayLengthRequested, + int *arrayLength, int padA[], int strideA[], int dilationA[], + cuinferConvolutionMode_t *mode, cuinferDataType_t *computeType); + +/// @brief Get the output dimensions given convolution descriptions. +/// @param[in] convDesc The convolution descriptor. +/// @param[in] inputTensorDesc The input tensor descriptor. +/// @param[in] filterDesc The filter descriptor. +/// @param[in] nbDims Number of dimensions. 2 for 2d and 3 for 3d. +/// @param[out] tensorOuputDimA The result output tensor dimensions. Height, +/// weight for 2d and depth, height, weight for 3d. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p convDesc is null or invalid conbination +/// of params in \p convDesc, \p inputTensorDesc and \p filterDesc. +cuinferStatus_t CUINFERWINAPI cuinferGetConvolutionNdForwardOutputDim( + const cuinferConvolutionDescriptor_t convDesc, + const cuinferTensorDescriptor_t inputTensorDesc, + const cuinferFilterDescriptor_t filterDesc, int nbDims, + int tensorOuputDimA[]); + +/// @brief Destroy a convolution descriptor after use. +/// @param[in] convDesc The ::cuinferConvolutionDescriptor_t to be destroyed. +/// @warning Deleting a \p convDesc twice is an undefined behavior. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +cuinferStatus_t CUINFERWINAPI +cuinferDestroyConvolutionDescriptor(cuinferConvolutionDescriptor_t convDesc); + +/** + * @brief Function to concatenate a few tensors to a output tensor. + * @details This function is made to concatenate tensors, the number of input + tensors can be two,three, or four channel in cuinferTensorDescriptor_t is + padded channel, the real channel is realc (when axis != 3, the realc is + useless). + * + * Example: Concat two tensors, x1Desc = {N, H, W, padc1}, x2Desc = {N, H, W, + padc2}, yDesc = {N, H, W, realc1 + realc2 + y_pad}. + * + * @param[in] x1Desc The information of input1. + * @param[in] x1 Input1 address. + * @param[in] x2Desc The information of input2. + * @param[in] x2 Input2 address. + * @param[in] x3Desc The information of input2. + * @param[in] x3 Input3 address. + * @param[in] x4Desc The information of input2. + * @param[in] x4 Input4 address. + * @param[in] yDesc The information of output. + * @param[out] y Output address. + * @param[in] axis Decide whether realc is useful. + * @param[in] bQuant Decide whether the result need multiply \p y_scale and \p + scale1 \p scale2 \p scale3 \p scale4. + * @return + * * ::CUINFER_STATUS_BAD_PARAM If \p x1, \p x2 is \p nullptr. + * * ::CUINFER_STATUS_NOT_SUPPORTED If not supported. + * * ::CUINFER_STATUS_SUCCESS If success. +*/ +cuinferStatus_t CUINFERWINAPI cuinferConcatenate( + cuinferHandle_t handle, const cuinferTensorDescriptor_t x1Desc, + const void *x1, const void *scale1, const int realc1, + const cuinferTensorDescriptor_t x2Desc, const void *x2, const void *scale2, + const int realc2, const cuinferTensorDescriptor_t x3Desc, const void *x3, + const void *scale3, const int realc3, + const cuinferTensorDescriptor_t x4Desc, const void *x4, const void *scale4, + const int realc4, const cuinferTensorDescriptor_t yDesc, void *y, + const void *y_scale, const int axis, bool bQuant); + +/// @brief Split input int8 tensor to 2 or 3 tensors. +/// @param[in] handle The libinfer handle. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] batch The batch. A quantity used or made at one time. +/// @param[in] height The height of the image tensor. +/// @param[in] width The width of the image tensor. +/// @param[in] sizeLen The split size, 2 or 3. +/// @param[in] sizes The size start of each parts. +/// @param[in] axis The axis to split. +/// @param[out] y The discriptor of output tensor y. +/// @return +/// * ::CUINFER_STATUS_NOT_SUPPORTED If not supported. +/// * ::CUINFER_STATUS_SUCCESS If success. +/// @todo Currently not used by other library. +cuinferStatus_t CUINFERWINAPI cuinferSplitForward( + cuinferHandle_t handle, const cuinferTensorDescriptor_t xDesc, + const void *x, const int batch, const int height, const int width, + const int sizeLen, const int *sizes, const int axis, void *y); + +/// Interpolation method used in image resize. +typedef enum { + CUINFER_INTER_NEAREST = 0, ///< Pixel is determined by it's nearest neighbor. + CUINFER_INTER_LINEAR = 1, ///< Pixel is determined by linear interpolation. + CUINFER_INTER_CUBIC = 2, ///< Pixcel is determined by cubic interpolation. + CUINFER_INTER_AREA = 3, ///< Not used. +} cuinferInterpolationFlag_t; + +/// @todo Explain this. +typedef enum { + CUINFER_HALF_PIXEL = 0, + CUINFER_ALIGN_CORNERS = 1, + CUINFER_ASYMMETRIC = 2, +} cuinferCoordinateTransformationMode_t; + +/// @brief Resize a image. +/// @note The input pointer and output space are not overlap. +/// @param[in] handle The libinfer handle. +/// @param[in] xDesc The tensor descriptor of the input. +/// @param[in] x The const pointer of input. +/// @param[in] interpolation Interpolation mode. +/// @param[in] transformMode +/// @param[in] yDesc The tensor descriptor of the output. +/// @param[out] y The pointer of output tensor y. +/// @return +/// * ::CUINFER_STATUS_NOT_SUPPORTED If algo is not supported. +/// * ::CUINFER_STATUS_SUCCESS If success. +cuinferStatus_t CUINFERWINAPI +cuinferResize2D(cuinferHandle_t handle, const cuinferTensorDescriptor_t xDesc, + const void *x, cuinferInterpolationFlag_t interpolation, + cuinferCoordinateTransformationMode_t transformMode, + const cuinferTensorDescriptor_t yDesc, void *y); + +/// Convolution forward algo selection preference. +typedef enum { + CUINFER_CONVOLUTION_FWD_NO_WORKSPACE = 0, ///< No extra workspace. + CUINFER_CONVOLUTION_FWD_PREFER_FASTEST = 1, ///< Prefer fastest. + CUINFER_CONVOLUTION_FWD_SPECIFY_WORKSPACE_LIMIT = + 2, ///< Specify workspace limit. +} cuinferConvolutionFwdPreference_t; + +/// Convolution forward algo. +typedef enum { + CUINFER_CONVOLUTION_FWD_ALGO_IMPLICIT_GEMM = 0, ///< Implicit gemm. + CUINFER_CONVOLUTION_FWD_ALGO_IMPLICIT_PRECOMP_GEMM = 1, ///< Implicit + CUINFER_CONVOLUTION_FWD_ALGO_GEMM = 2, ///< Gemm. + CUINFER_CONVOLUTION_FWD_ALGO_DIRECT = 3, ///< Direct compute use cuda call. + CUINFER_CONVOLUTION_FWD_ALGO_FFT = 4, ///< FFT. + CUINFER_CONVOLUTION_FWD_ALGO_FFT_TILING = 5, ///< FFT tiling. + CUINFER_CONVOLUTION_FWD_ALGO_WINOGRAD = 6, ///< Winograd. + CUINFER_CONVOLUTION_FWD_ALGO_WINOGRAD_NONFUSED = 7, ///< Winograd nonfused. + CUINFER_CONVOLUTION_FWD_ALGO_COUNT = 8, ///< Total algo count. +} cuinferConvolutionFwdAlgo_t; + +/// How to connect conv result and previous result. +typedef enum { + CUINFER_CONNECTION_NONE = 0, ///< No previous result is used. + CUINFER_CONNECTION_ADD = 1, ///< Add two results. + CUINFER_CONNECTION_MUL = 2, ///< Multiply two results + CUINFER_CONNECTION_CONCAT = 3, ///< Stack two results. +} cuinferTensorConnectionMode_t; + +/// Profile result of convolution forward algorithms. +typedef struct { + cuinferConvolutionFwdAlgo_t algo; ///< Algo name. + cuinferStatus_t status; ///< Return status. + float time; ///< Runtime. + size_t memory; ///< Memory needed. + cuinferDeterminism_t determinism; ///< Is algorithm deterministic. + cuinferMathType_t mathType; ///< Algo math type(use tensor op or not). + int reserved[3]; ///< Reserved. +} cuinferConvolutionFwdAlgoPerf_t; + +/// @brief Get count of convolution forward algorithms. +/// @param[in] handle The libinfer handle. +/// @param[out] count The number of convolution forward algorithms. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If \p handle is null. +cuinferStatus_t CUINFERWINAPI cuinferGetConvolutionForwardAlgorithmMaxCount( + cuinferHandle_t handle, int *count); + +/// @brief Find the best convolution forward algorithm under given conditions. +/// @details Formular is given based on the combination of params. +/// * y = activate(connect((conv(x, w) * (perchannelAlpha[i] or alpha) + +/// bias[i]), z * z_scale) * alpha2) +/// * y = connect(activate(conv(x, w) * (perchannelAlpha[i] or alpha) + +/// bias[i]), z * z_scale) * alpha2 +/// @todo For debug set enviroment variable \p DNN_DEBUG_FIND_CONV_FWD_ALGO to +/// the algo choosen. +/// @see ::cuinferQDEConvolutionForward +/// @param[in] handle The libinfer handle. +/// @param[in] alpha The scale factor used after convolution result. Single +/// float. +/// @param[in] perchannelAlpha The scale factor used after convolution result. +/// Channel times float. +/// @param[in] xDesc The info of input tensor x. +/// @param[in] wDesc The info of filter w. +/// @param[in] convDesc The info of convolution. +/// @param[in] yDesc The info of output tensor y. +/// @param[in] zDesc The info of input tensor z. +/// @param[in] biasDesc Not used. +/// @param[in] activationDesc The info of activation. +/// @param[in] connectionMode The connection mode. +/// @param[in] perChannel Whether alpha is individual for each channel. +/// @param[in] connectionBeforeActivation Whether activation is performed before +/// connection. +/// @param[in] requestedAlgoCount Requested algorithm max count. +/// @param[out] returnedAlgoCount Result algorithm count. +/// @param[out] perfResults Profile results. +/// @return +/// * ::CUINFER_STATUS_BAD_PARAM If input tensor is null or bad param. +/// * ::CUINFER_STATUS_NOT_SUPPORTED If algo is not supported. +/// * ::CUINFER_STATUS_SUCCESS If success. +cuinferStatus_t CUINFERWINAPI cuinferFindConvolutionForwardAlgorithm( + cuinferHandle_t handle, const void *alpha, const void *perchannelAlpha, + const cuinferTensorDescriptor_t xDesc, + const cuinferFilterDescriptor_t wDesc, + const cuinferConvolutionDescriptor_t convDesc, + const cuinferTensorDescriptor_t yDesc, + const cuinferTensorDescriptor_t zDesc, + const cuinferTensorDescriptor_t biasDesc, + const cuinferActivationDescriptor_t activationDesc, + const cuinferTensorConnectionMode_t connectionMode, bool perChannel, + bool connectionBeforeActivation, const int requestedAlgoCount, + int returnedAlgoCount[], cuinferConvolutionFwdAlgoPerf_t perfResults[]); + +/// @brief Find best convolution forward algorithms for \p float16. +/// @param[in] handle The libinfer handle. +/// @param[in] xDesc The descriptor of tensor x. +/// @param[in] wDesc The descriptor of filter w. +/// @param[in] convDesc The descriptor of convolution. +/// @param[in] yDesc The descriptor of tensor y. +/// @param[in] zDesc The descriptor of tensor z. +/// @param[in] biasDesc The discriptor of bias. +/// @param[in] activationDesc The discriptor of activation. +/// @param[in] connectionMode The connection mode. +/// @param[in] connectionBeforeActivation Whether activation is performed before +/// connection. +/// @param[in] requestedAlgoCount Requested algorithm max count. +/// @param[out] returnedAlgoCount Result algorithm count. +/// @param[out] perfResults Profile results. +/// @return +/// * ::CUINFER_STATUS_BAD_PARAM If input tensor is null or bad param. +/// * ::CUINFER_STATUS_SUCCESS If success. +cuinferStatus_t CUINFERWINAPI cuinferFindConvolutionForwardAlgorithmFP16( + cuinferHandle_t handle, const cuinferTensorDescriptor_t xDesc, + const cuinferFilterDescriptor_t wDesc, + const cuinferConvolutionDescriptor_t convDesc, + const cuinferTensorDescriptor_t yDesc, + const cuinferTensorDescriptor_t zDesc, + const cuinferTensorDescriptor_t biasDesc, + const cuinferActivationDescriptor_t activationDesc, + const cuinferTensorConnectionMode_t connectionMode, + bool connectionBeforeActivation, const int requestedAlgoCount, + int returnedAlgoCount[], cuinferConvolutionFwdAlgoPerf_t perfResults[]); + +/// @brief Find best convolution forward algorithm within limited workspace size +/// with actual profile. +/// @param[in] handle The libinfer handle. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] The const pointer of input filter w. +/// @param[in] convDesc The discriptor of convolution. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[in] y +/// @param[in] requestedAlgoCount Requested algorithm max count. +/// @param[out] returnedAlgoCount Result algorithm count. +/// @param[out] perfResults Profile results. +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[in] workSpaceSizeInBytes The workspace size pre-allocated. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If input tensor is null or bad param. +cuinferStatus_t CUINFERWINAPI cuinferFindConvolutionForwardAlgorithmEx( + cuinferHandle_t handle, const cuinferTensorDescriptor_t xDesc, + const void *x, const cuinferFilterDescriptor_t wDesc, const void *w, + const cuinferConvolutionDescriptor_t convDesc, + const cuinferTensorDescriptor_t yDesc, void *y, + const int requestedAlgoCount, int *returnedAlgoCount, + cuinferConvolutionFwdAlgoPerf_t *perfResults, void *workSpace, + size_t workSpaceSizeInBytes); + +/// @brief Find best convolution forward algorithm within limited workspace size +/// with no actual run. +/// @param[in] handle The libinfer handle. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] convDesc The discriptor of convolution. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[in] preference The algo preference. +/// @param[in] memoryLimitInBytes The memory limit. +/// @param[out] algo The result algorithm. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If input tensor is null or bad param. +cuinferStatus_t CUINFERWINAPI cuinferGetConvolutionForwardAlgorithm( + cuinferHandle_t handle, const cuinferTensorDescriptor_t xDesc, + const cuinferFilterDescriptor_t wDesc, + const cuinferConvolutionDescriptor_t convDesc, + const cuinferTensorDescriptor_t yDesc, + cuinferConvolutionFwdPreference_t preference, size_t memoryLimitInBytes, + cuinferConvolutionFwdAlgo_t *algo); + +/// @brief Find the best convolution forward algorithm. +/// @param[in] handle The libinfer handle. +/// @param[in] srcDesc The discriptor of input tensor. +/// @param[in] filterDesc The discriptor of filter tensor. +/// @param[in] convDesc The discriptor of convolution. +/// @param[in] destDesc The discriptor of output tensor. +/// @param[in] requestedAlgoCount Requested algorithm max count. +/// @param[out] returnedAlgoCount Result algorithm count. +/// @param[out] perfResults Profile results. +/// @return +/// * ::CUINFER_STATUS_SUCCESS If success. +/// * ::CUINFER_STATUS_BAD_PARAM If input tensor is null or bad param. +/// @todo This is not used by any other library. +cuinferStatus_t CUINFERWINAPI cuinferGetConvolutionForwardAlgorithm_v7( + cuinferHandle_t handle, const cuinferTensorDescriptor_t srcDesc, + const cuinferFilterDescriptor_t filterDesc, + const cuinferConvolutionDescriptor_t convDesc, + const cuinferTensorDescriptor_t destDesc, const int requestedAlgoCount, + int *returnedAlgoCount, cuinferConvolutionFwdAlgoPerf_t *perfResults); + +/// @brief Get extra workspace size in bytes used by convolution forward +/// algorithm. +/// @details Convolution algorithm (which requires potentially some workspace). +/// Helper function to return the minimum size of the workspace to be passed to +/// the convolution given an algo. +/// @param[in] handle The libinfer handle. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] convDesc The discriptor of convolution. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[in] algo The algorithm specified. +/// @param[out] sizeInBytes The result extra temporary space size in bytes. +/// @return +/// * ::CUINFER_STATUS_BAD_PARAM If input tensor is null or bad param. +/// * ::CUINFER_STATUS_NOT_SUPPORTED If algo not supported. +/// * ::CUINFER_STATUS_SUCCESS If success. +cuinferStatus_t CUINFERWINAPI cuinferGetConvolutionForwardWorkspaceSize( + cuinferHandle_t handle, const cuinferTensorDescriptor_t xDesc, + const cuinferFilterDescriptor_t wDesc, + const cuinferConvolutionDescriptor_t convDesc, + const cuinferTensorDescriptor_t yDesc, cuinferConvolutionFwdAlgo_t algo, + size_t *sizeInBytes); + +// clang-format off +/// @defgroup ConvolutionFunctions Convollution Functions +/// @details +/// Common result for all convolution functions for quantifier. +/// \code +/// if cuinferTensorConnectionMode_t == CUINFER_CONNECTION_NONE: +/// if bias == nullptr: +/// if perChannel == false: +/// y = clip(round(activate((convtransposed(x, w) * alpha)))) +/// if perChannel == ture: +/// y = clip(round(activate((convtransposed(x, w) * perchannelAlpha[i])))) +/// if bias != nullptr: +/// if perChannel == false: +/// y = clip(round(activate((convtransposed(x, w) * alpha) + bias[0]))) +/// if perChannel == ture: +/// y = clip(round(activate((convtransposed(x, w) * perchannelAlpha[i]) + bias[i]))) +/// elif cuinferTensorConnectionMode_t == CUINFER_CONNECTION_ADD: +/// if bias == nullptr: +/// if perChannel == false: +/// if befor_activation_ == false: +/// y = clip(round((activate(convtransposed(x, w) * alpha) + z * z_scale) * alpha2)) +/// else: +/// y = clip(round(activate(((convtransposed(x, w) * alpha) + z * z_scale) * alpha2))) +/// if perChannel == ture: +/// if connectionDesc.befor_activation_ == 0: +/// y = clip(round((activate(convtransposed(x, w) * perchannelAlpha[i]) + z * z_scale) * alpha2)) +/// else: +/// y = clip(round(activate(((convtransposed(x, w) * perchannelAlpha[i]) + z * z_scale) * alpha2))) +/// if bias != nullptr: +/// if perChannel == false: +/// if befor_activation_ == false: +/// y = clip(round((activate(convtransposed(x, w) * alpha + bias[i]) + z * z_scale) * alpha2)) +/// else: +/// y = clip(round(activate(((convtransposed(x, w) * alpha + bias[i]) + z * z_scale) * alpha2))) +/// if perChannel == ture: +/// if befor_activation_ == false: +/// y = clip(round((activate(convtransposed(x, w) * perchannelAlpha[i] + bias[i]) + z * z_scale) * alpha2)) +/// else: +/// y = clip(round(activate(((convtransposed(x, w) * perchannelAlpha[i] + bias[i]) + z * z_scale) * alpha2))) +/// elif cuinferTensorConnectionMode_t == CUINFER_CONNECTION_CONCAT: +/// if bias == nullptr: +/// if perChannel == false: +/// if befor_activation_ == false: +/// y = clip(round((concat(activate(convtransposed(x, w) * alpha), z * z_scale)) * alpha2)) +/// else: +/// y = clip(round(activate(concat(convtransposed(x, w) * alpha, z * z_scale)) * alpha2)) +/// if perChannel == ture: +/// if befor_activation_ == false: +/// y = clip(round((concat(activate(convtransposed(x, w) * perchannelAlpha[i]), z * z_scale)) * alpha2)) +/// else: +/// y = clip(round(activate(concat(convtransposed(x, w) * perchannelAlpha[i], z * z_scale) * alpha2))) +/// if bias != nullptr: +/// if perChannel == false: +/// if befor_activation_ == false: +/// y = clip(round(concat(activate(convtransposed(x, w) * alpha + bias[i]), z * z_scale) * alpha2)) +/// else: +/// y = clip(round(activate(concat(convtransposed(x, w) * alpha + bias[i], z * z_scale)) * alpha2)) +/// if perChannel == ture: +/// if befor_activation_ == false: +/// y = clip(round(concat(activate(convtransposed(x, w) * perchannelAlpha[i] + bias[i]), z * z_scale) * alpha2)) +/// else: +/// y = clip(round(activate(concat((convtransposed(x, w) * perchannelAlpha[i] + bias[i]), z * z_scale) * alpha2))) +/// \endcode +// clang-format on + +/// @brief Function to perform the forward pass for batch convolution. +/// @details Formula, y = alpha[0] * conv(x, w) + beta[0] * y. +/// @note Only int8(only relu) and true half configs are supported. +/// @ingroup ConvolutionFunctions +/// @param[in] handle The libinfer handle. +/// @param[in] alpha The pointer to scaling factor. +/// @param[in] xDesc The descriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] The const pointer of input filter w. +/// @param[in] convDesc The discriptor of convolution. +/// @param[in] algo The algorithm specified. +/// @param[in] workSpace The workspace pre-allocated. See the corresponding +/// get workspace size helper function. +/// @param[in] workSpaceSizeInBytes The workspace size in bytes. +/// @param[in] beta Pointer to scaling factor. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[in, out] y The discriptor of output tensor y. +/// @return +/// * ::CUINFER_STATUS_BAD_PARAM If input tensor is null or bad param. +/// * ::CUINFER_STATUS_NOT_SUPPORTED If algo not supported. +/// * ::CUINFER_STATUS_SUCCESS If success. +cuinferStatus_t CUINFERWINAPI +cuinferConvolutionForward(cuinferHandle_t handle, const void *alpha, + const cuinferTensorDescriptor_t xDesc, const void *x, + const cuinferFilterDescriptor_t wDesc, const void *w, + const cuinferConvolutionDescriptor_t convDesc, + cuinferConvolutionFwdAlgo_t algo, void *workSpace, + size_t workSpaceSizeInBytes, const void *beta, + const cuinferTensorDescriptor_t yDesc, void *y); + +/// @brief Convolution forward with quantifier. +/// @details For what params means like \p alpha, \p alpha2, and \p bias, see +/// \ref ConvolutionFunctions. +/// @ingroup ConvolutionFunctions +/// @param[in] handle The libinfer handle. +/// @param[in] alpha Pointer to scaling factor. +/// @param[in] beta Pointer to scaling factor. +/// @param[in] gamma Pointer to scaling factor. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] The const pointer of input filter w. +/// @param[in] convDesc The discriptor of convolution. +/// @param[in] algo The algorithm specified. +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[in] workSpaceSizeInBytes The workspace size in bytes. +/// @param[in] alpha2 The pointer to scaling factor +/// @param[in] zDesc +/// @param[in] z +/// @param[in] biasDesc +/// @param[in] bias +/// @param[in] activationDesc +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferQConvolutionForward( + cuinferHandle_t handle, const void *alpha, const void *beta, + const void *gamma, const cuinferTensorDescriptor_t xDesc, const void *x, + const cuinferFilterDescriptor_t wDesc, const void *w, + const cuinferConvolutionDescriptor_t convDesc, + cuinferConvolutionFwdAlgo_t algo, void *workSpace, + size_t workSpaceSizeInBytes, const void *alpha2, + const cuinferTensorDescriptor_t zDesc, const void *z, + const cuinferTensorDescriptor_t biasDesc, const void *bias, + const cuinferActivationDescriptor_t activationDesc, + const cuinferTensorDescriptor_t yDesc, void *y); + +/// @brief +/// @ingroup ConvolutionFunctions +/// @param[in] handle The libinfer handle. +/// @param[in] alpha Pointer to scaling factor. +/// @param[in] perchannelAlpha +/// @param[in] beta Pointer to scaling factor. +/// @param[in] gamma Pointer to scaling factor. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] The const pointer of input filter w. +/// @param[in] convDesc The discriptor of convolution. +/// @param[in] algo The algorithm specified. +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[in] workSpaceSizeInBytes +/// @param[in] alpha2 +/// @param[in] zDesc +/// @param[in] z +/// @param[in] biasDesc +/// @param[in] bias +/// @param[in] quadDesc +/// @param[in] perChannel +/// @param[in] activationDesc +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferQDConvolutionForward( + cuinferHandle_t handle, const void *alpha, const void *perchannelAlpha, + const void *beta, const void *gamma, const cuinferTensorDescriptor_t xDesc, + const void *x, const cuinferFilterDescriptor_t wDesc, const void *w, + const cuinferConvolutionDescriptor_t convDesc, + cuinferConvolutionFwdAlgo_t algo, void *workSpace, + size_t workSpaceSizeInBytes, const void *alpha2, + const cuinferTensorDescriptor_t zDesc, const void *z, + const cuinferTensorDescriptor_t biasDesc, const void *bias, + const cuinferTensorDescriptor_t quadDesc, bool perChannel, + const cuinferActivationDescriptor_t activationDesc, + const cuinferTensorDescriptor_t yDesc, void *y); + +/// @brief +/// @ingroup ConvolutionFunctions +/// @see Common format in group \ref ConvolutionFunctions. +/// @param[in] handle The libinfer handle. +/// @param[in] alpha Pointer to scaling factor. +/// @param[in] perchannelAlpha +/// @param[in] beta Pointer to scaling factor. +/// @param[in] gamma Pointer to scaling factor. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] The const pointer of input filter w. +/// @param[in] convDesc The discriptor of convolution. +/// @param[in] algo The algorithm specified. +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[in] workSpaceSizeInBytes +/// @param[in] alpha2 +/// @param[in] zScale +/// @param[in] zDesc +/// @param[in] z +/// @param[in] biasDesc +/// @param[in] bias +/// @param[in] perChannel +/// @param[in] activationDesc +/// @param[in] connectionBeforeActivation Whether activation is performed before +/// connection. +/// @param[in] connectionMode The connection mode. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferQDEConvolutionForward( + cuinferHandle_t handle, const void *alpha, const void *perchannelAlpha, + const void *beta, const void *gamma, const cuinferTensorDescriptor_t xDesc, + const void *x, const cuinferFilterDescriptor_t wDesc, const void *w, + const cuinferConvolutionDescriptor_t convDesc, + cuinferConvolutionFwdAlgo_t algo, void *workSpace, + size_t workSpaceSizeInBytes, const void *alpha2, const void *zScale, + const cuinferTensorDescriptor_t zDesc, const void *z, + const cuinferTensorDescriptor_t biasDesc, const void *bias, bool perChannel, + const cuinferActivationDescriptor_t activationDesc, + bool connectionBeforeActivation, + const cuinferTensorConnectionMode_t connectionMode, + const cuinferTensorDescriptor_t yDesc, void *y); + +/// @brief +/// @ingroup ConvolutionFunctions +/// @param[in] handle The libinfer handle. +/// @param[in] alpha Pointer to scaling factor. +/// @param[in] beta Pointer to scaling factor. +/// @param[in] gamma Pointer to scaling factor. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] The const pointer of input filter w. +/// @param[in] convDesc The discriptor of convolution. +/// @param[in] algo The algorithm specified. +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[in] workSpaceSizeInBytes +/// @param[in] alpha2 +/// @param[in] zDesc +/// @param[in] z +/// @param[in] biasDesc +/// @param[in] bias +/// @param[in] activationDesc +/// @param[in] connectionBeforeActivation Whether activation is performed before +/// connection. +/// @param[in] connectionMode The connection mode. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferHalfConvolution2dForward( + cuinferHandle_t handle, const void *alpha, const void *beta, + const void *gamma, const cuinferTensorDescriptor_t xDesc, const void *x, + const cuinferFilterDescriptor_t wDesc, const void *w, + const cuinferConvolutionDescriptor_t convDesc, + cuinferConvolutionFwdAlgo_t algo, void *workSpace, + size_t workSpaceSizeInBytes, const void *alpha2, + const cuinferTensorDescriptor_t zDesc, const void *z, + const cuinferTensorDescriptor_t biasDesc, const void *bias, + const cuinferActivationDescriptor_t activationDesc, + bool connectionBeforeActivation, + const cuinferTensorConnectionMode_t connectionMode, + const cuinferTensorDescriptor_t yDesc, void *y); + +typedef enum { + CUINFER_CONVOLUTION_BWD_FILTER_ALGO_0 = 0, ///< Non-deterministic. + CUINFER_CONVOLUTION_BWD_FILTER_ALGO_1 = 1, + CUINFER_CONVOLUTION_BWD_FILTER_ALGO_FFT = 2, + CUINFER_CONVOLUTION_BWD_FILTER_ALGO_3 = 3, ///< Non-deterministic. + CUINFER_CONVOLUTION_BWD_FILTER_ALGO_WINOGRAD = 4, ///< Not implemented. + CUINFER_CONVOLUTION_BWD_FILTER_ALGO_WINOGRAD_NONFUSED = 5, + CUINFER_CONVOLUTION_BWD_FILTER_ALGO_FFT_TILING = 6, + CUINFER_CONVOLUTION_BWD_FILTER_ALGO_COUNT = 7 +} cuinferConvolutionBwdFilterAlgo_t; + +typedef struct { + cuinferConvolutionBwdFilterAlgo_t algo; + cuinferStatus_t status; + float time; + size_t memory; + cuinferDeterminism_t determinism; + cuinferMathType_t mathType; + int reserved[3]; +} cuinferConvolutionBwdFilterAlgoPerf_t; + +typedef enum { + CUINFER_CONVOLUTION_BWD_DATA_ALGO_0 = 0, ///< Non-deterministic. + CUINFER_CONVOLUTION_BWD_DATA_ALGO_1 = 1, + CUINFER_CONVOLUTION_BWD_DATA_ALGO_FFT = 2, + CUINFER_CONVOLUTION_BWD_DATA_ALGO_FFT_TILING = 3, + CUINFER_CONVOLUTION_BWD_DATA_ALGO_WINOGRAD = 4, + CUINFER_CONVOLUTION_BWD_DATA_ALGO_WINOGRAD_NONFUSED = 5, + CUINFER_CONVOLUTION_BWD_DATA_ALGO_COUNT = 6 +} cuinferConvolutionBwdDataAlgo_t; + +typedef struct { + cuinferConvolutionBwdDataAlgo_t algo; + cuinferStatus_t status; + float time; + size_t memory; + cuinferDeterminism_t determinism; + cuinferMathType_t mathType; + int reserved[3]; +} cuinferConvolutionBwdDataAlgoPerf_t; + +/// @brief +/// @param[in] handle The libinfer handle. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] convDesc The discriptor of convolution. +/// @param[out] colBuffer +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferIm2Col(cuinferHandle_t handle, const cuinferTensorDescriptor_t xDesc, + const void *x, const cuinferFilterDescriptor_t wDesc, + const cuinferConvolutionDescriptor_t convDesc, void *colBuffer); + +/// Softmax algorithm. +typedef enum { + /// Straightforward implementation. May overflow. This is useful when + /// input is guaranteed in range. + CUINFER_SOFTMAX_FAST = 0, + /// Subtract max from every point to avoid overflow. + CUINFER_SOFTMAX_ACCURATE = 1, + /// Add log to result. This will use algorithm accurate. + CUINFER_SOFTMAX_LOG = 2, +} cuinferSoftmaxAlgorithm_t; + +typedef enum { + /// Compute the softmax over all C, H, W for each N. + CUINFER_SOFTMAX_MODE_INSTANCE = 0, + /// Compute the softmax over all C for each H, W, N. + CUINFER_SOFTMAX_MODE_CHANNEL = 1, + /// Compute the softmax over all W for each N, C, H. + CUINFER_SOFTMAX_MODE_WIDTH = 2 +} cuinferSoftmaxMode_t; + +/// @defgroup SortmaxFunctions Softmax Funtions +/// @note Softmax functions: All of the form "output = alpha * Op(inputs) + beta +/// * output". + +/// @brief Function to perform forward softmax. +/// @ingroup SortmaxFunctions +/// @param[in] handle The libinfer handle. +/// @param[in] algo The algorithm specified. +/// @param[in] mode +/// @param[in] alpha Pointer to scaling factor. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] beta Pointer to scaling factor. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferSoftmaxForward( + cuinferHandle_t handle, cuinferSoftmaxAlgorithm_t algo, + cuinferSoftmaxMode_t mode, const void *alpha, + const cuinferTensorDescriptor_t xDesc, const void *x, const void *beta, + const cuinferTensorDescriptor_t yDesc, void *y); + +/// @brief Function to perform forward dequant, softmax and quant. +/// @ingroup SoftmaxFunctions +/// @param[in] handle The libinfer handle. +/// @param[in] algo The algorithm specified. +/// @param[in] mode +/// @param[in] quant_scale +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] zero_point +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferDeQuantSoftmaxForwardQuant( + cuinferHandle_t handle, cuinferSoftmaxAlgorithm_t algo, + cuinferSoftmaxMode_t mode, const void *quant_scale, ///< 2 value! + const cuinferTensorDescriptor_t xDesc, const void *x, + const void *zero_point, const cuinferTensorDescriptor_t yDesc, void *y); + +/// Pooling mode. +typedef enum { + CUINFER_POOLING_MAX = 0, + CUINFER_POOLING_AVERAGE_COUNT_INCLUDE_PADDING = + 1, ///< Count for average includes padded values. + CUINFER_POOLING_AVERAGE_COUNT_EXCLUDE_PADDING = + 2, ///< Count for average does not include padded values. + CUINFER_POOLING_MAX_DETERMINISTIC = 3 +} cuinferPoolingMode_t; + +/// @brief Create an instance of pooling descriptor. +/// @param[out] poolingDesc +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferCreatePoolingDescriptor(cuinferPoolingDescriptor_t *poolingDesc); + +/// @brief +/// @param[out] poolingDesc +/// @param[in] mode +/// @param[in] maxpoolingNanOpt +/// @param[in] windowHeight +/// @param[in] windowWidth +/// @param[in] verticalPadding +/// @param[in] horizontalPadding +/// @param[in] verticalStride +/// @param[in] horizontalStride +/// @return +cuinferStatus_t CUINFERWINAPI cuinferSetPooling2dDescriptor( + cuinferPoolingDescriptor_t poolingDesc, cuinferPoolingMode_t mode, + cuinferNanPropagation_t maxpoolingNanOpt, int windowHeight, int windowWidth, + int verticalPadding, int horizontalPadding, int verticalStride, + int horizontalStride); + +/// @brief +/// @param[in] poolingDesc +/// @param[out] mode +/// @param[out] maxpoolingNanOpt +/// @param[out] windowHeight +/// @param[out] windowWidth +/// @param[out] verticalPadding +/// @param[out] horizontalPadding +/// @param[out] verticalStride +/// @param[out] horizontalStride +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetPooling2dDescriptor( + const cuinferPoolingDescriptor_t poolingDesc, cuinferPoolingMode_t *mode, + cuinferNanPropagation_t *maxpoolingNanOpt, int *windowHeight, + int *windowWidth, int *verticalPadding, int *horizontalPadding, + int *verticalStride, int *horizontalStride); + +/// @brief +/// @param[out] poolingDesc +/// @param[in] mode +/// @param[in] maxpoolingNanOpt +/// @param[in] nbDims +/// @param[in] windowDimA +/// @param[in] paddingA +/// @param[in] strideA +/// @return +cuinferStatus_t CUINFERWINAPI cuinferSetPoolingNdDescriptor( + cuinferPoolingDescriptor_t poolingDesc, const cuinferPoolingMode_t mode, + const cuinferNanPropagation_t maxpoolingNanOpt, int nbDims, + const int windowDimA[], const int paddingA[], const int strideA[]); + +/// @brief +/// @param[in] poolingDesc +/// @param[in] nbDimsRequested +/// @param[out] mode +/// @param[out] maxpoolingNanOpt +/// @param[out] nbDims +/// @param[out] windowDimA +/// @param[out] paddingA +/// @param[out] strideA +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetPoolingNdDescriptor( + const cuinferPoolingDescriptor_t poolingDesc, int nbDimsRequested, + cuinferPoolingMode_t *mode, cuinferNanPropagation_t *maxpoolingNanOpt, + int *nbDims, int windowDimA[], int paddingA[], int strideA[]); + +/// @brief +/// @param[in] poolingDesc +/// @param[out] inputTensorDesc +/// @param[in] nbDims +/// @param[out] outputTensorDimA +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetPoolingNdForwardOutputDim( + const cuinferPoolingDescriptor_t poolingDesc, + const cuinferTensorDescriptor_t inputTensorDesc, int nbDims, + int outputTensorDimA[]); + +/// @brief +/// @param[in] poolingDesc +/// @param[in] inputTensorDesc +/// @param[out] n +/// @param[out] c +/// @param[out] h +/// @param[out] w +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetPooling2dForwardOutputDim( + const cuinferPoolingDescriptor_t poolingDesc, + const cuinferTensorDescriptor_t inputTensorDesc, int *n, int *c, int *h, + int *w); + +/// @brief Destroy an instance of pooling descriptor. +/// @param[in] poolingDesc +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferDestroyPoolingDescriptor(cuinferPoolingDescriptor_t poolingDesc); + +/// @defgroup PoolingFunctions Pooling Functions +/// @note Pooling functions: All of the form "output = alpha * Op(inputs) + beta +/// * output" + +/// @brief Function to perform forward pooling. +/// @ingroup PoolingFunctions +/// @param[in] handle The libinfer handle. +/// @param[in] poolingDesc +/// @param[in] alpha Pointer to scaling factor. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] beta Pointer to scaling factor. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferPoolingForward( + cuinferHandle_t handle, const cuinferPoolingDescriptor_t poolingDesc, + const void *alpha, const cuinferTensorDescriptor_t xDesc, const void *x, + const void *beta, const cuinferTensorDescriptor_t yDesc, void *y); + +/// Activation Mode. @note Some activation function use extra parameters like a, +/// which can be set by ::cuinferSetActivationDescriptor. +typedef enum { + CUINFER_ACTIVATION_SIGMOID = 0, ///< f(x) = 1(1+e^-x). + CUINFER_ACTIVATION_RELU = 1, ///< f(x) = max(x, 0). + CUINFER_ACTIVATION_TANH = 2, ///< f(x) = tanh(x) = 2sigmod(2x)-1. + CUINFER_ACTIVATION_CLIPPED_RELU = 3, ///< f(x) = max(min(x,ceiling),0). + CUINFER_ACTIVATION_ELU = 4, ///< f(x) = x if x > 0 else a(e^x-1). + CUINFER_ACTIVATION_IDENTITY = 5, ///< f(x) = x. + CUINFER_ACTIVATION_LEAKY_RELU = 6, ///< f(x) = max(x, ax). a = -0.01 i.e. + CUINFER_ACTIVATION_SILU = 7, ///< f(x) = x/(1 + e^-x). + CUINFER_ACTIVATION_HARD_SWISH = 8, ///< x*max(0,min(6,x+3))/6. + CUINFER_ACTIVATION_HARD_SIGMOID = 9, ///< f(x) = max(0,min(1,(x+1)/2)). + CUINFER_ACTIVATION_MISH = 10, ///< f(x) = x*tanh(x)*log(1+e^x). +} cuinferActivationMode_t; + +/// @defgroup ActivationFunctions Activation Functions +/// @note Activation functions: All of the form "output = alpha * Op(inputs) + +/// beta * output" + +/// @brief +/// @ingroup ActivationFunctions +/// @param[out] activationDesc +/// @return +cuinferStatus_t CUINFERWINAPI cuinferCreateActivationDescriptor( + cuinferActivationDescriptor_t *activationDesc); + +/// @brief +/// @ingroup ActivationFunctions +/// @param[out] activationDesc +/// @param[in] mode +/// @param[in] reluNanOpt +/// @param[in] coef Ceiling for clipped RELU, alpha for ELU. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferSetActivationDescriptor( + cuinferActivationDescriptor_t activationDesc, cuinferActivationMode_t mode, + cuinferNanPropagation_t reluNanOpt, double coef); + +/// @brief +/// @ingroup ActivationFunctions +/// @param[in] activationDesc +/// @param[out] mode +/// @param[out] reluNanOpt +/// @param[out] coef Ceiling for clipped RELU, alpha for ELU. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetActivationDescriptor( + const cuinferActivationDescriptor_t activationDesc, + cuinferActivationMode_t *mode, cuinferNanPropagation_t *reluNanOpt, + double *coef); + +/// @brief +/// @ingroup ActivationFunctions +/// @param[in] activationDesc +/// @return +cuinferStatus_t CUINFERWINAPI cuinferDestroyActivationDescriptor( + cuinferActivationDescriptor_t activationDesc); + +/// @brief Function to perform forward activation. +/// @ingroup ActivationFunctions +/// @param[in] handle The libinfer handle. +/// @param[in] activationDesc +/// @param[in] alpha Pointer to scaling factor. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] beta Pointer to scaling factor. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferActivationForward( + cuinferHandle_t handle, cuinferActivationDescriptor_t activationDesc, + const void *alpha, const cuinferTensorDescriptor_t xDesc, const void *x, + const void *beta, const cuinferTensorDescriptor_t yDesc, void *y); + +/// @defgroup LRNFunctions LRN Functions +/// @note LRN functions: output = alpha * normalize(x) + beta * old_y + +/// @brief Create an instance of LRN (Local Response Normalization) descriptor. +/// @details Uses lrnN=5, lrnAlpha=1e-4, lrnBeta=0.75, lrnK=2.0 as defaults +/// from Krizhevsky'12 ImageNet paper. +/// @ingroup LRNFunctions +/// @param[out] normDesc +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferCreateLRNDescriptor(cuinferLRNDescriptor_t *normDesc); + +/// @ingroup LRNFunctions +#define CUINFER_LRN_MIN_N 1 ///< minimum allowed lrnN +/// @ingroup LRNFunctions +#define CUINFER_LRN_MAX_N 16 ///< maximum allowed lrnN +/// @ingroup LRNFunctions +#define CUINFER_LRN_MIN_K 1e-5 ///< minimum allowed lrnK +/// @ingroup LRNFunctions +#define CUINFER_LRN_MIN_BETA 0.01 ///< minimum allowed lrnBeta + +/// LRN layer mode +/// @ingroup LRNFunctions +typedef enum { + CUINFER_LRN_CROSS_CHANNEL_DIM1 = + 0, ///< Normalize across tensor's dimA[1] dimension +} cuinferLRNMode_t; + +/// @brief +/// @details Uses a window [center-lookBehind, center+lookAhead], where +/// lookBehind = floor( (lrnN-1)/2 ), lookAhead = lrnN-lookBehind-1. +/// Values of double parameters cast to tensor data type. +/// @ingroup LRNFunctions +/// @param[out] normDesc +/// @param[in] lrnN +/// @param[in] lrnAlpha +/// @param[in] lrnBeta +/// @param[in] lrnK +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferSetLRNDescriptor(cuinferLRNDescriptor_t normDesc, unsigned lrnN, + double lrnAlpha, double lrnBeta, double lrnK); + +/// @brief Retrieve the settings currently stored in an LRN layer descriptor. +/// @details Any of the provided pointers can be NULL (no corresponding value +/// will be returned). +/// @ingroup LRNFunctions +/// @param[in] normDesc +/// @param[out] lrnN +/// @param[out] lrnAlpha +/// @param[out] lrnBeta +/// @param[out] lrnK +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferGetLRNDescriptor(cuinferLRNDescriptor_t normDesc, unsigned *lrnN, + double *lrnAlpha, double *lrnBeta, double *lrnK); + +/// @brief Destroy an instance of LRN descriptor. +/// @ingroup LRNFunctions +/// @param[in] lrnDesc +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferDestroyLRNDescriptor(cuinferLRNDescriptor_t lrnDesc); + +/// @brief LRN cross-channel forward computation. +/// @details Double parameters cast to tensor data type. +/// @ingroup LRNFunctions +/// @param[in] handle The libinfer handle. +/// @param[in] normDesc +/// @param[in] lrnMode +/// @param[in] alpha Pointer to scaling factor. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] beta Pointer to scaling factor. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferLRNCrossChannelForward( + cuinferHandle_t handle, cuinferLRNDescriptor_t normDesc, + cuinferLRNMode_t lrnMode, const void *alpha, + const cuinferTensorDescriptor_t xDesc, const void *x, const void *beta, + const cuinferTensorDescriptor_t yDesc, void *y); + +typedef enum { + /// \p bnScale, \p bnBias tensor dims are 1xCxHxWx.. (one value per + /// CHW...-slice, normalized over N slice). + CUINFER_BATCHNORM_PER_ACTIVATION = 0, + /// \p bnScale, \p bnBias tensor dims are 1xCx1x1 (one value per C-dim + /// normalized over Nx1xHxW subtensors). + CUINFER_BATCHNORM_SPATIAL = 1, + /// \p bnScale, \p bnBias tensor dims are 1xCx1x1 (one value per C-dim + /// normalized over Nx1xHxW subtensors). May be faster than + /// ::CUINFER_BATCHNORM_SPATIAL but imposes some limits on the range of + /// values. + CUINFER_BATCHNORM_SPATIAL_PERSISTENT = 2, +} cuinferBatchNormMode_t; + +/// Minimum epsilon allowed to be used in the Batch Normalization formula. +#define CUINFER_BN_MIN_EPSILON 0.0 + +/// @brief +/// @details Derives a tensor descriptor from layer data descriptor for +/// BatchNormalization \p scale, \p invVariance, \p bnBias, and \p bnScale +/// tensors. Use this tensor desc for \p bnScaleBiasMeanVarDesc and \p +/// bnScaleBiasDiffDesc in Batch Normalization forward and backward functions. +/// @param[out] derivedBnDesc +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] mode +/// @return +cuinferStatus_t CUINFERWINAPI cuinferDeriveBNTensorDescriptor( + cuinferTensorDescriptor_t derivedBnDesc, + const cuinferTensorDescriptor_t xDesc, cuinferBatchNormMode_t mode); + +typedef enum { + CUINFER_BATCHNORM_OPS_BN = 0, ///< Do batch normalization only. + CUINFER_BATCHNORM_OPS_BN_ACTIVATION = 1, ///< Do batchNorm, then activation. + CUINFER_BATCHNORM_OPS_BN_ADD_ACTIVATION = 2, + ///< Do batchNorm, then elemWiseAdd, then activation. +} cuinferBatchNormOps_t; + +/// @brief +/// @param[in] handle The libinfer handle. +/// @param[in] mode +/// @param[in] bnOps +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] zDesc +/// @param[in] yDesc The discriptor of tensor y. +/// @param[in] bnScaleBiasMeanVarDesc +/// @param[in] activationDesc +/// @param[out] sizeInBytes The result extra temporary space size in bytes. +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferGetBatchNormalizationForwardTrainingExWorkspaceSize( + cuinferHandle_t handle, cuinferBatchNormMode_t mode, + cuinferBatchNormOps_t bnOps, const cuinferTensorDescriptor_t xDesc, + const cuinferTensorDescriptor_t zDesc, + const cuinferTensorDescriptor_t yDesc, + const cuinferTensorDescriptor_t bnScaleBiasMeanVarDesc, + const cuinferActivationDescriptor_t activationDesc, size_t *sizeInBytes); + +/// @brief +/// @param[in] handle The libinfer handle. +/// @param[in] mode +/// @param[in] bnOps +/// @param[in] activationDesc +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[out] sizeInBytes The result extra temporary space size in bytes. +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferGetBatchNormalizationTrainingExReserveSpaceSize( + cuinferHandle_t handle, cuinferBatchNormMode_t mode, + cuinferBatchNormOps_t bnOps, + const cuinferActivationDescriptor_t activationDesc, + const cuinferTensorDescriptor_t xDesc, size_t *sizeInBytes); + +/// @brief +/// @details Computes y = BN(x). Also accumulates moving averages of mean and +/// inverse variances. +/// +/// 'Gamma'(\p bnScale) and 'Beta'(\p bnBias) respectively in Ioffe and +/// Szegedy's paper's notation. +/// +/// MUST use factor=1 in the very first call of a complete training cycle. +/// Use a factor=1/(1+n) at N-th call to the function to get Cumulative Moving +/// Average (CMA) behavior \f( \mathrm{CMA|[n] = (x[1]+...+x[n])/n \f) Since +/// \f{eqnarray*}{ +/// \mathrm{CMA}[n+1] &=& (n*\mathrm{CMA}[n]+x[n+1])/(n+1) \\\\ +/// &=& ((n+1)*\mathrm{CMA}[n]-\mathrm{CMA}[n])/(n+1) + x[n+1]/(n+1) \\\\ +/// &=& \mathrm{CMA}[n]*(1-1/(n+1)) + x[n+1]*1/(n+1) +/// \f}. +/// +/// Shared desc for the next 6 tensors in the argument list. \p bnScale, \p +/// bnBias, \p resultRunningMean, \p resultRunningVariance, \p resultSaveMean +/// and \p resultSaveInvVariance. +/// * Data type to be set as follows: type = (typeOf(x) == double) +/// ? double : float Dimensions for this descriptor depend on normalization mode +/// * Spatial Normalization : tensors are expected to have dims +/// 1xCx1x1 (normalization is performed across NxHxW) +/// * Per-Activation Normalization : tensors are expected to have dims of +/// 1xCxHxW (normalization is performed across N) +/// @param[in] handle The libinfer handle. +/// @param[in] mode +/// @param[in] alpha alpha[0] = result blend factor. +/// @param[in] beta beta[0] = dest layer blend factor +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x NxCxHxW +/// @param[in] yDesc The discriptor of tensor y. +/// @param[in] y NxCxHxW +/// @param[in] bnScaleBiasMeanVarDesc +/// @param[in] bnScale +/// @param[in] bnBias +/// @param[in] exponentialAverageFactor +/// @param[out] resultRunningMean Used in Training phase only. runningMean = +/// newMean*factor + runningMean*(1-factor). +/// @param[out] resultRunningVariance Output in training mode, input in +/// inference. Is the moving average of variance[x] (factor is applied in the +/// same way as for runningMean). +/// @param[in] epsilon Has to be >= CUINFER_BN_MIN_EPSILON. Should be the same +/// in forward and backward functions. +/// @param[out] resultSaveMean Optionally save intermediate results from the +/// forward pass here - can be reused to speed up backward pass. NULL if unused +/// @param[out] resultSaveInvVariance +/// @return +cuinferStatus_t CUINFERWINAPI cuinferBatchNormalizationForwardTraining( + cuinferHandle_t handle, cuinferBatchNormMode_t mode, const void *alpha, + const void *beta, const cuinferTensorDescriptor_t xDesc, const void *x, + const cuinferTensorDescriptor_t yDesc, void *y, + const cuinferTensorDescriptor_t bnScaleBiasMeanVarDesc, const void *bnScale, + const void *bnBias, double exponentialAverageFactor, + void *resultRunningMean, void *resultRunningVariance, double epsilon, + void *resultSaveMean, void *resultSaveInvVariance); + +/// Computes y = relu(BN(x) + z). Also accumulates moving averages of mean and +/// inverse variances + +/// @brief +/// @param[in] handle The libinfer handle. +/// @param[in] mode +/// @param[in] bnOps +/// @param[in] alpha alpha[0] = result blend factor. +/// @param[in] beta beta[0] = dest layer blend factor +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] xData +/// @param[in] zDesc +/// @param[in] zData +/// @param[in] yDesc The discriptor of tensor y. +/// @param[in] yData +/// @param[in] bnScaleBiasMeanVarDesc +/// @param[in] bnScale +/// @param[in] bnBias +/// @param[in] exponentialAverageFactor +/// @param[out] resultRunningMean +/// @param[out] resultRunningVariance +/// @param[in] epsilon Has to be >= CUINFER_BN_MIN_EPSILON. Should be the same +/// in forward and backward functions. +/// @param[out] resultSaveMean Optionally save intermediate results from the +/// forward pass here - can be reused to speed up backward pass. NULL if unused. +/// @param[out] resultSaveInvVariance +/// @param[in] activationDesc +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[in] workSpaceSizeInBytes +/// @param[out] reserveSpace +/// @param[out] reserveSpaceSizeInBytes +/// @return +cuinferStatus_t CUINFERWINAPI cuinferBatchNormalizationForwardTrainingEx( + cuinferHandle_t handle, cuinferBatchNormMode_t mode, + cuinferBatchNormOps_t bnOps, const void *alpha, const void *beta, + const cuinferTensorDescriptor_t xDesc, const void *xData, + const cuinferTensorDescriptor_t zDesc, const void *zData, + const cuinferTensorDescriptor_t yDesc, void *yData, + const cuinferTensorDescriptor_t bnScaleBiasMeanVarDesc, const void *bnScale, + const void *bnBias, double exponentialAverageFactor, + void *resultRunningMean, void *resultRunningVariance, double epsilon, + void *resultSaveMean, void *resultSaveInvVariance, + cuinferActivationDescriptor_t activationDesc, void *workspace, + size_t workSpaceSizeInBytes, void *reserveSpace, + size_t reserveSpaceSizeInBytes); + +/// @brief Performs Batch Normalization during Inference: +/// @details y[i] = bnScale[k] * (x[i] - estimatedMean[k]) / sqrt(epsilon + +/// estimatedVariance[k]) + bnBias[k] with bnScale, bnBias, runningMean, +/// runningInvVariance tensors indexed according to spatial or per-activation +/// mode. Refer to cuinferBatchNormalizationForwardTraining above for notes on +/// function arguments. +/// @param[in] handle The libinfer handle. +/// @param[in] mode +/// @param[in] alpha alpha[0] = result blend factor +/// @param[in] beta beta[0] = dest layer blend factor +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x NxCxHxW +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y NxCxHxW +/// @param[in] bnScaleBiasMeanVarDesc +/// @param[in] bnScale +/// @param[in] bnBias +/// @param[in] estimatedMean +/// @param[in] estimatedVariance +/// @param[in] epsilon +/// @return +cuinferStatus_t CUINFERWINAPI cuinferBatchNormalizationForwardInference( + cuinferHandle_t handle, cuinferBatchNormMode_t mode, const void *alpha, + const void *beta, const cuinferTensorDescriptor_t xDesc, const void *x, + const cuinferTensorDescriptor_t yDesc, void *y, + const cuinferTensorDescriptor_t bnScaleBiasMeanVarDesc, const void *bnScale, + const void *bnBias, const void *estimatedMean, + const void *estimatedVariance, double epsilon); + +/// @defgroup SpatialTransformer Spatial Transform Apis +/// @note APIs for spatial transformer network + +typedef struct cuinferDropoutStruct *cuinferDropoutDescriptor_t; + +/// @brief +/// @param[out] dropoutDesc +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferCreateDropoutDescriptor(cuinferDropoutDescriptor_t *dropoutDesc); + +/// @brief +/// @param[in] dropoutDesc +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferDestroyDropoutDescriptor(cuinferDropoutDescriptor_t dropoutDesc); + +/// @brief Helper function to determine size of the states to be passed to +/// LibinferSetDropoutDescriptor. +/// @param[in] handle The libinfer handle. +/// @param[out] sizeInBytes The result extra temporary space size in bytes. +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferDropoutGetStatesSize(cuinferHandle_t handle, size_t *sizeInBytes); + +/// @brief helper function to determine size of the reserve space to be passed +/// to dropout forward/backward calls. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[out] sizeInBytes The result extra temporary space size in bytes. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferDropoutGetReserveSpaceSize( + cuinferTensorDescriptor_t xdesc, size_t *sizeInBytes); + +/// @brief +/// @param[in] dropoutDesc +/// @param[in] handle The libinfer handle. +/// @param[in] dropout +/// @param[out] states +/// @param[in] stateSizeInBytes +/// @param[in] seed +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferSetDropoutDescriptor(cuinferDropoutDescriptor_t dropoutDesc, + cuinferHandle_t handle, float dropout, void *states, + size_t stateSizeInBytes, unsigned long long seed); + +/// @brief Restores the dropout descriptor to a previously saved-off state +/// @param dropoutDesc +/// @param handle +/// @param dropout +/// @param states +/// @param stateSizeInBytes +/// @param seed +/// @return +cuinferStatus_t CUINFERWINAPI cuinferRestoreDropoutDescriptor( + cuinferDropoutDescriptor_t dropoutDesc, cuinferHandle_t handle, + float dropout, void *states, size_t stateSizeInBytes, + unsigned long long seed); + +/// @brief +/// @param[in] dropoutDesc +/// @param[in] handle The libinfer handle. +/// @param[out] dropout +/// @param[out] states +/// @param[out] seed +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetDropoutDescriptor( + cuinferDropoutDescriptor_t dropoutDesc, cuinferHandle_t handle, + float *dropout, void **states, unsigned long long *seed); + +/// @brief +/// @param[in] handle The libinfer handle. +/// @param[in] dropoutDesc +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @param[in] reserveSpace +/// @param[in] reserveSpaceSizeInBytes +/// @return +cuinferStatus_t CUINFERWINAPI cuinferDropoutForward( + cuinferHandle_t handle, const cuinferDropoutDescriptor_t dropoutDesc, + const cuinferTensorDescriptor_t xDesc, const void *x, + const cuinferTensorDescriptor_t yDesc, void *y, void *reserveSpace, + size_t reserveSpaceSizeInBytes); + +/// @defgroup BasicRNNAPIs Basic RNN APIs + +/// @ingroup BasicRNNAPIs +typedef enum { + CUINFER_RNN_ALGO_STANDARD = 0, + CUINFER_RNN_ALGO_PERSIST_STATIC = 1, + CUINFER_RNN_ALGO_PERSIST_DYNAMIC = 2, + CUINFER_RNN_ALGO_COUNT = 3, +} cuinferRNNAlgo_t; + +/// @ingroup BasicRNNAPIs +typedef enum { + CUINFER_RNN_RELU = 0, ///< Basic RNN cell type with ReLu activation. + CUINFER_RNN_TANH = 1, ///< Basic RNN cell type with tanh activation. + CUINFER_LSTM = 2, ///< LSTM with no peephole connections. + CUINFER_GRU = 3, ///< Using h' = tanh(r * Uh(t-1) + Wx) and h = (1 - z) * h' + + ///< z * h(t-1); +} cuinferRNNMode_t; + +/// @ingroup BasicRNNAPIs +typedef enum { + CUINFER_UNIDIRECTIONAL = 0, ///< Aingle direction network. + CUINFER_BIDIRECTIONAL = 1, ///< Output concatination at each layer. +} cuinferDirectionMode_t; + +/// @ingroup BasicRNNAPIs +typedef enum { + CUINFER_LINEAR_INPUT = + 0, ///< Adjustable weight matrix in first layer input GEMM. + CUINFER_SKIP_INPUT = + 1, ///< Fixed identity matrix in the first layer input GEMM. +} cuinferRNNInputMode_t; + +/// @ingroup BasicRNNAPIs +struct cuinferRNNStruct; +/// @ingroup BasicRNNAPIs +typedef struct cuinferRNNStruct *cuinferRNNDescriptor_t; + +/// @ingroup BasicRNNAPIs +struct cuinferPersistentRNNPlan; +/// @ingroup BasicRNNAPIs +typedef struct cuinferPersistentRNNPlan *cuinferPersistentRNNPlan_t; + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[out] rnnDesc +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferCreateRNNDescriptor(cuinferRNNDescriptor_t *rnnDesc); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[in] rnnDesc +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferDestroyRNNDescriptor(cuinferRNNDescriptor_t rnnDesc); + +/// @brief +/// @details \p dataType in weight descriptors and input descriptors is used to +/// describe data/parameter storage. Dropout is between RNN layers, not between +/// recurrent steps. +/// @ingroup BasicRNNAPIs +/// @param handle +/// @param rnnDesc +/// @param hiddenSize +/// @param numLayers +/// @param dropoutDesc +/// @param inputMode +/// @param direction +/// @param mode +/// @param algo +/// @param mathPrec In the RNN descriptor is determines compute math precision, +/// modified by ::cuinferMathType_t. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferSetRNNDescriptor( + cuinferHandle_t handle, cuinferRNNDescriptor_t rnnDesc, + const int hiddenSize, const int numLayers, + cuinferDropoutDescriptor_t dropoutDesc, cuinferRNNInputMode_t inputMode, + cuinferDirectionMode_t direction, cuinferRNNMode_t mode, + cuinferRNNAlgo_t algo, cuinferDataType_t mathPrec); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[in] handle The libinfer handle. +/// @param[in] rnnDesc +/// @param[out] hiddenSize +/// @param[out] numLayers +/// @param[out] dropoutDesc +/// @param[out] inputMode +/// @param[out] direction +/// @param[out] mode +/// @param[out] algo +/// @param[out] mathPrec +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetRNNDescriptor( + cuinferHandle_t handle, cuinferRNNDescriptor_t rnnDesc, int *hiddenSize, + int *numLayers, cuinferDropoutDescriptor_t *dropoutDesc, + cuinferRNNInputMode_t *inputMode, cuinferDirectionMode_t *direction, + cuinferRNNMode_t *mode, cuinferRNNAlgo_t *algo, + cuinferDataType_t *mathPrec); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[out] rnnDesc +/// @param[in] mType +/// @return +cuinferStatus_t CUINFERWINAPI cuinferSetRNNMatrixMathType( + cuinferRNNDescriptor_t rnnDesc, cuinferMathType_t mType); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[in] rnnDesc +/// @param[out] mType +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetRNNMatrixMathType( + cuinferRNNDescriptor_t rnnDesc, cuinferMathType_t *mType); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[in] handle The libinfer handle. +/// @param[out] rnnDesc +/// @param[in] recProjSize +/// @param[in] outProjSize +/// @return +cuinferStatus_t CUINFERWINAPI cuinferSetRNNProjectionLayers( + cuinferHandle_t handle, cuinferRNNDescriptor_t rnnDesc, + const int recProjSize, const int outProjSize); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[in] handle The libinfer handle. +/// @param[in] rnnDesc +/// @param[out] recProjSize +/// @param[out] outProjSize +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetRNNProjectionLayers( + cuinferHandle_t handle, const cuinferRNNDescriptor_t rnnDesc, + int *recProjSize, int *outProjSize); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @note Expensive. Creates the plan for the specific settings. +/// @param[in] rnnDesc +/// @param[in] minibatch +/// @param[in] dataType +/// @param[out] plan +/// @return +cuinferStatus_t CUINFERWINAPI cuinferCreatePersistentRNNPlan( + cuinferRNNDescriptor_t rnnDesc, const int minibatch, + const cuinferDataType_t dataType, cuinferPersistentRNNPlan_t *plan); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[in] plan +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferDestroyPersistentRNNPlan(cuinferPersistentRNNPlan_t plan); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[in] rnnDesc +/// @param[out] plan +/// @return +cuinferStatus_t CUINFERWINAPI cuinferSetPersistentRNNPlan( + cuinferRNNDescriptor_t rnnDesc, cuinferPersistentRNNPlan_t plan); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[in] handle The libinfer handle. +/// @param[in] rnnDesc +/// @param[out] seqLength +/// @param[out] xDesc +/// @param[out] sizeInBytes The result extra temporary space size in bytes. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetRNNTrainingReserveSize( + cuinferHandle_t handle, const cuinferRNNDescriptor_t rnnDesc, + const int seqLength, const cuinferTensorDescriptor_t *xDesc, + size_t *sizeInBytes); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[in] handle The libinfer handle. +/// @param[in] rnnDesc +/// @param[out] xDesc +/// @param[out] sizeInBytes The result extra temporary space size in bytes. +/// @param[out] dataType +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetRNNParamsSize( + cuinferHandle_t handle, const cuinferRNNDescriptor_t rnnDesc, + const cuinferTensorDescriptor_t xDesc, size_t *sizeInBytes, + cuinferDataType_t dataType); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[in] handle The libinfer handle. +/// @param[in] rnnDesc +/// @param[out] pseudoLayer +/// @param[out] xDesc +/// @param[out] wDesc +/// @param[out] w +/// @param[out] linLayerID +/// @param[out] linLayerMatDesc +/// @param[out] linLayerMat +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetRNNLinLayerMatrixParams( + cuinferHandle_t handle, const cuinferRNNDescriptor_t rnnDesc, + const int pseudoLayer, const cuinferTensorDescriptor_t xDesc, + const cuinferFilterDescriptor_t wDesc, const void *w, const int linLayerID, + cuinferFilterDescriptor_t linLayerMatDesc, void **linLayerMat); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[in] handle The libinfer handle. +/// @param[in] rnnDesc +/// @param[out] pseudoLayer +/// @param[out] xDesc +/// @param[out] wDesc +/// @param[out] w +/// @param[out] linLayerID +/// @param[out] linLayerBiasDesc +/// @param[out] linLayerBias +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetRNNLinLayerBiasParams( + cuinferHandle_t handle, const cuinferRNNDescriptor_t rnnDesc, + const int pseudoLayer, const cuinferTensorDescriptor_t xDesc, + const cuinferFilterDescriptor_t wDesc, const void *w, const int linLayerID, + cuinferFilterDescriptor_t linLayerBiasDesc, void **linLayerBias); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[in] handle The libinfer handle. +/// @param[in] rnnDesc +/// @param[in] seqLength +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] hxDesc +/// @param[in] hx +/// @param[in] cxDesc +/// @param[in] cx +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] The const pointer of input filter w. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @param[in] hyDesc +/// @param[out] hy +/// @param[in] cyDesc +/// @param[out] cy +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[in] workSpaceSizeInBytes +/// @return +cuinferStatus_t CUINFERWINAPI cuinferRNNForwardInference( + cuinferHandle_t handle, const cuinferRNNDescriptor_t rnnDesc, + const int seqLength, const cuinferTensorDescriptor_t *xDesc, const void *x, + const cuinferTensorDescriptor_t hxDesc, const void *hx, + const cuinferTensorDescriptor_t cxDesc, const void *cx, + const cuinferFilterDescriptor_t wDesc, const void *w, + const cuinferTensorDescriptor_t *yDesc, void *y, + const cuinferTensorDescriptor_t hyDesc, void *hy, + const cuinferTensorDescriptor_t cyDesc, void *cy, void *workspace, + size_t workSpaceSizeInBytes); + +/// @brief +/// @ingroup BasicRNNAPIs +/// @param[in] handle The libinfer handle. +/// @param[in] rnnDesc +/// @param[in] seqLength +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] hxDesc +/// @param[in] hx +/// @param[in] cxDesc +/// @param[in] cx +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] The const pointer of input filter w. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @param[in] hyDesc +/// @param[out] hy +/// @param[in] cyDesc +/// @param[out] cy +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[in] workSpaceSizeInBytes +/// @param[in] reserveSpace +/// @param[in] reserveSpaceSizeInBytes +/// @return +cuinferStatus_t CUINFERWINAPI cuinferRNNForwardTraining( + cuinferHandle_t handle, const cuinferRNNDescriptor_t rnnDesc, + const int seqLength, const cuinferTensorDescriptor_t *xDesc, const void *x, + const cuinferTensorDescriptor_t hxDesc, const void *hx, + const cuinferTensorDescriptor_t cxDesc, const void *cx, + const cuinferFilterDescriptor_t wDesc, const void *w, + const cuinferTensorDescriptor_t *yDesc, void *y, + const cuinferTensorDescriptor_t hyDesc, void *hy, + const cuinferTensorDescriptor_t cyDesc, void *cy, void *workspace, + size_t workSpaceSizeInBytes, void *reserveSpace, + size_t reserveSpaceSizeInBytes); + +/// CTC LOSS +typedef enum { + CUINFER_CTC_LOSS_ALGO_DETERMINISTIC = 0, + CUINFER_CTC_LOSS_ALGO_NON_DETERMINISTIC = 1 +} cuinferCTCLossAlgo_t; + +/// Input normalization mode for loss function +typedef enum { + CUINFER_LOSS_NORMALIZATION_NONE = 0, + CUINFER_LOSS_NORMALIZATION_SOFTMAX = 1 +} cuinferLossNormalizationMode_t; + +/// CTC (Connectionist Temporal Classification) loss descriptor +/// create/destory/set/get functions +cuinferStatus_t CUINFERWINAPI +cuinferCreateCTCLossDescriptor(cuinferCTCLossDescriptor_t *ctcLossDesc); + +/// @brief +/// @param[out] ctcLossDesc +/// @param[in] compType +/// @return +cuinferStatus_t CUINFERWINAPI cuinferSetCTCLossDescriptor( + cuinferCTCLossDescriptor_t ctcLossDesc, cuinferDataType_t compType); + +/// @brief +/// @param[out] ctcLossDesc +/// @param[in] compType +/// @param[in] normMode +/// @param[in] gradMode +/// @return +cuinferStatus_t CUINFERWINAPI cuinferSetCTCLossDescriptorEx( + cuinferCTCLossDescriptor_t ctcLossDesc, cuinferDataType_t compType, + cuinferLossNormalizationMode_t normMode, cuinferNanPropagation_t gradMode); + +/// @brief +/// @param[out] ctcLossDesc +/// @param[in] compType +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetCTCLossDescriptor( + cuinferCTCLossDescriptor_t ctcLossDesc, cuinferDataType_t *compType); + +/// @brief +/// @param[out] ctcLossDesc +/// @param[in] compType +/// @param[in] normMode +/// @param[in] gradMode +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetCTCLossDescriptorEx( + cuinferCTCLossDescriptor_t ctcLossDesc, cuinferDataType_t *compType, + cuinferLossNormalizationMode_t *normMode, + cuinferNanPropagation_t *gradMode); + +/// @brief +/// @param[in] ctcLossDesc +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferDestroyCTCLossDescriptor(cuinferCTCLossDescriptor_t ctcLossDesc); + +/// @brief Return the ctc costs and gradients, given the probabilities and +/// labels. +/// @param[in] handle The libinfer handle. +/// @param[in] probsDesc Tensor descriptor for probabilities, the dimensions are +/// T,N,A (T is the timing steps, N is the mini batch size, A is the alphabet +/// size). +/// @param[in] probs Probabilities after softmax, in GPU memory. +/// @param[in] labels Labels, in CPU memory. +/// @param[in] labelLengths The length of each label, in CPU memory. +/// @param[in] inputLengths The lengths of timing steps in each batch, in CPU +/// memory. +/// @param[out] costs The returned costs of CTC, in GPU memory. +/// @param[in] gradientsDesc Tensor descriptor for gradients, the dimensions +/// are T,N,A. +/// @param[out] gradients The returned CTC gradients, in GPU memory, to compute +/// costs only, set it to NULL. +/// @param[in] algo Algorithm selected, supported now 0 and 1. +/// @param[in] ctcLossDesc +/// @param[in] workspace Pointer to the workspace, in GPU memory. +/// @param[in] workSpaceSizeInBytes Size of the workspace. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferCTCLoss( + cuinferHandle_t handle, const cuinferTensorDescriptor_t probsDesc, + const void *probs, const int *labels, const int *labelLengths, + const int *inputLengths, void *costs, + const cuinferTensorDescriptor_t gradientsDesc, void *gradients, + cuinferCTCLossAlgo_t algo, cuinferCTCLossDescriptor_t ctcLossDesc, + void *workspace, size_t workSpaceSizeInBytes); + +/// return the workspace size needed for ctc + +/// @brief +/// @param[in] handle The libinfer handle. +/// @param[in] probsDesc Tensor descriptor for probabilities, the dimensions are +/// T,N,A (T is the timing steps, N is the mini batch size, A is the alphabet +/// size). +/// @param[in] gradientsDesc Tensor descriptor for gradients, the dimensions are +/// T,N,A. To compute costs only, set it to nullptr. +/// @param[in] labels labels, in CPU memory +/// @param[in] labelLengths The length of each label, in CPU memory +/// @param[in] inputLengths The lengths of timing steps in each batch, in CPU +/// memory +/// @param[in] algo The algorithm selected. Algo 0 and 1 are supported for now. +/// @param[in] ctcLossDesc +/// @param[out] sizeInBytes pointer to the returned workspace size +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetCTCLossWorkspaceSize( + cuinferHandle_t handle, const cuinferTensorDescriptor_t probsDesc, + const cuinferTensorDescriptor_t gradientsDesc, const int *labels, + const int *labelLengths, const int *inputLengths, cuinferCTCLossAlgo_t algo, + cuinferCTCLossDescriptor_t ctcLossDesc, size_t *sizeInBytes); + +typedef struct { + union Algorithm { + cuinferConvolutionFwdAlgo_t convFwdAlgo; + cuinferConvolutionBwdFilterAlgo_t convBwdFilterAlgo; + cuinferConvolutionBwdDataAlgo_t convBwdDataAlgo; + cuinferRNNAlgo_t RNNAlgo; + cuinferCTCLossAlgo_t CTCLossAlgo; + } algo; +} cuinferAlgorithm_t; + +/// Struct containing useful informaiton for each API call. +typedef struct { + unsigned cuinfer_version; + cuinferStatus_t cuinferStatus; + unsigned time_sec; ///< Epoch time in seconds. + unsigned time_usec; ///< Microseconds part of epoch time. + unsigned time_delta; ///< time since start in seconds. + cuinferHandle_t handle; ///< Cuinfer handle. + cudaStream_t stream; ///< Cuda stream ID. + unsigned long long pid; ///< Process ID. + unsigned long long tid; ///< Thread ID. + int cudaDeviceId; ///< CUDA device ID. + int reserved[15]; ///< Reserved for future use. +} cuinferDebug_t; + +/// @defgroup BertBaseInt8TransformerFunctions Bert Base Int8 Transformer +/// Functions + +/// @brief +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] token_emb +/// @param[in] pos_emb +/// @param[in] tokens +/// @param[out] output +/// @param[out] pad_mask +/// @param[in] pad_id +/// @param[in] batch_size +/// @param[in] seq_len +/// @param[in] hidden_dim +/// @param[in] stream +/// @param[in] lang_emb +/// @param[in] lang_id +/// @param[in] multilg_type +/// @param[in] dequant_scale +/// @param[in] scaled +/// @return * CUINFER_STATUS_SUCCESS +cuinferStatus_t cuinferEncEmbI8I(const void *token_emb, const void *pos_emb, + const void *tokens, void *output, + void *pad_mask, int pad_id, int batch_size, + int seq_len, int hidden_dim, + cudaStream_t stream, const void *lang_emb, + const void *lang_id, int multilg_type, + float dequant_scale, bool scaled); + +/// @brief +/// @details Description: from ixrt cuinferEncEmbI8I, +/// and the pad_mask is int32 instead of int8 from previous interface. +/// +/// Params Mapping: +/// | src | dst | +/// |---------------|----------------| +/// | token_emb | token_emb | +/// | pos_emb | pos_emb | +/// | tokens | tokens | +/// | output | output | +/// | pad_mask | pad_masktokens | +/// | pad_id | pad_id | +/// | batch_size | batch_size | +/// | seq_len | seq_len | +/// | hidden_dim | hidden_dim | +/// | stream | stream | +/// | lang_emb | lang_emb | +/// | lang_id | lang_id | +/// | multilg_type | multilg_type | +/// | dequant_scale | dequant_scale | +/// | scaled | scaled | +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] token_emb +/// @param[in] pos_emb +/// @param[in] tokens +/// @param[out] output +/// @param[out] pad_mask +/// @param[in] pad_id +/// @param[in] batch_size +/// @param[in] seq_len +/// @param[in] hidden_dim +/// @param[in] stream +/// @param[in] lang_emb +/// @param[in] lang_id +/// @param[in] multilg_type +/// @param[in] dequant_scale +/// @param[in] scaled +/// @return * CUINFER_STATUS_SUCCESS +cuinferStatus_t cuinferEncEmbI8I_M8I(const void *token_emb, const void *pos_emb, + const void *tokens, void *output, + void *pad_mask, int pad_id, int batch_size, + int seq_len, int hidden_dim, + cudaStream_t stream, const void *lang_emb, + const void *lang_id, int multilg_type, + float dequant_scale, bool scaled); + +/// @brief +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] token_num +/// @param[in] hidden_size +/// @param[in] stream +/// @param[in, out] input +/// @param[out] output +/// @param[in] scale +/// @param[in] bias +/// @param[in] residual_bias +/// @param[in] quant_scale +/// @param[in] is_post_ln +/// @param[in] out_col32 +/// @return * CUINFER_STATUS_SUCCESS +cuinferStatus_t +cuinferLayernormResualI8O(int token_num, int hidden_size, cudaStream_t stream, + void *input, void *output, const void *scale, + const void *bias, const void *residual_bias, + float quant_scale, bool is_post_ln, bool out_col32); + +/// @brief +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] batch_token_num +/// @param[in] hidden_size +/// @param[in] stream +/// @param[in] ori_qkv +/// @param[in] qkv_bias +/// @param[out] new_qkv +/// @param[in] max_batch_dim +/// @param[in] batch_seq_len +/// @param[in] dim_per_head +/// @param[in] head_num +/// @param[in] quant_scale +/// @param[in] dequant_scale +/// @param[in] in_col32 +/// @return * CUINFER_STATUS_SUCCESS +cuinferStatus_t cuinferArrangeEncselfQkvI8II8O( + int batch_token_num, int hidden_size, cudaStream_t stream, + const void *ori_qkv, const void *qkv_bias, void *new_qkv, int max_batch_dim, + int batch_seq_len, int dim_per_head, int head_num, float quant_scale, + float dequant_scale, bool in_col32); + +/// @brief +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] batch_size +/// @param[in] batch_seq_len +/// @param[in] head_num +/// @param[in] stream +/// @param[out] correlation +/// @param[in] src_padding_mask +/// @param[out] outputs +/// @param[in] quant_scale +/// @param[in] dequant_scale +/// @return * CUINFER_STATUS_SUCCESS +cuinferStatus_t cuinferCorrelationSoftmaxEncselfI32II8O( + int batch_size, int batch_seq_len, int head_num, cudaStream_t stream, + void *correlation, const void *src_padding_mask, void *outputs, + float quant_scale, float dequant_scale); + +/// @brief +/// @details Description: from ixrt IxinferCorrelationSoftmaxEncselfI8II8O +/// seperate correlation's input and output from inplace algorithm. +/// +/// Params Mapping: +/// | src | dst | +/// |------------------|------------------| +/// | batch_size | batch_size | +/// | batch_seq_len | batch_seq_len | +/// | head_num | head_num | +/// | stream | stream | +/// | correlation | correlation | +/// | src_padding_mask | src_padding_mask | +/// | outputs | correlation | +/// | quant_scale | quant_scale | +/// | dequant_scale | dequant_scale | +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] batch_size +/// @param[in] batch_seq_len +/// @param[in] head_num +/// @param[in] stream +/// @param[out] correlation +/// @param[in] src_padding_mask +/// @param[out] outputs +/// @param[in] quant_scale +/// @param[in] dequant_scale +/// @return * CUINFER_STATUS_SUCCESS +cuinferStatus_t cuinferCorrelationSoftmaxEncselfI8II8O( + int batch_size, int batch_seq_len, int head_num, cudaStream_t stream, + void *correlation, const void *src_padding_mask, void *outputs, + float quant_scale, float dequant_scale); + +/// @brief +/// @details Description: from ixrt IxinferArrangeAttenOutputI8II8O +/// defalt \p max_thread_per_block to 1024. +/// +/// Params Mapping: +/// | src | dst | +/// |-----------------|----------------------| +/// | batch_token_num | batch_token_num | +/// | hidden_size | hidden_size | +/// | stream | stream | +/// | ori_q | ori_q | +/// | new_q | new_q | +/// | beam_size | beam_size | +/// | dim_per_head | dim_per_head | +/// | head_num | head_num | +/// | 1024 | max_thread_per_block | +/// | quant_scale | quant_scale | +/// | dequant_scale | dequant_scale | +/// | out_col32 | | +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] batch_token_num +/// @param[in] hidden_size +/// @param[in] stream +/// @param[in] ori_q +/// @param[out] new_q +/// @param[in] beam_size +/// @param[in] dim_per_head +/// @param[in] head_num +/// @param[in] quant_scale +/// @param[in] dequant_scale +/// @param[in] out_col32 +/// @return +/// * ::CUINFER_STATUS_SUCCESS +cuinferStatus_t cuinferArrangeAttenOutputI8II8O( + int batch_token_num, int hidden_size, cudaStream_t stream, + const void *ori_q, void *new_q, int beam_size, int dim_per_head, + int head_num, float quant_scale, float dequant_scale, bool out_col32); + +/// @brief +/// @ingroup BertBaseInt8TransformerFunctions +/// @details Description: from ixrt IxinferLnResidualI8I +/// +/// Params Mapping: +/// | src | dst | +/// |---------------|---------------| +/// | input | input | +/// | scale | scale | +/// | bias | bias | +/// | residual | residual | +/// | output | output | +/// | batch_tokens | batch_tokens | +/// | hidden_size | hidden_size | +/// | dequant_scale | dequant_scale | +/// | stream | stream | +/// @param[in] input +/// @param[in] scale +/// @param[in] bias +/// @param[in] residual +/// @param[out] output +/// @param[in] batch_tokens +/// @param[in] hidden_size +/// @param[in] dequant_scale +/// @param[in] stream +/// @return +/// * ::CUINFER_STATUS_SUCCESS +cuinferStatus_t cuinferResidualBiaslnI8I(const void *input, const void *scale, + const void *bias, const void *residual, + void *output, int batch_tokens, + int hidden_size, float dequant_scale, + cudaStream_t stream); + +/// @brief +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] input +/// @param[in] scale +/// @param[in] bias +/// @param[in] residual_bias +/// @param[out] output +/// @param[out] residual +/// @param[in] batch_tokens +/// @param[in] hidden_size +/// @param[in] dequant_scale +/// @param[in] quant_scale +/// @param[in] stream +/// @param[in] is_post_ln +/// @param[in] in_col32 +/// @param[in] out_col32 +/// @param[in] colsum +/// @return +/// * ::CUINFER_STATUS_SUCCESS +cuinferStatus_t cuinferResidualBiasLnI8II8O( + const void *input, const void *scale, const void *bias, + const void *residual_bias, void *output, void *residual, int batch_tokens, + int hidden_size, float dequant_scale, float quant_scale, + cudaStream_t stream, bool is_post_ln, bool in_col32, bool out_col32, + const void *colsum = nullptr); + +/// @brief +/// @ingroup BertBaseInt8TransformerFunctions +/// @details Description: from ixrt IxinferResidualBiasLnI8II8O +/// residual_out is write to residual and make it inplace. +/// +/// Param Mappings: +/// | src | dst | +/// |---------------|----------------------| +/// | input | input | +/// | scale | scale | +/// | bias | bias | +/// | residual_bias | residual_bias | +/// | output | output | +/// | residual | residual | +/// | residual_out | residual | +/// | batch_tokens | batch_tokens | +/// | hidden_size | hidden_size | +/// | dequant_scale | dequant_scale | +/// | quant_scale | quant_scale | +/// | 1024 | max_thread_per_block | +/// | stream | stream | +/// | is_post_ln | is_post_ln | +/// | colsum | colsum | +/// @param[in] input +/// @param[in] scale +/// @param[in] bias +/// @param[in] residual_bias +/// @param[out] output +/// @param[out] residual +/// @param[out] residual_out +/// @param[in] batch_tokens +/// @param[in] hidden_size +/// @param[in] dequant_scale +/// @param[in] quant_scale +/// @param[in] stream +/// @param[in] is_post_ln +/// @param[in] colsum +/// @return +/// * ::CUINFER_STATUS_SUCCESS +cuinferStatus_t cuinferResidualBiasLnI8II8OF( + const void *input, const void *scale, const void *bias, + const void *residual_bias, void *output, void *residual, void *residual_out, + int batch_tokens, int hidden_size, float dequant_scale, float quant_scale, + cudaStream_t stream, bool is_post_ln, const void *colsum = nullptr); + +/// @brief +/// @ingroup BertBaseInt8TransformerFunctions +/// @details Description: from ixrt ViterbiDecode, template is specilized +/// according to num_tags internally, slightly change in parameters' order. +/// +/// Param Mappings: +/// | src | dst | +/// |-------------------|-------------------| +/// | stream | stream | +/// | batch_size | batch_size | +/// | seq_len | seq_length | +/// | num_tags | num_tags | +/// | emissions | emissions | +/// | mask | mask | +/// | start_transitions | start_transitions | +/// | transitions | transitions | +/// | end_transitions | end_transitions | +/// | output | best_path | +/// @param[in] stream +/// @param[in] batch_size +/// @param[in] seq_len +/// @param[in] num_tags +/// @param[in, out] emissions +/// @param[in, out] mask +/// @param[out] start_transitions +/// @param[out] transitions +/// @param[out] end_transitions +/// @param[out] output +/// @return +/// * ::CUINFER_STATUS_SUCCESS +cuinferStatus_t cuinferViterbiDecode(cudaStream_t stream, int batch_size, + int seq_len, int num_tags, void *emissions, + void *mask, void *start_transitions, + void *transitions, void *end_transitions, + void *output); + +/// @brief +/// @details From ixrt IxinferMhaI8Launcher. +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] stream +/// @param[in] q +/// @param[in] k +/// @param[in] v +/// @param[in] mask +/// @param[out] c +/// @param[in] batch_size +/// @param[in] head_num +/// @param[in] seq_len +/// @param[in] head_dim +/// @param[in] qmax +/// @param[in] kmax +/// @param[in] vmax +/// @param[in] smax +/// @param[in] qkmax +/// @param[in] rmax +/// @return +/// * ::CUINFER_STATUS_SUCCESS +/// * ::CUINFER_STATUS_INTERNAL_ERROR +cuinferStatus_t cuinferFusedMultiHeadAttentionI8( + cudaStream_t stream, void *q, void *k, void *v, void *mask, void *c, + int batch_size, int head_num, int seq_len, int head_dim, float qmax, + float kmax, float vmax, float smax, float qkmax, float rmax); + +/// @brief +/// @details Description: from ixrt IxinferBiasGeluI8II8O +/// +/// Params Mapping: +/// | src | dst | +/// |-----------------|---------------| +/// | batch_token_num | input | +/// | stream | stream | +/// | input | input | +/// | output | output | +/// | bias | bias | +/// | feature_dim | feature_dim | +/// | dequant_scale | dequant_scale | +/// | quant_scale | quant_scale | +/// | in_col32 | | +/// | out_col32 | | +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] batch_token_num +/// @param[in] stream +/// @param[in] input +/// @param[out] output +/// @param[in] bias +/// @param[in] feature_dim +/// @param[in] dequant_scale +/// @param[in] quant_scale +/// @param[in] in_col32 +/// @param[in] out_col32 +/// @todo remove incol32, outcol32 +/// @todo input should mark as const +/// @return +/// * ::CUINFER_STATUS_SUCCESS +/// * ::CUINFER_STATUS_INTERNAL_ERROR +cuinferStatus_t cuinferBiasGeluI8II8O(int batch_token_num, cudaStream_t stream, + void *input, void *output, + const void *bias, int feature_dim, + float dequant_scale, float quant_scale, + bool in_col32, bool out_col32); + +/// @brief +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] input +/// @param[in] scale +/// @param[in] bias +/// @param[in] residual_bias +/// @param[out] output +/// @param[out] residual +/// @param[in] batch_tokens +/// @param[in] hidden_size +/// @param[in] dequant_scale +/// @param[in] quant_scale +/// @param[in] stream +/// @param[in] is_post_ln +/// @param[in] in_col32 +/// @param[in] out_col32 +/// @param[in] colsum +cuinferStatus_t cuinferResidualBiaslnI32II8O( + const void *input, const void *scale, const void *bias, + const void *residual_bias, void *output, void *residual, int batch_tokens, + int hidden_size, float dequant_scale, float quant_scale, + cudaStream_t stream, bool is_post_ln, bool in_col32, bool out_col32, + const void *colsum); + +/// @brief +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] input +/// @param[in] scale +/// @param[in] bias +/// @param[in] residual +/// @param[out] output +/// @param[in] batch_tokens +/// @param[in] hidden_size +/// @param[in] dequant_scale +/// @param[in] stream +/// @param[in] in_col32 +/// @param[in] colsum +cuinferStatus_t cuinferResidualBiaslnI32I(const void *input, const void *scale, + const void *bias, + const void *residual, void *output, + int batch_tokens, int hidden_size, + float dequant_scale, + cudaStream_t stream, bool in_col32, + const void *colsum); + +/// @brief +/// @details Description: from ixrt IxinferLnResidualI8OLauncher +/// Params Mapping: +/// | src | dst | +/// |---------------|---------------| +/// | token_num | batch_tokens | +/// | hidden_size | hidden_size | +/// | stream | stream | +/// | input | input | +/// | output | output | +/// | residual_out | residual | +/// | scale | scale | +/// | bias | bias | +/// | residual_bias | residual_bias | +/// | quant_scale | quant_scale | +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] input +/// @param[in] scale +/// @param[in] bias +/// @param[in] residual_bias +/// @param[out] output +/// @param[out] residual_out +/// @param[in] token_num +/// @param[in] hidden_size +/// @param[in] quant_scale +/// @param[in] stream +cuinferStatus_t cuinferLayernormResidualI8OFO( + const void *input, const void *scale, const void *bias, + const void *residual_bias, void *output, void *residual_out, int token_num, + int hidden_size, float quant_scale, cudaStream_t stream); + +/// @brief +/// @details Description: from ixrt IxinferArrangeEncselfQkvI8II8O +/// * in_col32 will be removed todo +/// * max_thread_per_block default to 1024 +/// * new_qkv result split to 3 parts and output +/// Params Maping: +/// | src | dst | +/// |-----------------|----------------------| +/// | batch_token_num | batch_token_num | +/// | hidden_size | hidden_size | +/// | stream | stream | +/// | ori_qkv | ori_qkv | +/// | qkv_bias | qkv_bias | +/// | new_q | new_qkv | +/// | new_k | new_qkv | +/// | new_v | new_qkv | +/// | max_batch_dim | max_batch_dim | +/// | batch_seq_len | batch_seq_len | +/// | dim_per_head | dim_per_head | +/// | head_num | head_num | +/// | 1024 | max_thread_per_block | +/// | quant_scale | quant_scale | +/// | dequant_scale | dequant_scale | +/// @ingroup BertBaseInt8TransformerFunctions +/// @param[in] batch_token_num +/// @param[in] hidden_size +/// @param[in] stream +/// @param[in] ori_qkv +/// @param[in] qkv_bias +/// @param[out] new_q +/// @param[out] new_k +/// @param[out] new_v +/// @param[in] max_batch_dim +/// @param[in] batch_seq_len +/// @param[in] dim_per_head +/// @param[in] head_num +/// @param[in] quant_scale +/// @param[in] dequant_scale +cuinferStatus_t cuinferArrangeEncselfQkvSepI8II8O( + int batch_token_num, int hidden_size, cudaStream_t stream, + const void *ori_qkv, const void *qkv_bias, void *new_q, void *new_k, + void *new_v, int max_batch_dim, int batch_seq_len, int dim_per_head, + int head_num, float quant_scale, float dequant_scale); + +/// @defgroup GEMM + +/// @ingroup GEMM +typedef enum { + CUINFER_OP_N = 0, + CUINFER_OP_T = 1, + CUINFER_OP_C = 2, + CUINFER_OP_ROW2_COL16_4R2 = 3, +} cuinferOperation_t; + +/// @ingroup GEMM +typedef enum { + CUINFER_POINTER_MODE_HOST, ///< The pointer is host pointer. + CUINFER_POINTER_MODE_DEVICE, ///< The pointer is device pointer. +} cuinferPointerMode_t; + +/// @ingroup GEMM +typedef enum { + CUINFER_BLAS_GEMM_CUSTOM_NONE = 0, + CUINFER_BLAS_GEMM_CUSTOM_BIAS_ADD_ROW_OUT = 1, + CUINFER_BLAS_GEMM_CUSTOM_HALFBIAS = 2, + CUINFER_BLAS_GEMM_CUSTOM_HALFBIAS_GELU = 3, + CUINFER_BLAS_GEMM_CUSTOM_HALFBIAS_RELU = 4, + CUINFER_BLAS_GEMM_CUSTOM_HALFBIAS_TRANSPOSE = 5, + CUINFER_BLAS_GEMM_CUSTOM_FLOATBIAS = 6, + CUINFER_BLAS_GEMM_CUSTOM_FLOATBIAS_GELU = 7, + CUINFER_BLAS_GEMM_CUSTOM_FLOATBIAS_RELU = 8, + CUINFER_BLAS_GEMM_CUSTOM_FLOATBIAS_TRANSPOSE = 9, + CUINFER_BLAS_GEMM_CUSTOM_HALFBIAS_SIGMOID = 10, + CUINFER_BLAS_GEMM_CUSTOM_FLOATBIAS_SIGMOID = 11, + CUINFER_BLAS_GEMM_CUSTOM_HALFBIAS_SILU = 12, + CUINFER_BLAS_GEMM_CUSTOM_FLOATBIAS_SILU = 13, + CUINFER_BLAS_GEMM_CUSTOM_SIGMOID = 14, + CUINFER_BLAS_GEMM_CUSTOM_SILU = 15, + CUINFER_BLAS_GEMM_CUSTOM_HALFBIAS_TANH = 16, + CUINFER_BLAS_GEMM_CUSTOM_FLOATBIAS_TANH = 17, + CUINFER_BLAS_GEMM_SPECIAL_INT8_FLOATBIAS = 18, + CUINFER_BLAS_GEMM_SPECIAL_INT8_FLOATBIAS_GELU = 19 +} cuinferGEMMCustomOption_t; + +/// @brief +/// @ingroup GEMM +/// @param[in] handle The libinfer handle. +/// @param[in] stream +/// @param[in] ptrMode +/// @param[in] transa +/// @param[in] transb +/// @param[in] m +/// @param[in] n +/// @param[in] k +/// @param[in] alpha Pointer to scaling factor. +/// @param[in] A +/// @param[in] Atype +/// @param[in] lda +/// @param[in] strideA +/// @param[in] B +/// @param[in] Btype +/// @param[in] ldb +/// @param[in] strideB +/// @param[in] beta Pointer to scaling factor. +/// @param[out] C +/// @param[in] Ctype +/// @param[in] ldc +/// @param[in] strideC +/// @param[in] batchCount +/// @param[in] computeType +/// @param[in] scaleType +/// @param[in] customHostPtr +/// @param[in] customDevicePtr +/// @param[in] customOption +/// @return +cuinferStatus_t CUINFERWINAPI cuinferCustomGemm( + cuinferHandle_t handle, cudaStream_t stream, cuinferPointerMode_t ptrMode, + cuinferOperation_t transa, cuinferOperation_t transb, int m, int n, int k, + const void *alpha, const void *A, cudaDataType_t Atype, int lda, + long long int strideA, const void *B, cudaDataType_t Btype, int ldb, + long long int strideB, const void *beta, void *C, cudaDataType_t Ctype, + int ldc, long long int strideC, int batchCount, cudaDataType_t computeType, + cudaDataType_t scaleType, const void *customHostPtr, + const void *customDevicePtr, cuinferGEMMCustomOption_t customOption); + +/// @brief +/// @ingroup GEMM +/// @param[in] m +/// @param[in] n +/// @param[in] k +/// @param[in] transA +/// @param[in] transB +/// @param[in] Atype +/// @param[in] Btype +/// @param[in] Ctype +/// @param[in] computeType +/// @param[in] scaleType +/// @param[out] workspaceSize +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetCustomGemmExWorkspace( + int m, int n, int k, cuinferOperation_t transA, cuinferOperation_t transB, + cudaDataType_t Atype, cudaDataType_t Btype, cudaDataType_t Ctype, + cudaDataType_t computeType, cudaDataType_t scaleType, + size_t *workspaceSize); + +/// @brief +/// @ingroup GEMM +/// @param[in] handle The libinfer handle. +/// @param[in] stream +/// @param[in] ptrMode +/// @param[in] transa +/// @param[in] transb +/// @param[in] m +/// @param[in] n +/// @param[in] k +/// @param[in] alpha Pointer to scaling factor. +/// @param[in] A +/// @param[in] Atype +/// @param[in] lda +/// @param[in] strideA +/// @param[in] B +/// @param[in] Btype +/// @param[in] ldb +/// @param[in] strideB +/// @param[in] beta Pointer to scaling factor. +/// @param[out] C +/// @param[in] Ctype +/// @param[in] ldc +/// @param[in] strideC +/// @param[in] batchCount +/// @param[in] computeType +/// @param[in] scaleType +/// @param[in] customHostPtr +/// @param[in] customDevicePtr +/// @param[in] customOption +/// @param[in] workspace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferCustomGemmEx( + cuinferHandle_t handle, cudaStream_t stream, cuinferPointerMode_t ptrMode, + cuinferOperation_t transa, cuinferOperation_t transb, int m, int n, int k, + const void *alpha, const void *A, cudaDataType_t Atype, int lda, + long long int strideA, const void *B, cudaDataType_t Btype, int ldb, + long long int strideB, const void *beta, void *C, cudaDataType_t Ctype, + int ldc, long long int strideC, int batchCount, cudaDataType_t computeType, + cudaDataType_t scaleType, const void *customHostPtr, + const void *customDevicePtr, cuinferGEMMCustomOption_t customOption, + void *workspace); + +/// @defgroup NMS NoN-Max Suppression(NMS) +/// @note The bounding boxex is of form [xmin, ymin, xmax, ymax, class_id, +/// score], which is 6 floats. The bounding box can be either form of pixel or +/// scaled to 0.0-1.0. + +/// @brief Gpu version of Non-Max Suppression(NMS) over bounding boxex. +/// @ingroup NMS +/// @note The bounding boxex is of form [xmin, ymin, xmax, ymax, class_id, +/// score], which is 6 floats. The bounding box can be either form of pixel or +/// scaled to 0.0-1.0. +/// @param[in] handle The libinfer handle. +/// @param[in] pDetections The input bounding boxex. Device pointer. Size +/// pDetections[nInputs][6]. +/// @param[in] nInputs The number of input bounding boxex. +/// @param[out] pKeepDetections The result bounding boxex. Device pointer. +/// @param[in] nMaxKeep The max result bounding boxex. 0 <= \p nKeep <= \p +/// nMaxKeep. +/// @param[out] nKeep The number of result bounding boxex to kept. +/// @param[in] fIoUThresh The IoU threshold. The bounding boxex will be +/// suppressed if iou score is over this threshold. +/// @param[in] fScoreThresh The score threshold, only higher score are come into +/// consideration. +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[out] outputIndice The index of corresponding result. Set to \p +/// nullptr will disable it. +/// @return +/// * ::CUINFER_STATUS_BAD_PARAM If param is invalid(mostly nMaxKeep too large). +/// * ::CUINFER_STATUS_SUCCESS If success. +cuinferStatus_t CUINFERWINAPI +cuinferNMS(cuinferHandle_t handle, float *pDetections, const int nInputs, + float *pKeepDetections, const int nMaxKeep, int *nKeep, + const float fIoUThresh, const float fScoreThresh, void *workspace, + int *outputIndice = nullptr); + +/// @brief Get the workspace of the corresponding ::cuinferNMS. +/// @ingroup NMS +/// @param pDetections Not used. +/// @param[in] nInputs The number of input bounding boxex. +/// @param pKeepDetections Not used. +/// @param[in] nMaxKeep The max result bounding boxex. 0 <= \p nKeep <= \p +/// nMaxKeep. +/// @param nKeep not used. +/// @param[in] fIoUThresh The score threshold, only higher score are come into +/// consideration. +/// @param[in] fScoreThresh The score threshold, only higher score are come into +/// consideration. +/// @param[out] sizeInBytes The result extra temporary space size in bytes. +/// @param[in] outputIndice Whether output index of corresponding result. +/// @return +/// * ::CUINFER_STATUS_BAD_PARAM If param is invalid(mostly nMaxKeep too large). +/// * ::CUINFER_STATUS_SUCCESS If success. +cuinferStatus_t CUINFERWINAPI cuinferGetNMSWorkspaceSize( + float *pDetections, const int nInputs, float *pKeepDetections, + const int nMaxKeep, int *nKeep, const float fIoUThresh, + const float fScoreThresh, size_t *sizeInBytes, bool outputIndice = false); + +/// @brief The batched version of ::cuinferNMS. +/// @ingroup NMS +/// @param[in] handle The libinfer handle. +/// @param[in] batch The batch. A quantity used or made at one time. +/// @param[in] pDetections The input bounding boxex. Device pointer. Size +/// pDetections[batch][nInputs][6]. +/// @param[in] nInputs The number of input bounding boxex in each batch. +/// @param[out] pKeepDetections The result bounding boxex. Device pointer. Note +/// the padding when first fewer batchs not full. +/// @param[in] nMaxKeep The max result bounding boxex. 0 <= \p nKeep <= \p +/// nMaxKeep for every batch. +/// @param[out] nKeep The number of result bounding boxex to kept for each +/// batch. Size batch. +/// @param[in] fIoUThresh The score threshold, only higher score are come into +/// consideration. +/// @param[in] fScoreThresh The score threshold, only higher score are come into +/// consideration. +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function.Whether output index of corresponding +/// result.t *pKeepDetections, const int nMaxKeep, +/// * ::CUINFER_STATUS_BAD_PARAM If param is invalid(mostly nMaxKeep too large). +/// * ::CUINFER_STATUS_SUCCESS If success. +cuinferStatus_t CUINFERWINAPI +cuinferNMSBatched(cuinferHandle_t handle, int batch, float *pDetections, + const int nInputs, float *pKeepDetections, const int nMaxKeep, + int *nKeep, const float fIoUThresh, const float fScoreThresh, + void *workspace, int *outputIndice = nullptr); + +/// @brief Get the workspace of the corresponding ::cuinferGetNMSWorkspaceSize. +/// @ingroup NMS +/// @param[in] batch The batch. A quantity used or made at one time. +/// @param pDetections Not used. +/// @param[in] nInputs The number of input bounding boxex in each batch. +/// @param pKeepDetections Not used. +/// @param[in] nMaxKeep The max result bounding boxex. 0 <= \p nKeep <= \p +/// nMaxKeep for every batch. +/// @param[in] nKeep The number of result bounding boxex to kept for each +/// batch. Size batch. +/// @param[in] fIoUThresh The score threshold, only higher score are come into +/// consideration. +/// @param[in] fScoreThresh The score threshold, only higher score are come into +/// consideration. +/// @param[out] sizeInBytes The result extra temporary space size in bytes. +/// @param[in] outputIndice Whether output index of corresponding result. +/// @return +/// * ::CUINFER_STATUS_BAD_PARAM If param is invalid(mostly nMaxKeep too large). +/// * ::CUINFER_STATUS_SUCCESS If success. +cuinferStatus_t CUINFERWINAPI cuinferGetNMSBatchedWorkspaceSize( + int batch, float *pDetections, const int nInputs, float *pKeepDetections, + const int nMaxKeep, int *nKeep, const float fIoUThresh, + const float fScoreThresh, size_t *sizeInBytes, bool outputIndice = false); + +/// @brief NMS algo specilized for Yolo format. +/// @note The output format is [x, y, w, h, boxscore, class_score1, ..., ] +/// @note Due to the nms process. Only the boxscoore with highest class_score +/// will be kept. And all other classes will be supressed. +/// @ingroup NMS +/// @param[in] handle The libinfer handle. +/// @param[in] n_batch The number of batch. +/// @param[in] n_bbox the number of bbox. +/// @param[in] detection The pointer of input tensor, size is +/// [n_batch][n_bbox][n_class+5]. +/// @param[in] n_class The number of class. +/// @param[out] keep_detection The result bounding boxex. Device pointer. +/// @param[in] max_keep_per_batch The max result bounding boxex. 0 <= \p +/// n_keep_each_batch[i] <= \p max_keep_per_batch. +/// @param[out] n_keep_each_batch The result bounding boxex number for each +/// batch. +/// @param[in] iou_threshold The IoU threshold. The bounding boxex will be +/// suppressed if iou score is over this threshold. +/// @param[in] score_threshold The score threshold, only higher score are come +/// into consideration. +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[out] outputIndice The index of the original input. Set to \p nullptr +/// if unused. +/// @return +/// * ::CUINFER_STATUS_BAD_PARAM If param is invalid(mostly nMaxKeep too large). +/// * ::CUINFER_STATUS_SUCCESS If success. +cuinferStatus_t CUINFERWINAPI cuinferNMSBatchedYoloFused( + cuinferHandle_t handle, int n_batch, int n_bbox, float *detection, + int n_class, float *keep_detection, int max_keep_per_batch, + int *n_keep_each_batch, float iou_threshold, float score_threshold, + void *workspace, int *outputIndice = nullptr); + +/// @brief Get the workspace of the ::cuinferNMSBatchedYoloFused. +/// @ingroup NMS +/// @param[in] n_batch The number of batch. +/// @param[in] n_bbox the number of bbox. +/// @param detection Not used. +/// @param[in] n_class The number of class. +/// @param keep_detection Not used. +/// @param[in] max_keep_per_batch The max result bounding boxex. 0 <= \p +/// n_keep_each_batch[i] <= \p max_keep_per_batch. +/// @param n_keep_each_batch Not used. +/// @param[in] iou_threshold The IoU threshold. The bounding boxex will be +/// suppressed if iou score is over this threshold. +/// @param[in] score_threshold The score threshold, only higher score are come +/// into consideration. +/// @param[out] workspace_size_in_bytes The result workspace size in bytes. +/// @param[in] outputIndice Whether output index of corresponding result. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetNMSBatchedYoloFusedWorkspaceSize( + int n_batch, int n_bbox, float *detection, int n_class, + float *keep_detection, int max_keep_per_batch, int *n_keep_each_batch, + float iou_threshold, float score_threshold, size_t *workspace_size_in_bytes, + bool outputIndice = false); + +/// @defgroup TransformerFMHAAPIs Transformer FHMA APIS + +struct cuinferFMHAParam { + float q_amax = 0.0f; + float k_amax = 0.0f; + float v_amax = 0.0f; + float r_amax = 1.0f; + float s_max = 1.0f; + cuinferSoftmaxAlgorithm_t softmax_algo = + cuinferSoftmaxAlgorithm_t::CUINFER_SOFTMAX_FAST; +}; + +/// @brief +/// @ingroup TransformerFMHAAPIs +/// @param[in] handle The libinfer handle. +/// @param[in] fmha_param +/// @param[in] computeType +/// @param[in] dataType +/// @param[in] maskType +/// @param[in] q_desc +/// @param[in] q_data +/// @param[in] k_desc +/// @param[in] k_data +/// @param[in] v_desc +/// @param[in] v_data +/// @param[in] mask_desc +/// @param[in] padding_mask +/// @param[in] o_desc +/// @param[out] o_data +/// @param[in] use_tcu +/// @return +cuinferStatus_t CUINFERWINAPI cuinferFMHAForward( + cuinferHandle_t handle, cuinferFMHAParam fmha_param, + cuinferDataType_t computeType, cuinferDataType_t dataType, + cuinferDataType_t maskType, const cuinferTensorDescriptor_t q_desc, + const void *q_data, const cuinferTensorDescriptor_t k_desc, + const void *k_data, const cuinferTensorDescriptor_t v_desc, + const void *v_data, const cuinferTensorDescriptor_t mask_desc, + const void *padding_mask, const cuinferTensorDescriptor_t o_desc, + void *o_data, const bool use_tcu = true); + +/// @ingroup TransformerFMHAAPIs +typedef enum { + CUINFER_FATTN_BHSD = 0, + CUINFER_FATTN_BSHD = 1 +} cuinferFlashAttnLayout_t; + +/// @ingroup TransformerFMHAAPIs +struct cuinferFMHAQuantParam { + float q_amax; + float k_amax; + float v_amax; + float p_amax; + float o_amax; +}; + +/// @ingroup TransformerFMHAAPIs +typedef enum { + CUINFER_FATTN_ALIBI_MODE_SUB_KQ = 0, + CUINFER_FATTN_ALIBI_MODE_SQRT_SUB_QK = 1, +} cuinferFlashAttnAlibiMode_t; + +/// @ingroup TransformerFMHAAPIs +struct cuinferFlashAttnConfigInfo { + cuinferFlashAttnLayout_t layout; + cuinferFMHAQuantParam quantParam; + bool isCausal; + float scaling; + int *qoSeqArray; + int *kvSeqArray; + int kvSeqStart; + int kvSeqEnd; + int kvHeadNum; + bool isAlibi; + cuinferFlashAttnAlibiMode_t alibiMode; + float *slopeM; + int qStride; + int kStride; + int vStride; +}; + +/// @brief +/// @ingroup TransformerFMHAAPIs +/// @param[in] handle The libinfer handle. +/// @param[in] flashAttnInfo +/// @param[in] qDesc +/// @param[in] q +/// @param[in] kDesc +/// @param[in] k +/// @param[in] vDesc +/// @param[in] v +/// @param[in] maskDesc +/// @param[in] mask +/// @param[in] oDesc +/// @param[out] o +/// @return +cuinferStatus_t CUINFERWINAPI cuinferFMHAForwardEx( + cuinferHandle_t handle, const cuinferFlashAttnConfigInfo &flashAttnInfo, + const cuinferTensorDescriptor_t qDesc, const void *q, + const cuinferTensorDescriptor_t kDesc, const void *k, + const cuinferTensorDescriptor_t vDesc, const void *v, + const cuinferTensorDescriptor_t maskDesc, const void *mask, + const cuinferTensorDescriptor_t oDesc, void *o); + +/// @ingroup TransformerFMHAAPIs +typedef enum { + CUINFER_GPTATTEN_CONTEXT = 0, + CUINFER_GPTATTEN_DECODE = 1, +} cuinferGPTFlashAttnMode_t; + +/// @ingroup TransformerFMHAAPIs +struct cuinferGPTFlashAttnConfigInfo { + cuinferGPTFlashAttnMode_t attenMode; + float scaling; + int qHeadnum; + int kvHeadnum; + int maxQSeqlen; + const int* seqArray; +}; + +/// @brief +/// @ingroup TransformerFMHAAPIs +/// @param[in] handle The libinfer handle. +/// @param[in] flashAttnInfo config params of tensorrt llm fmha +/// @param[in] qkvDesc The discriptor of input tensor qkv. +/// @param[in] qkv Const pointer to input tensor qkv. +/// @param[in] pastkvDesc The discriptor of input tensor kv cache. +/// @param[in] pastkv Const pointer to input tensor kv cache. +/// @param[in] oDesc The discriptor of output tensor o. +/// @param[out] o Pointer to output tensor o. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGPTFMHAForward( + cuinferHandle_t handle, + const cuinferGPTFlashAttnConfigInfo& flashAttnInfo, + const cuinferTensorDescriptor_t qkvDesc, + const void* qkv, + const cuinferTensorDescriptor_t pastkvDesc, + const void* pastkv, + const cuinferTensorDescriptor_t oDesc, + void* o); + +/// @brief +/// @param[in] handle The libinfer handle. +/// @param[in] x_desc +/// @param[in] x Const pointer to input tensor x. +/// @param[in] y_desc +/// @param[out] y The discriptor of output tensor y. +/// @param[in] resize_method +/// @param[in] size_h +/// @param[in] size_w +/// @param[in] top +/// @param[in] left +/// @return +cuinferStatus_t CUINFERWINAPI cuinferCropAndResize( + cuinferHandle_t handle, const cuinferTensorDescriptor_t x_desc, + const void *x, const cuinferTensorDescriptor_t y_desc, void *y, + cuinferInterpolationFlag_t resize_method, int size_h, int size_w, int top, + int left); + +/// @brief +/// @param[in] handle The libinfer handle. +/// @param[in] x Const pointer to input tensor x. +/// @param[out] y The discriptor of output tensor y. +/// @param[in] data_in_type +/// @param[in] compute_type +/// @param[in] data_out_type +/// @param[in] anchor_num +/// @param[in] anchors +/// @param[in] grid +/// @param[in] stride +/// @param[in] num_class +/// @param[in] n_batch +/// @param[in] anchor_first +/// @return +cuinferStatus_t CUINFERWINAPI cuinferYoloV5Detect( + cuinferHandle_t handle, const void *x, void *y, + cuinferDataType_t data_in_type, cuinferDataType_t compute_type, + cuinferDataType_t data_out_type, int anchor_num, const int *anchors, + int grid, int stride, int num_class, int n_batch, bool anchor_first); + +/// @defgroup LayerNorm Layer Norm + +/// @brief +/// @ingroup LayerNorm +/// @note Only serves 2-dim N and C +/// @param[in] handle The libinfer handle. +/// @param[in] x Const pointer to input tensor x. +/// @param[out] y The discriptor of output tensor y. +/// @param[in] data_in_type +/// @param[in] compute_type +/// @param[in] data_out_type +/// @param[in] n +/// @param[in] c +/// @param[in] scale +/// @param[in] bias +/// @param[in] epsilon +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferLayerNorm(cuinferHandle_t handle, const void *x, void *y, + cuinferDataType_t data_in_type, cuinferDataType_t compute_type, + cuinferDataType_t data_out_type, int n, int c, + const void *scale, const void *bias, const float epsilon); + +/// @brief +/// @ingroup LayerNorm +/// @param[in] handle The libinfer handle. +/// @param[in] data_type +/// @param[in] input +/// @param[in] ln_scale +/// @param[in] ln_bias +/// @param[in] residual_bias +/// @param[in] residual_in +/// @param[out] residual_out +/// @param[out] output +/// @param[in] batch_tokens +/// @param[in] hidden_size +/// @param[in] is_postln +/// @param[in] epsilon +/// @return +cuinferStatus_t CUINFERWINAPI cuinferBiasResidualLn( + cuinferHandle_t handle, cuinferDataType_t data_type, const void *input, + const void *ln_scale, const void *ln_bias, const void *residual_bias, + const void *residual_in, void *residual_out, void *output, int batch_tokens, + int hidden_size, bool is_postln, float epsilon); + +/// @defgroup GroupNorm Group Norm + +/// @ingroup GroupNorm +typedef enum { + CUINFER_GROUPNORM_AFFINE_NONE = 0, + CUINFER_GROUPNORM_AFFINE_PERCHANNEL = 1, + CUINFER_GROUPNORM_AFFINE_PERGROUP = 2, +} cuinferGroupNormAffineMode; + +/// @brief +/// @ingroup GroupNorm +/// @param[in] handle The libinfer handle. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] scale +/// @param[in] bias +/// @param[in] num_groups +/// @param[in] affineMode +/// @param[in] y +/// @param[in] epsilon +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGroupNorm( + cuinferHandle_t handle, const cuinferTensorDescriptor_t xDesc, + const void *x, const void *scale, const void *bias, const int num_groups, + cuinferGroupNormAffineMode affineMode, void *y, const float epsilon); + +/// @brief +/// @param[in] handle The libinfer handle. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] scale +/// @param[in] bias +/// @param[out] y The discriptor of output tensor y. +/// @param[in] epsilon +/// @return +cuinferStatus_t CUINFERWINAPI cuinferInstanceNorm( + cuinferHandle_t handle, const cuinferTensorDescriptor_t xDesc, + const void *x, const void *scale, const void *bias, void *y, + const float epsilon); + +/// @brief +/// @param[in] handle The libinfer handle. +/// @param[in] x_desc +/// @param[in] x Const pointer to input tensor x. +/// @param[out] y The discriptor of output tensor y. +/// @param[in] n_index +/// @param[in] c_index +/// @param[in] d_index +/// @param[in] h_index +/// @param[in] w_index +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferTranspose(cuinferHandle_t handle, const cuinferTensorDescriptor_t x_desc, + const void *x, void *y, unsigned n_index, unsigned c_index, + unsigned d_index, unsigned h_index, unsigned w_index); + +/// @defgroup TransposedConv Transposed Conv + +/// @ingroup TransposedConv +typedef enum { + CUINFER_CONVOLUTION_TRANSPOSE_ALGO_AUTO = 0, ///< Recommand default. + CUINFER_CONVOLUTION_TRANSPOSE_ALGO_DIRECT = 1, ///< Todo. + CUINFER_CONVOLUTION_TRANSPOSE_ALGO_EXPLICIT_GEMM = 2, ///< For large batch. + CUINFER_CONVOLUTION_TRANSPOSE_ALGO_EXPLICIT_GEMM2 = 3, ///< For small c. + CUINFER_CONVOLUTION_TRANSPOSE_ALGO_IMPLICIT_GEMM = 4, ///< Todo. + CUINFER_CONVOLUTION_TRANSPOSE_ALGO_COUNT = 5, +} cuinferConvolutionTransposeAlgo_t; + +/// @brief +/// @ingroup TransposedConv +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] convDesc The discriptor of convolution. +/// @param[in] algo The algorithm specified. +/// @param[out] workSpaceSizeInBytes +/// @param[in] zDesc +/// @param[in] biasDesc +/// @param[in] activationDesc +/// @param[in] connectionMode The connection mode. +/// @param[in] yDesc The discriptor of tensor y. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetQDEConvolutionTransposedWorkspaceSize( + const cuinferTensorDescriptor_t xDesc, + const cuinferFilterDescriptor_t wDesc, + const cuinferConvolutionDescriptor_t convDesc, + cuinferConvolutionTransposeAlgo_t algo, size_t *workSpaceSizeInBytes, + const cuinferTensorDescriptor_t zDesc, + const cuinferTensorDescriptor_t biasDesc, + const cuinferActivationDescriptor_t activationDesc, + cuinferTensorConnectionMode_t connectionMode, + const cuinferTensorDescriptor_t yDesc); + +/// @brief +/// @details y = clip(round(activate(alpha * conv(x, w) + z * beta + bias) * +/// alpha2)) biasDesc is not used, zDesc == yDesc +/// @ingroup TransposedConv +/// @param[in] handle The libinfer handle. +/// @param[in] alpha Pointer to scaling factor. +/// @param[in] perchannelAlpha +/// @param[in] beta Pointer to scaling factor. +/// @param[in] gamma Pointer to scaling factor. +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] The const pointer of input filter w. +/// @param[in] convDesc The discriptor of convolution. +/// @param[in] algo The algorithm specified. +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[in] workSpaceSizeInBytes +/// @param[in] alpha2 +/// @param[in] zScale +/// @param[in] zDesc +/// @param[in] z +/// @param[in] biasDesc +/// @param[in] bias +/// @param[in] perChannel +/// @param[in] activationDesc +/// @param[in] connectionBeforeActivation Whether activation is performed before +/// connection. +/// @param[in] connectionMode The connection mode. +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferQDEConvolutionTranspose( + cuinferHandle_t handle, const void *alpha, const void *perchannelAlpha, + const void *beta, const void *gamma, const cuinferTensorDescriptor_t xDesc, + const void *x, const cuinferFilterDescriptor_t wDesc, const void *w, + const cuinferConvolutionDescriptor_t convDesc, + cuinferConvolutionTransposeAlgo_t algo, void *workSpace, + size_t workSpaceSizeInBytes, const void *alpha2, const void *zScale, + const cuinferTensorDescriptor_t zDesc, const void *z, + const cuinferTensorDescriptor_t biasDesc, const void *bias, bool perChannel, + const cuinferActivationDescriptor_t activationDesc, + bool connectionBeforeActivation, + cuinferTensorConnectionMode_t connectionMode, + const cuinferTensorDescriptor_t yDesc, void *y); + +/// @defgroup TopK Top-K + +/// @brief +/// @ingroup TopK +/// @param[in] n +/// @param[in] m +/// @param[in] top_k +/// @param[in] sort_dim +/// @param[in] largest +/// @param[in] sorted +/// @param[in] out_value +/// @param[in] out_indice +/// @param[in] data_type +/// @param[out] workspace_size +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferGetTopKWorkspace(int n, int m, int top_k, int sort_dim, bool largest, + bool sorted, bool out_value, bool out_indice, + cuinferDataType_t data_type, size_t *workspace_size); + +/// @brief +/// @ingroup TopK +/// @param[in] handle The libinfer handle. +/// @param[in] input +/// @param[in] n +/// @param[in] m +/// @param[in] top_k +/// @param[in] sort_dim +/// @param[in] largest +/// @param[in] sorted +/// @param[out] out_value +/// @param[out] out_indice +/// @param[in] datatype +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferTopK(cuinferHandle_t handle, const void *input, int n, int m, int top_k, + int sort_dim, bool largest, bool sorted, void *out_value, + int *out_indice, cuinferDataType_t datatype, void *workspace); + +/// @brief +/// @ingroup TopK +/// @param[in] top_k +/// @param[in] batch The batch. A quantity used or made at one time. +/// @param[in] n +/// @param[in] m +/// @param[in] k +/// @param[in] largest +/// @param[in] sorted +/// @param[in] sort_dim +/// @param[in] output +/// @param[in] indice +/// @param[in] datatype +/// @param[out] workspace_size +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetTopKBatchWorkspace( + int top_k, int batch, int n, int m, int k, bool largest, bool sorted, + int sort_dim, bool output, bool indice, cuinferDataType_t datatype, + size_t *workspace_size); + +/// @brief +/// @ingroup TopK +/// @param[in] handle The libinfer handle. +/// @param[in] input +/// @param[in] top_k +/// @param[in] batch The batch. A quantity used or made at one time. +/// @param[in] n +/// @param[in] m +/// @param[in] k +/// @param[in] largest +/// @param[in] sorted +/// @param[in] sort_dim +/// @param[out] output +/// @param[out] indice +/// @param[in] datatype +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @return +cuinferStatus_t CUINFERWINAPI cuinferTopKBatch( + cuinferHandle_t handle, const void *input, int top_k, int batch, int n, + int m, int k, bool largest, bool sorted, int sort_dim, void *output, + int *indice, cuinferDataType_t datatype, void *workspace); + +/// @defgroup Reduce + +/// @brief +/// @ingroup Reduce +/// @param[in] in_type +/// @param[in] acc_type +/// @param[in] out_type +/// @param[in] reduce_op +/// @param[in] n_dims +/// @param[in] dims +/// @param[in] n_reduce_dims +/// @param[in] reduce_dim_index +/// @param[out] workspace_size +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetReduceWorkspace( + cuinferDataType_t in_type, cuinferDataType_t acc_type, + cuinferDataType_t out_type, cuinferReduceTensorOp_t reduce_op, int n_dims, + const int *dims, int n_reduce_dims, const int *reduce_dim_index, + size_t *workspace_size); + +/// @brief +/// @ingroup Reduce +/// @param[in] handle The libinfer handle. +/// @param[in] in +/// @param[out] out +/// @param[in] in_type +/// @param[in] acc_type +/// @param[in] out_type +/// @param[in] reduce_op +/// @param[in] n_dims +/// @param[in] dims +/// @param[in] n_reduce_dims +/// @param[in] reduce_dim_index +/// @param[in] workspace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferReduce(cuinferHandle_t handle, const void *in, void *out, + cuinferDataType_t in_type, cuinferDataType_t acc_type, + cuinferDataType_t out_type, cuinferReduceTensorOp_t reduce_op, + int n_dims, const int *dims, int n_reduce_dims, + const int *reduce_dim_index, void *workspace); + +/// @defgroup HammingDistance Hamming Distance + +/// @ingroup HammingDistance +typedef enum { + CUINFER_HAMMING_DISTANCE_MODE_PER_BIT, + CUINFER_HAMMING_DISTANCE_MODE_PER_CHAR, +} cuinferHammingDistanceMode; + +/// @brief +/// @ingroup HammingDistance +/// @param[in] n +/// @param[in] batch The batch. A quantity used or made at one time. +/// @param[in] mode +/// @param[out] workspace_size +/// @return +cuinferStatus_t CUINFERWINAPI cuinferGetHammingDistanceWorkspace( + int n, int batch, cuinferHammingDistanceMode mode, size_t *workspace_size); + +/// @brief +/// @ingroup HammingDistance +/// @param[in] handle The libinfer handle. +/// @param[in] in_x +/// @param[in] in_y +/// @param[out] out +/// @param[in] n +/// @param[in] batch The batch. A quantity used or made at one time. +/// @param[in] mode +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @return +cuinferStatus_t CUINFERWINAPI +cuinferHammingDistance(cuinferHandle_t handle, const unsigned char *in_x, + const unsigned char *in_y, int *out, int n, int batch, + cuinferHammingDistanceMode mode, void *workspace); + +/// @brief +/// @param[in] handle The libinfer handle. +/// @param[in] rnnDesc +/// @param[in] seqLength +/// @param[in] xDesc The discriptor of input tensor x. +/// @param[in] x Const pointer to input tensor x. +/// @param[in] hxDesc +/// @param[in] hx +/// @param[in] cxDesc +/// @param[in] cx +/// @param[in] wDesc The discriptor of filter w. +/// @param[in] The const pointer of input filter w. +/// @param[in] rDesc +/// @param[in] r +/// @param[in] biasDesc +/// @param[in] bias +/// @param[in] yDesc The discriptor of tensor y. +/// @param[out] y The discriptor of output tensor y. +/// @param[in] hyDesc +/// @param[out] hy +/// @param[in] cyDesc +/// @param[out] cy +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[in] workSpaceSizeInBytes +/// @return +cuinferStatus_t CUINFERWINAPI cuinferLSTMForwardInference( + cuinferHandle_t handle, const cuinferRNNDescriptor_t rnnDesc, + const int seqLength, const cuinferTensorDescriptor_t xDesc, const void *x, + const cuinferTensorDescriptor_t hxDesc, const void *hx, + const cuinferTensorDescriptor_t cxDesc, const void *cx, + const cuinferFilterDescriptor_t wDesc, const void *w, + const cuinferFilterDescriptor_t rDesc, const void *r, + const cuinferTensorDescriptor_t biasDesc, const void *bias, + const cuinferTensorDescriptor_t yDesc, void *y, + const cuinferTensorDescriptor_t hyDesc, void *hy, + const cuinferTensorDescriptor_t cyDesc, void *cy, void *workSpace, + size_t workSpaceSizeInBytes); + +/// @defgroup PageAttention Page Attension + +/// @brief +/// @ingroup PageAttention +/// @param[in] num_seqs +/// @param[in] num_heads +/// @param[in] block_size +/// @param[in] max_context_len +/// @param[out] workspaceSize +/// @return +cuinferStatus_t CUINFERWINAPI cuInferPageAttentionGetWorkspaceV2( + unsigned num_seqs, unsigned num_heads, unsigned block_size, + unsigned max_context_len, size_t *workspaceSize); + +/// @brief +/// @ingroup PageAttention +/// @param[in] num_seqs +/// @param[in] num_heads +/// @param[in] head_size +/// @param[in] block_size +/// @param[in] max_context_len +/// @param[out] workspaceSize +/// @return +cuinferStatus_t CUINFERWINAPI cuInferPageAttentionGetWorkspace( + unsigned num_seqs, unsigned num_heads, unsigned head_size, + unsigned block_size, unsigned max_context_len, size_t *workspaceSize); + +/// @brief +/// @ingroup PageAttention +/// @param[in] handle The libinfer handle. +/// @param[out] out_ptr +/// @param[in] outType +/// @param[in] query_ptr +/// @param[in] queryType +/// @param[in] num_seqs +/// @param[in] num_heads +/// @param[in] head_size +/// @param[in] query_stride +/// @param[in] kv_block_stride +/// @param[in] kv_head_stride +/// @param[in] key_cache_ptr +/// @param[in] keyCacheType +/// @param[in] value_cache_ptr +/// @param[in] valueCacheType +/// @param[in] block_size +/// @param[in] head_mapping +/// @param[in] scale +/// @param[in] block_tables_ptr +/// @param[in] max_num_blocks_per_seq +/// @param[in] context_lens_ptr +/// @param[in] max_context_len +/// @param[in] alibi_slopes_ptr +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[in] alibi_sqrt +/// @return +cuinferStatus_t CUINFERWINAPI cuInferPageAttentionV2( + cuinferHandle_t handle, void *__restrict__ out_ptr, cudaDataType_t outType, + const void *__restrict__ query_ptr, cudaDataType_t queryType, int num_seqs, + int num_heads, int head_size, int query_stride, int kv_block_stride, + int kv_head_stride, const void *__restrict__ key_cache_ptr, + cudaDataType_t keyCacheType, const void *__restrict__ value_cache_ptr, + cudaDataType_t valueCacheType, int block_size, const int *head_mapping, + float scale, const int *__restrict__ block_tables_ptr, + int max_num_blocks_per_seq, const int *__restrict__ context_lens_ptr, + int max_context_len, const float *__restrict__ alibi_slopes_ptr, + void *workspace = nullptr, bool alibi_sqrt = false); + +/// @brief +/// @ingroup PageAttention +/// @param[in] handle The libinfer handle. +/// @param[out] out_ptr +/// @param[in] outType +/// @param[in] query_ptr +/// @param[in] queryType +/// @param[in] num_seqs +/// @param[in] num_heads +/// @param[in] head_size +/// @param[in] query_stride +/// @param[in] kv_block_stride +/// @param[in] kv_head_stride +/// @param[in] key_cache_ptr +/// @param[in] keyCacheType +/// @param[in] value_cache_ptr +/// @param[in] valueCacheType +/// @param[in] block_size +/// @param[in] head_mapping +/// @param[in] scale +/// @param[in] block_tables_ptr +/// @param[in] max_num_blocks_per_seq +/// @param[in] context_lens_ptr +/// @param[in] max_context_len +/// @param[in] alibi_slopes_ptr +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[in] alibi_sqrt +/// @return +cuinferStatus_t CUINFERWINAPI cuInferPageAttention( + cuinferHandle_t handle, void *__restrict__ out_ptr, cudaDataType_t outType, + const void *__restrict__ query_ptr, cudaDataType_t queryType, int num_seqs, + int num_heads, int head_size, int query_stride, int kv_block_stride, + int kv_head_stride, const void *__restrict__ key_cache_ptr, + cudaDataType_t keyCacheType, const void *__restrict__ value_cache_ptr, + cudaDataType_t valueCacheType, int block_size, const int *head_mapping, + float scale, const int *__restrict__ block_tables_ptr, + int max_num_blocks_per_seq, const int *__restrict__ context_lens_ptr, + int max_context_len, const float *__restrict__ alibi_slopes_ptr, + void *workspace = nullptr, bool alibi_sqrt = false); + +/// @brief +/// @ingroup PageAttention +/// @param[in] handle The libinfer handle. +/// @param[out] out_ptr +/// @param[in] outType +/// @param[in] query_ptr +/// @param[in] key_ptr +/// @param[in] value_ptr +/// @param[in] queryType +/// @param[in] num_seqs +/// @param[in] num_heads +/// @param[in] num_kv_heads +/// @param[in] head_size +/// @param[in] query_stride +/// @param[in] key_stride +/// @param[in] value_stride +/// @param[in] kv_block_stride +/// @param[in] kv_head_stride +/// @param[in] key_cache_ptr +/// @param[in] keyCacheType +/// @param[in] value_cache_ptr +/// @param[in] valueCacheType +/// @param[in] block_size +/// @param[in] head_mapping +/// @param[in] scale +/// @param[in] block_tables_ptr +/// @param[in] max_num_blocks_per_seq +/// @param[in] context_lens_ptr +/// @param[in] max_context_len +/// @param[in] alibi_slopes_ptr +/// @param[in] workSpace The workspace pre-allocated. See the corresponding get +/// workspace size helper function. +/// @param[in] alibi_sqrt +/// @return +cuinferStatus_t CUINFERWINAPI cuInferPageAttentionFuse( + cuinferHandle_t handle, void *__restrict__ out_ptr, cudaDataType_t outType, + const void *__restrict__ query_ptr, const void *__restrict__ key_ptr, + const void *__restrict__ value_ptr, cudaDataType_t queryType, int num_seqs, + int num_heads, int num_kv_heads, int head_size, int query_stride, + int key_stride, int value_stride, int kv_block_stride, int kv_head_stride, + const void *__restrict__ key_cache_ptr, cudaDataType_t keyCacheType, + const void *__restrict__ value_cache_ptr, cudaDataType_t valueCacheType, + int block_size, const int *head_mapping, float scale, + const int *__restrict__ block_tables_ptr, int max_num_blocks_per_seq, + const int *__restrict__ context_lens_ptr, int max_context_len, + const float *__restrict__ alibi_slopes_ptr, void *workspace = nullptr, + bool alibi_sqrt = false); + +#if defined(__cplusplus) +} +#endif + +#endif /* CUINFER_H_ */ +#pragma GCC visibility pop diff --git a/cat_files/mma_cu10.h b/cat_files/mma_cu10.h new file mode 100644 index 00000000..b3084819 --- /dev/null +++ b/cat_files/mma_cu10.h @@ -0,0 +1,394 @@ +/*************************************************************************************************** +* Copyright (c) 2021 Iluvatar CoreX. All rights reserved. +* Copyright Declaration: This software, including all of its code and documentation, +* except for the third-party software it contains, is a copyrighted work of Shanghai Iluvatar CoreX +* Semiconductor Co., Ltd. and its affiliates ("Iluvatar CoreX") in accordance with the PRC Copyright +* Law and relevant international treaties, and all rights contained therein are enjoyed by Iluvatar +* CoreX. No user of this software shall have any right, ownership or interest in this software and +* any use of this software shall be in compliance with the terms and conditions of the End User +* License Agreement. + **************************************************************************************************/ + +/*! \file + \brief Matrix Multiply for BigIsland 1st generation +*/ + +#pragma once + +#include "cutlass/arch/mma.h" + +#include "cutlass/layout/matrix.h" +#include "cutlass/gemm/gemm.h" + +//////////////////////////////////////////////////////////////////////////////// + +namespace cutlass { +namespace arch { + +/// BigIsland Tensor Core tile format - EM orinted vector type definitions +/// fp32 +typedef float v4float_t __attribute__((ext_vector_type(4))); +/// s32 +typedef int32_t v4int32_t __attribute__((ext_vector_type(4))); +/// u32 +typedef uint32_t v4uint32_t __attribute__((ext_vector_type(4))); +/// fp16 +typedef uint16_t v4half_t __attribute__((ext_vector_type(4))); +/// bf16 +typedef uint16_t v4bfloat16_t __attribute__((ext_vector_type(4))); +/// s8 +typedef int8_t v4int8_t __attribute__((ext_vector_type(4))); +/// u8 +typedef uint8_t v4uint8_t __attribute__((ext_vector_type(4))); + +//////////////////////////////////////////////////////////////////////////////// +// +// Matrix multiply accumulate 161616 - U32 accumulation +// +//////////////////////////////////////////////////////////////////////////////// + +/// Matrix multiply-add operation: U32 = U8 * U8 + U32 +template +struct Mma< + gemm::GemmShape<16, 16, 16>, + 64, + uint8_t, + LayoutA, + uint8_t, + LayoutB, + uint32_t, + LayoutC, + OpMultiplyAdd> { + + using Shape = gemm::GemmShape<16, 16, 16>; + + using ElementA = uint8_t; + using FragmentA = Array; + + using ElementB = uint8_t; + using FragmentB = Array; + + using ElementC = uint; + using FragmentC = Array; + + using Operator = OpMultiplyAdd; + using ArchTag = arch::Cu10; + + CUTLASS_HOST_DEVICE + void operator()( + FragmentC &d, + FragmentA const &a, + FragmentB const &b, + FragmentC const &c + ) const { +#if CUTLASS_ARCH_CU10_SUPPORTED + v4uint8_t src_A; + v4uint8_t src_B; + v4uint32_t src_C; + v4uint32_t dst_D; + + src_A[0] = a[0]; + src_A[1] = a[1]; + src_A[2] = a[2]; + src_A[3] = a[3]; + src_B[0] = b[0]; + src_B[1] = b[1]; + src_B[2] = b[2]; + src_B[3] = b[3]; + src_C[0] = c[0]; + src_C[1] = c[1]; + src_C[2] = c[2]; + src_C[3] = c[3]; + + dst_D = __ivcorex_matrix_mad_u32x4_u8x4(src_A, src_B, src_C); + + d[0] = dst_D[0]; + d[1] = dst_D[1]; + d[2] = dst_D[2]; + d[3] = dst_D[3]; +#else + assert(0); +#endif + } +}; + +//////////////////////////////////////////////////////////////////////////////// +// +// Matrix multiply accumulate 161616 - S32 accumulation +// +//////////////////////////////////////////////////////////////////////////////// + +/// Matrix multiply-add operation: S32 = S8 * S8 + S32 +template +struct Mma< + gemm::GemmShape<16, 16, 16>, + 64, + int8_t, + LayoutA, + int8_t, + LayoutB, + int, + LayoutC, + OpMultiplyAdd> { + + using Shape = gemm::GemmShape<16, 16, 16>; + + using ElementA = int8_t; + using FragmentA = Array; + + using ElementB = int8_t; + using FragmentB = Array; + + using ElementC = int; + using FragmentC = Array; + + using Operator = OpMultiplyAdd; + using ArchTag = arch::Cu10; + + CUTLASS_HOST_DEVICE + void operator()( + FragmentC &d, + FragmentA const &a, + FragmentB const &b, + FragmentC const &c + ) const { +#if CUTLASS_ARCH_CU10_SUPPORTED + v4int8_t src_A; + v4int8_t src_B; + v4int32_t src_C; + v4int32_t dst_D; + + src_A[0] = a[0]; + src_A[1] = a[1]; + src_A[2] = a[2]; + src_A[3] = a[3]; + src_B[0] = b[0]; + src_B[1] = b[1]; + src_B[2] = b[2]; + src_B[3] = b[3]; + src_C[0] = c[0]; + src_C[1] = c[1]; + src_C[2] = c[2]; + src_C[3] = c[3]; + + dst_D = __ivcorex_matrix_mad_i32x4_i8x4(src_A, src_B, src_C); + + d[0] = dst_D[0]; + d[1] = dst_D[1]; + d[2] = dst_D[2]; + d[3] = dst_D[3]; +#else + assert(0); +#endif + } +}; + +//////////////////////////////////////////////////////////////////////////////// +// +// Matrix multiply accumulate 161616 - FP32 accumulation +// +//////////////////////////////////////////////////////////////////////////////// + +/// Matrix multiply-add operation: FP32 = FP16 * FP16 + FP32 +template +struct Mma< + gemm::GemmShape<16, 16, 16>, + 64, + cutlass::half_t, + LayoutA, + cutlass::half_t, + LayoutB, + float, + LayoutC, + OpMultiplyAdd> { + + using Shape = gemm::GemmShape<16, 16, 16>; + + using ElementA = cutlass::half_t; + using FragmentA = Array; + + using ElementB = cutlass::half_t; + using FragmentB = Array; + + using ElementC = float; + using FragmentC = Array; + + using Operator = OpMultiplyAdd; + using ArchTag = arch::Cu10; + + CUTLASS_HOST_DEVICE + void operator()( + FragmentC &d, + FragmentA const &a, + FragmentB const &b, + FragmentC const &c + ) const { + v4half_t src_A; + v4half_t src_B; + v4float_t src_C; + v4float_t dst_D; + + src_A[0] = half_t(a[0]).storage; + src_A[1] = half_t(a[1]).storage; + src_A[2] = half_t(a[2]).storage; + src_A[3] = half_t(a[3]).storage; + src_B[0] = half_t(b[0]).storage; + src_B[1] = half_t(b[1]).storage; + src_B[2] = half_t(b[2]).storage; + src_B[3] = half_t(b[3]).storage; + src_C[0] = c[0]; + src_C[1] = c[1]; + src_C[2] = c[2]; + src_C[3] = c[3]; + + dst_D = __ivcorex_matrix_mad_f32x4_f16x4(src_A, src_B, src_C); +#if 0 +if(threadIdx.x == 0) +printf( + ">>> After\n" + "A: %f, %f, %f, %f\n" + "B: %f, %f, %f, %f\n" + "C: %f, %f, %f, %f\n" + "D: %f, %f, %f, %f\n\n", + float(a[0]), float(a[1]), float(a[2]), float(a[3]), + float(b[0]), float(b[1]), float(b[2]), float(b[3]), + float(src_C[0]), float(src_C[1]), float(src_C[2]), float(src_C[3]), + float(d[0]), float(d[1]), float(d[2]), float(d[3]) +); +#endif + + d[0] = dst_D[0]; + d[1] = dst_D[1]; + d[2] = dst_D[2]; + d[3] = dst_D[3]; + + } +}; + +/// Matrix multiply-add operation: FP32 = BF16 * BF16 + FP32 +template +struct Mma< + gemm::GemmShape<16, 16, 16>, + 64, + bfloat16_t, + LayoutA, + bfloat16_t, + LayoutB, + float, + LayoutC, + OpMultiplyAdd> { + + using Shape = gemm::GemmShape<16, 16, 16>; + + using ElementA = bfloat16_t; + using FragmentA = Array; + + using ElementB = bfloat16_t; + using FragmentB = Array; + + using ElementC = float; + using FragmentC = Array; + + using Operator = OpMultiplyAdd; + using ArchTag = arch::Cu10; + + CUTLASS_HOST_DEVICE + void operator()( + FragmentC &d, + FragmentA const &a, + FragmentB const &b, + FragmentC const &c + ) const { + v4bfloat16_t src_A; + v4bfloat16_t src_B; + v4float_t src_C; + v4float_t dst_D; + + src_A[0] = bfloat16_t(a[0]).storage; + src_A[1] = bfloat16_t(a[1]).storage; + src_A[2] = bfloat16_t(a[2]).storage; + src_A[3] = bfloat16_t(a[3]).storage; + src_B[0] = bfloat16_t(b[0]).storage; + src_B[1] = bfloat16_t(b[1]).storage; + src_B[2] = bfloat16_t(b[2]).storage; + src_B[3] = bfloat16_t(b[3]).storage; + src_C[0] = c[0]; + src_C[1] = c[1]; + src_C[2] = c[2]; + src_C[3] = c[3]; +#if __clang_major__ >= 16 + dst_D = __ivcorex_matrix_mad_f32x4_bf16x4(src_A, src_B, src_C); +#else + dst_D = __ivcorex_matrix_mad_f32_bf16(src_A, src_B, src_C); +#endif + d[0] = dst_D[0]; + d[1] = dst_D[1]; + d[2] = dst_D[2]; + d[3] = dst_D[3]; + } +}; + +/// Matrix multiply-add operation: FP32 = FP32 * FP32 + FP32 +template +struct Mma< + gemm::GemmShape<16,16,16>, + 64, + float, + LayoutA, + float, + LayoutB, + float, + LayoutC, + OpMultiplyAdd> { + + using Shape = gemm::GemmShape<16,16,16>; + + using ElementA = float; + using FragmentA = Array; + + using ElementB = float; + using FragmentB = Array; + + using ElementC = float; + using FragmentC = Array; + + using Operator = OpMultiplyAdd; + using ArchTag = arch::Cu10; + + CUTLASS_HOST_DEVICE + void operator()( + FragmentC &d, + FragmentA const &a, + FragmentB const &b, + FragmentC const &c + ) const { + v4float_t src_A; + v4float_t src_B; + v4float_t src_C; + v4float_t dst_D; + + src_A[0] = a[0]; + src_A[1] = a[1]; + src_A[2] = a[2]; + src_A[3] = a[3]; + src_B[0] = b[0]; + src_B[1] = b[1]; + src_B[2] = b[2]; + src_B[3] = b[3]; + src_C[0] = c[0]; + src_C[1] = c[1]; + src_C[2] = c[2]; + src_C[3] = c[3]; + + dst_D = __ivcorex_matrix_mad_f32x4_f32x4(src_A, src_B, src_C); + + d[0] = dst_D[0]; + d[1] = dst_D[1]; + d[2] = dst_D[2]; + d[3] = dst_D[3]; + } +}; + +//////////////////////////////////////////////////////////////////////////////// +} +} diff --git a/cat_files/mma_tensor_op.h b/cat_files/mma_tensor_op.h new file mode 100644 index 00000000..2f9e8705 --- /dev/null +++ b/cat_files/mma_tensor_op.h @@ -0,0 +1,382 @@ +/*************************************************************************************************** + * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ + +/*************************************************************************************************** +* Copyright (c) 2021 Iluvatar CoreX. All rights reserved. +* Copyright Declaration: This software, including all of its code and documentation, +* except for the third-party software it contains, is a copyrighted work of Shanghai Iluvatar CoreX +* Semiconductor Co., Ltd. and its affiliates ("Iluvatar CoreX") in accordance with the PRC Copyright +* Law and relevant international treaties, and all rights contained therein are enjoyed by Iluvatar +* CoreX. No user of this software shall have any right, ownership or interest in this software and +* any use of this software shall be in compliance with the terms and conditions of the End User +* License Agreement. + **************************************************************************************************/ + +/*! \file + \brief Templates implementing warp-level matrix multiply-accumulate operations targeting + Tensor Cores. +*/ + +#pragma once + +#include "cutlass/cutlass.h" +#include "cutlass/array.h" +#include "cutlass/platform/platform.h" + +#include "cutlass/numeric_conversion.h" +#include "cutlass/numeric_types.h" +#include "cutlass/matrix_shape.h" + +#include "cutlass/arch/mma.h" + +#include "cutlass/gemm/gemm.h" +#include "cutlass/gemm/warp/mma.h" + +#include "cutlass/gemm/warp/mma_tensor_op_policy.h" +#include "cutlass/gemm/warp/mma_tensor_op_tile_iterator.h" + +///////////////////////////////////////////////////////////////////////////////////////////////// + +namespace cutlass { +namespace gemm { +namespace warp { + +///////////////////////////////////////////////////////////////////////////////////////////////// + +namespace detail { + +template +struct ConvertAndPack { + + using Converter = NumericArrayConverter; + + CUTLASS_HOST_DEVICE + Array operator()(Array const &source) { + Converter converter; + + return converter(source); + } +}; + +template +struct ConvertAndPack { + + CUTLASS_HOST_DEVICE + Array operator()(Array const &source) { + return source; + } +}; + +template +struct ConvertAndPack { + + using Converter = NumericArrayConverter; + + CUTLASS_HOST_DEVICE + Array operator()(Array const &source) { + Converter converter; + + Array tmp; + + CUTLASS_PRAGMA_UNROLL + for (int i = 0; i < N; ++i) { + int idx = (((i << 1) & 2) | ((i >> 1) & 1) | (i & 0xfffffffc)); + tmp[i] = source[idx]; + } + + return converter(tmp); + } +}; + +template +struct ConvertAndPack { + + using Converter = NumericArrayConverter; + + CUTLASS_HOST_DEVICE + Array operator()(Array const &source) { + Converter converter; + + Array tmp; + + CUTLASS_PRAGMA_UNROLL + for (int i = 0; i < N; ++i) { + int idx = (((i << 1) & 2) | ((i >> 1) & 1) | (i & 0xfffffffc)); + tmp[i] = source[idx]; + } + + return converter(tmp); + } +}; + +///////////////////////////////////////////////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace detail + +///////////////////////////////////////////////////////////////////////////////////////////////// + +/// Structure to compute the matrix product targeting CUDA cores and SIMT math instructions. +template < + /// Size of the Gemm problem - concept: gemm::GemmShape<> + typename Shape_, + /// Data type of A elements + typename ElementA_, + /// Layout of A matrix (concept: MatrixLayout) + typename LayoutA_, + /// Data type of B elements + typename ElementB_, + /// Layout of B matrix (concept: MatrixLayout) + typename LayoutB_, + /// Element type of C matrix + typename ElementC_, + /// Layout of C matrix (concept: MatrixLayout) + typename LayoutC_, + /// Policy describing warp-level MmaTensorOp (concept: MmaTensorOp policy) + typename Policy_, + /// Number of partitions along K dimension + int PartitionsK_ = 1, + /// Store the accumulators in row major or column major. + /// Iluvatar Tensor Core always stores accumulators in row major + bool AccumulatorsInRowMajor = true, + /// Used for partial specialization + typename Enable = bool +> +class MmaTensorOp { +public: + /// Shape of warp-level matrix operation (concept: GemmShape) + using Shape = Shape_; + + /// Data type of multiplicand A + using ElementA = ElementA_; + + /// Layout of multiplicand A + using LayoutA = LayoutA_; + + /// Data type of multiplicand B + using ElementB = ElementB_; + + /// Layout of multiplicand B + using LayoutB = LayoutB_; + + /// Data type of accumulator matrix C + using ElementC = ElementC_; + + /// Layout of accumulator matrix C + using LayoutC = LayoutC_; + + /// Shape of the warp in units of thread (concept: MmaLanePolicySimt) + using Policy = Policy_; + + /// Underlying matrix multiply operator (concept: arch::Mma) + using ArchMmaOperator = typename Policy::Operator; + + /// Architecture tag from underlying instruction + using ArchTag = typename ArchMmaOperator::ArchTag; + + /// Indicates class of matrix operator + using OperatorClass = arch::OpClassTensorOp; + + /// Shape of underlying instruction + using InstructionShape = typename ArchMmaOperator::Shape; + + /// Complex transform on A operand + static ComplexTransform const kTransformA = ComplexTransform::kNone; + + /// Complex transform on B operand + static ComplexTransform const kTransformB = ComplexTransform::kNone; + + /// Number of threads participating in warp-level matrix product + static int const kThreadCount = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK_; + +public: + /// FIXME(Peter Han): workaround to adapt to simt epilogue, need to remove + struct ThreadMma { + using ElementC = ElementC; + }; + + /// Iterates over the A operand in memory + using IteratorA = MmaTensorOpMultiplicandTileIterator< + MatrixShape, + Operand::kA, + ElementA, + LayoutA, + InstructionShape, + kThreadCount, + kPartitionsK>; + + /// Storage for A tile + using FragmentA = typename IteratorA::Fragment; + + /// Storage for transformed A tile + using TransformedFragmentA = + Array; + + /// Iterates over the B operand in memory + using IteratorB = MmaTensorOpMultiplicandTileIterator< + MatrixShape, + Operand::kB, + ElementB, + LayoutB, + InstructionShape, + kThreadCount, + kPartitionsK>; + + /// Storage for B tile + using FragmentB = typename IteratorB::Fragment; + + /// Storage for transformed B tile + using TransformedFragmentB = + Array; + + /// Iterates over the C operand in memory + using IteratorC = MmaTensorOpAccumulatorTileIterator< + MatrixShape, + ElementC, + LayoutC, + InstructionShape>; + + /// Storage for C tile + using FragmentC = typename IteratorC::Fragment; + + static_assert( + !(Shape::kM % Policy::Operator::Shape::kM) && + !(Shape::kN % Policy::Operator::Shape::kN) && + !(Shape::kK % Policy::Operator::Shape::kK), + "Shape of warp-level Mma must be divisible by operator shape."); + + using MmaIterations = gemm::GemmShape< + (Shape::kM + ArchMmaOperator::Shape::kM - 1) / ArchMmaOperator::Shape::kM, + (Shape::kN + ArchMmaOperator::Shape::kN - 1) / ArchMmaOperator::Shape::kN, + InstructionShape::kK / Policy::Operator::Shape::kK + >; + +public: + + /// Underlying matrix multiply operator (concept: arch::Mma) + ArchMmaOperator mma; + +public: + + // + // Methods + // + + /// Ctor + CUTLASS_DEVICE + MmaTensorOp() {} + + /// Performs a warp-level matrix multiply-accumulate operation + CUTLASS_DEVICE + void operator()( + FragmentC &D, + TransformedFragmentA const &A, + TransformedFragmentB const &B, + FragmentC const &C + ) const { + + using MmaOperandA = typename ArchMmaOperator::FragmentA; + using MmaOperandB = typename ArchMmaOperator::FragmentB; + using MmaOperandC = typename ArchMmaOperator::FragmentC; + + D = C; + + MmaOperandA const *ptr_A = reinterpret_cast(&A); + MmaOperandB const *ptr_B = reinterpret_cast(&B); + MmaOperandC *ptr_D = reinterpret_cast(&D); + + // Serpentine visitation order maximizing reuse of Rb + CUTLASS_PRAGMA_UNROLL + for (int k = 0; k < MmaIterations::kK; ++k) { + CUTLASS_PRAGMA_UNROLL + for (int m = 0; m < MmaIterations::kM; ++m) { + CUTLASS_PRAGMA_UNROLL + for (int n = 0; n < MmaIterations::kN; ++n) { + int n_serpentine = ((m % 2) ? (MmaIterations::kN - 1 - n) : n); + + /// assume A is column-major in VRF, B is row-major in VRF + if(AccumulatorsInRowMajor) { + mma( + ptr_D[n_serpentine + m * MmaIterations::kN], + ptr_A[m + k * MmaIterations::kM], + ptr_B[n_serpentine + k * MmaIterations::kN], + ptr_D[n_serpentine + m * MmaIterations::kN]); + } else { + mma( + ptr_D[m + n_serpentine * MmaIterations::kM], + ptr_A[m + k * MmaIterations::kM], + ptr_B[n_serpentine + k * MmaIterations::kN], + ptr_D[m + n_serpentine * MmaIterations::kM]); + } + } + } + } + } + + /// Transform the mma operands to the required types + CUTLASS_DEVICE + void transform(TransformedFragmentA &dst_A, TransformedFragmentB &dst_B, + FragmentA const &A, FragmentB const &B) const { + + // + // Define conversions from source type to instruction type + // + FloatRoundStyle const kRoundA = + PreferredRoundingMode::kRound; + FloatRoundStyle const kRoundB = + PreferredRoundingMode::kRound; + detail::ConvertAndPack + convert_A; + NumericArrayConverter + convert_B; + Array const *ptr_A = + reinterpret_cast const *>(&A); + Array * + ptr_dst_A = reinterpret_cast *>(&dst_A); + + dst_B = convert_B(B); + + ptr_dst_A[0] = convert_A(ptr_A[0]); + ptr_dst_A[1] = convert_A(ptr_A[1]); + } +}; + +///////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace warp +} // namespace gemm +} // namespace cutlass + +///////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/cat_files/mma_tensor_op_policy.h b/cat_files/mma_tensor_op_policy.h new file mode 100644 index 00000000..4538c7fd --- /dev/null +++ b/cat_files/mma_tensor_op_policy.h @@ -0,0 +1,71 @@ +/*************************************************************************************************** + * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ + +/*************************************************************************************************** +* Copyright (c) 2021 Iluvatar CoreX. All rights reserved. +* Copyright Declaration: This software, including all of its code and documentation, +* except for the third-party software it contains, is a copyrighted work of Shanghai Iluvatar CoreX +* Semiconductor Co., Ltd. and its affiliates ("Iluvatar CoreX") in accordance with the PRC Copyright +* Law and relevant international treaties, and all rights contained therein are enjoyed by Iluvatar +* CoreX. No user of this software shall have any right, ownership or interest in this software and +* any use of this software shall be in compliance with the terms and conditions of the End User +* License Agreement. + **************************************************************************************************/ + +/*! \file + \brief Policy describing implementation details of warp-level GEMM targeting Tensor Cores. +*/ + +#pragma once + +#include "cutlass/cutlass.h" +#include "cutlass/matrix_shape.h" +#include "cutlass/gemm/gemm.h" + +///////////////////////////////////////////////////////////////////////////////////////////////// + +namespace cutlass { +namespace gemm { +namespace warp { + +///////////////////////////////////////////////////////////////////////////////////////////////// + +/// Policy +template < + typename Operator_, ///< hardware instruction(s) performing TensorOp (concept: arch::Mma) + typename OpDelta_ ///< distance between operations (concept: MatrixShape) +> +struct MmaTensorOpPolicy { + + using Operator = Operator_; ///< hardware instruction(s) performing TensorOp (concept: arch::Mma) + using OpDelta = OpDelta_; ///< distance between operations (concept: MatrixShape) + using MmaShape = typename Operator::Shape; +}; + +///////////////////////////////////////////////////////////////////////////////////////////////// + +} // namespace warp +} // namespace gemm +} // namespace cutlass diff --git a/cat_files/mma_tensor_op_tile_iterator.h b/cat_files/mma_tensor_op_tile_iterator.h new file mode 100644 index 00000000..db3f716e --- /dev/null +++ b/cat_files/mma_tensor_op_tile_iterator.h @@ -0,0 +1,5595 @@ +/*************************************************************************************************** + * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************************/ + +/*************************************************************************************************** +* Copyright (c) 2021 Iluvatar CoreX. All rights reserved. +* Copyright Declaration: This software, including all of its code and documentation, +* except for the third-party software it contains, is a copyrighted work of Shanghai Iluvatar CoreX +* Semiconductor Co., Ltd. and its affiliates ("Iluvatar CoreX") in accordance with the PRC Copyright +* Law and relevant international treaties, and all rights contained therein are enjoyed by Iluvatar +* CoreX. No user of this software shall have any right, ownership or interest in this software and +* any use of this software shall be in compliance with the terms and conditions of the End User +* License Agreement. + **************************************************************************************************/ + +/*! \file + \brief Defines iterators used by warp-level matrix multiply operations targeting Tensor Cores. +*/ + +#pragma once + +#include "cutlass/cutlass.h" + +#include "cutlass/array.h" +#include "cutlass/numeric_types.h" +#include "cutlass/tensor_ref.h" +#include "cutlass/matrix_shape.h" + +#include "cutlass/gemm/gemm.h" + +#include "cutlass/layout/matrix.h" +#include "cutlass/layout/tensor.h" +#include "cutlass/layout/pitch_linear.h" +#include "cutlass/layout/tensor_op_multiplicand.h" + +//////////////////////////////////////////////////////////////////////////////// + +namespace cutlass { +namespace gemm { +namespace warp { + +//////////////////////////////////////////////////////////////////////////////// + +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Operand identity + Operand Operand, + /// Data type of elements + typename Element_, + /// Layout of operand + typename Layout_, + /// Shape of one matrix production operation (concept: GemmShape) + typename InstructionShape_, + /// Number of threads participating in one matrix operation + int Threads, + /// Number of partitions along K dimension + int PartitionsK = 1> +class MmaTensorOpMultiplicandTileIterator; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for row-major A operands of 4bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kA, + Element_, + layout::TensorOpMultiplicand<32, layout::RowMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpMultiplicand<32, layout::RowMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert(Shape::kColumn == InstructionShape::kK, "Shape::kColumn must equal InstructionShape::kK"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape; + }; + + /// Access type + using AccessType = Array; + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Offset in units of element + int offset_ = 0; + + /// Pointers holding same stride + Element* pointers_[4]; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data() + ref.offset({lane_id / 16, lane_id % 16}); + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + pointers_[i] = ptr + i * 64; + } + } + + /// Adds a pointer offset to interal pointer(s) to advance through memory + /// So far, isn't used anywhere. Offset must be muliple of Layout::TileShape + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_pointer_offset(LongIndex offset) { + offset_ += int(offset); + return *this; + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + offset_ += tile_offset.row() * Shape::kRow * stride_ + + tile_offset.column() * (Shape::kColumn / layout::EmShape::kColumn) * layout::EmShape::kCount; + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({0, 1}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({0, -1}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int idx = 0; + int offset = ptr_offset + offset_; + + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + dst_ptr[idx] = *reinterpret_cast(pointers_[i] + offset); + ++idx; + } + offset += stride_ * 16; + } + } + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for column-major A operands of 4bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kA, + Element_, + layout::TensorOpMultiplicand<32, layout::ColumnMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpMultiplicand<32, layout::ColumnMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert(Shape::kColumn == InstructionShape::kK, "Shape::kColumn must equal InstructionShape::kK"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape; + }; + + /// Access type + using AccessType = Array; + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Offset in units of element + int offset_ = 0; + + /// Pointers holding same stride + Element* pointers_[4]; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + int const r = lane_id / 16; + int const c = lane_id % 16; + Element* ptr = ref.data(); + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + pointers_[i] = ptr + ref.offset({r + i * 4, c}); + } + } + + /// Adds a pointer offset to interal pointer(s) to advance through memory + /// So far, isn't used anywhere. Offset must be muliple of Layout::TileShape + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_pointer_offset(LongIndex offset) { + offset_ += int(offset); + return *this; + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + offset_ += tile_offset.column() * Shape::kColumn * stride_ + + tile_offset.row() * (Shape::kRow / layout::EmShape::kRow) * layout::EmShape::kCount; + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({0, 1}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({0, -1}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int idx = 0; + int offset = ptr_offset + offset_; + + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + dst_ptr[idx] = *reinterpret_cast(pointers_[i] + offset); + ++idx; + } + offset += layout::EmShape::kCount; + } + } + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for row-major B operands of 4bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kB, + Element_, + layout::TensorOpMultiplicand<32, layout::RowMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpMultiplicand<32, layout::RowMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert(Shape::kRow == InstructionShape::kK, "Shape::kRow must equal InstructionShape::kK"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape<1, Shape::kColumn / InstructionShape::kN>; + }; + + /// Access type + using AccessType = Array; + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Offset in units of element + int offset_ = 0; + + /// Pointers holding same stride + Element* pointers_[4]; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); + int const r = lane_id / 16; + int const c = lane_id % 16; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + pointers_[i] = ptr + ref.offset({r + i * 4, c}); + } + } + + /// Adds a pointer offset to interal pointer(s) to advance through memory + /// So far, isn't used anywhere. Offset must be muliple of Layout::TileShape + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_pointer_offset(LongIndex offset) { + offset_ += int(offset); + return *this; + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + offset_ += tile_offset.row() * Shape::kRow * stride_ + + tile_offset.column() * (Shape::kColumn / layout::EmShape::kColumn) * layout::EmShape::kCount; + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({1, 0}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({-1, 0}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int idx = 0; + int offset = ptr_offset + offset_; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + dst_ptr[idx] = *reinterpret_cast(pointers_[i] + offset); + ++idx; + } + offset += layout::EmShape::kCount; + } + } + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for column-major B operands of 4bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kB, + Element_, + layout::TensorOpMultiplicand<32, layout::ColumnMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kB; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpMultiplicand<32, layout::ColumnMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert(Shape::kRow == InstructionShape::kK, "Shape::kRow must equal InstructionShape::kK"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape<1, Shape::kColumn / InstructionShape::kN>; + }; + + /// Access type + using AccessType = Array; + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Offset in units of element + int offset_ = 0; + + /// Pointers holding same stride + Element* pointers_[4]; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); + int const r = lane_id / 16; + int const c = lane_id % 16; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + pointers_[i] = ptr + ref.offset({r + i * 4, c}); + } + } + + /// Adds a pointer offset to interal pointer(s) to advance through memory + /// So far, isn't used anywhere. Offset must be muliple of Layout::TileShape + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_pointer_offset(LongIndex offset) { + offset_ += int(offset); + return *this; + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + offset_ += tile_offset.column() * Shape::kColumn * stride_ + + tile_offset.row() * (Shape::kRow / layout::EmShape::kRow) * layout::EmShape::kCount; + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({1, 0}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({-1, 0}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int idx = 0; + int offset = ptr_offset + offset_; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + dst_ptr[idx] = *reinterpret_cast(pointers_[i] + offset); + idx++; + } + offset += stride_ * 16; + } + } + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +/// 2bytes (half/bhalf) /// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for row-major A operands of 2bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kA, + Element_, + layout::TensorOpMultiplicand<16, layout::RowMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpMultiplicand<16, layout::RowMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert(Shape::kColumn == InstructionShape::kK, "Shape::kColumn must equal InstructionShape::kK"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape; + }; + + /// Access type + using AccessType = Array; + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride + Element* pointers_[2][2]; + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); + int r = (lane_id / 16) * 2; + int c = lane_id % 16; + + pointers_[0][0] = ptr + ref.offset({r, c}); + pointers_[0][1] = ptr + ref.offset({r + 8, c}); + pointers_[1][0] = ptr + ref.offset({r, c + 16}); + pointers_[1][1] = ptr + ref.offset({r + 8, c + 16}); + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row() * (Shape::kRow / layout::EmShape::kRow); + iteration_column_ += tile_offset.column(); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({0, 1}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({0, -1}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const col_offset = (iteration_column_ / 2) * layout::EmShape::kCount * 2 + ptr_offset; + int idx = 0; + + if(iteration_column_ & 1) { + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kRow * stride_; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 2; ++i) { + dst_ptr[idx] = *reinterpret_cast( + pointers_[1][i] + col_offset + row_offset); + ++idx; + } + } + } else { + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kRow * stride_; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 2; ++i) { + dst_ptr[idx] = *reinterpret_cast( + pointers_[0][i] + col_offset + row_offset); + ++idx; + } + } + } + } + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for column-major A operands of 2bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kA, + Element_, + layout::TensorOpMultiplicand<16, layout::ColumnMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpMultiplicand<16, layout::ColumnMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape; + }; + + /// Access type + using AccessType = Array; + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride + Element* pointers_[2][2]; + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); + int r = (lane_id / 16) * 2; + int c = lane_id % 16; + + pointers_[0][0] = ptr + ref.offset({r, c}); + pointers_[0][1] = ptr + ref.offset({r + 8, c}); + pointers_[1][0] = ptr + ref.offset({r + 16, c}); + pointers_[1][1] = ptr + ref.offset({r + 24, c}); + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row() * (Shape::kRow / layout::EmShape::kRow); + iteration_column_ += tile_offset.column(); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({0, 1}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({0, -1}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int idx = 0; + int const col_offset = iteration_column_ * layout::EmShape::kColumn * stride_ + ptr_offset; + + if(iteration_row_ & 1) { + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = ((iteration_row_ + r) / 2) * layout::EmShape::kCount * 2; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 2; ++i) { + dst_ptr[idx] = *reinterpret_cast( + pointers_[(r + 1) & 1][i] + col_offset + row_offset); + ++idx; + } + } + } else { + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = ((iteration_row_ + r) / 2) * layout::EmShape::kCount * 2; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 2; ++i) { + dst_ptr[idx] = *reinterpret_cast( + pointers_[r & 1][i] + col_offset + row_offset); + ++idx; + } + } + } + } + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for row-major B operands of 2bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kB, + Element_, + layout::TensorOpMultiplicand<16, layout::RowMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kB; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpMultiplicand<16, layout::RowMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape<1, Shape::kColumn / InstructionShape::kN>; + }; + + /// Access type + using AccessType = Array; + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride + Element* pointers_[2][2]; + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + int r = (lane_id / 16) * 2; + int c = lane_id % 16; + + pointers_[0][0] = ref.data() + ref.offset({r, c}); + pointers_[0][1] = ref.data() + ref.offset({r + 8, c}); + pointers_[1][0] = ref.data() + ref.offset({r, c + 16}); + pointers_[1][1] = ref.data() + ref.offset({r + 8, c + 16}); + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row(); + iteration_column_ += tile_offset.column() * (Shape::kColumn / layout::EmShape::kColumn); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({1, 0}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({-1, 0}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int idx = 0; + int const row_offset = iteration_row_ * layout::EmShape::kRow * stride_ + ptr_offset; + + if(iteration_column_ & 1) { + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = ((iteration_column_ + c) / 2) * layout::EmShape::kCount * 2; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 2; ++i) { + dst_ptr[idx] = *reinterpret_cast(pointers_[(c + 1)& 1][i] + col_offset + row_offset); + ++idx; + } + } + } else { + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = ((iteration_column_ + c) / 2) * layout::EmShape::kCount * 2; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 2; ++i) { + dst_ptr[idx] = *reinterpret_cast(pointers_[c & 1][i] + col_offset + row_offset); + ++idx; + } + } + } + } + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for column-major B operands of 2bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kB, + Element_, + layout::TensorOpMultiplicand<16, layout::ColumnMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kB; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpMultiplicand<16, layout::ColumnMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape<1, Shape::kColumn / InstructionShape::kN>; + }; + + /// Access type + using AccessType = Array; + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride + Element* pointers_[2][2]; + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); + int r = (lane_id / 16) * 2; + int c = lane_id % 16; + + pointers_[0][0] = ptr + int(ref.offset({r, c})); + pointers_[0][1] = ptr + int(ref.offset({r + 8, c})); + pointers_[1][0] = ptr + int(ref.offset({r + 16, c})); + pointers_[1][1] = ptr + int(ref.offset({r + 24, c})); + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row(); + iteration_column_ += tile_offset.column() * (Shape::kColumn / layout::EmShape::kColumn); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({1, 0}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({-1, 0}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const row_offset = (iteration_row_ / 2) * layout::EmShape::kCount * 2 + ptr_offset; + int idx = 0; + + if(iteration_row_ & 1) { + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kColumn * stride_; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 2; ++i) { + dst_ptr[idx] = *reinterpret_cast( + pointers_[1][i] + row_offset + col_offset); + idx++; + } + } + } else { + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kColumn * stride_; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 2; ++i) { + dst_ptr[idx] = *reinterpret_cast( + pointers_[0][i] + row_offset + col_offset); + idx++; + } + } + } + } + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +/// 1byte (int8/uint8) /// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for row-major A operands of 1byte width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kA, + Element_, + layout::TensorOpMultiplicand<8, layout::RowMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpMultiplicand<8, layout::RowMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert(Shape::kColumn == InstructionShape::kK, "Shape::kColumn must equal InstructionShape::kK"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape; + }; + + /// Access type + using AccessType = Array; + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride + Element* pointers_[4]; + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); + int r = (lane_id / 16) * 4; + int c = lane_id % 16; + + pointers_[0] = ptr + ref.offset({r, c}); + pointers_[1] = ptr + ref.offset({r, c + 16}); + pointers_[2] = ptr + ref.offset({r, c + 32}); + pointers_[3] = ptr + ref.offset({r, c + 48}); + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row() * (Shape::kRow / layout::EmShape::kRow); + iteration_column_ += tile_offset.column(); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({0, 1}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({0, -1}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const col_offset = (iteration_column_ / 4) * layout::EmShape::kCount * 4 + ptr_offset; + int idx = 0; + + if((iteration_column_ & 3) == 3) { + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kRow * stride_; + + dst_ptr[idx] = *reinterpret_cast( + pointers_[3] + col_offset + row_offset); + ++idx; + } + } else if((iteration_column_ & 3) == 2) { + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kRow * stride_; + + dst_ptr[idx] = *reinterpret_cast( + pointers_[2] + col_offset + row_offset); + ++idx; + } + } else if((iteration_column_ & 3) == 1) { + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kRow * stride_; + + dst_ptr[idx] = *reinterpret_cast( + pointers_[1] + col_offset + row_offset); + ++idx; + } + } else { + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kRow * stride_; + + dst_ptr[idx] = *reinterpret_cast( + pointers_[0] + col_offset + row_offset); + ++idx; + } + } + } + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for column-major A operands of 1byte width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kA, + Element_, + layout::TensorOpMultiplicand<8, layout::ColumnMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpMultiplicand<8, layout::ColumnMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape; + }; + + /// Access type + using AccessType = Array; + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride + Element* pointers_[4]; + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); + int r = (lane_id / 16) * 4; + int c = lane_id % 16; + + pointers_[0] = ptr + ref.offset({r, c}); + pointers_[1] = ptr + ref.offset({r + 16, c}); + pointers_[2] = ptr + ref.offset({r + 32, c}); + pointers_[3] = ptr + ref.offset({r + 48, c}); + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row() * (Shape::kRow / layout::EmShape::kRow); + iteration_column_ += tile_offset.column(); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({0, 1}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({0, -1}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int idx = 0; + int const col_offset = iteration_column_ * layout::EmShape::kColumn * stride_ + ptr_offset; + + if((iteration_row_ & 3) == 3) { + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = ((iteration_row_ + r) / 4) * layout::EmShape::kCount * 4; + + dst_ptr[idx] = *reinterpret_cast( + pointers_[(r + 3) & 3] + col_offset + row_offset); + ++idx; + } + } else if((iteration_row_ & 3) == 2) { + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = ((iteration_row_ + r) / 4) * layout::EmShape::kCount * 4; + + dst_ptr[idx] = *reinterpret_cast( + pointers_[(r + 2) & 3] + col_offset + row_offset); + ++idx; + } + } else if((iteration_row_ & 3) == 1) { + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = ((iteration_row_ + r) / 4) * layout::EmShape::kCount * 4; + + dst_ptr[idx] = *reinterpret_cast( + pointers_[(r + 1) & 3] + col_offset + row_offset); + ++idx; + } + } else { + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = ((iteration_row_ + r) / 4) * layout::EmShape::kCount * 4; + + dst_ptr[idx] = *reinterpret_cast( + pointers_[r & 3] + col_offset + row_offset); + ++idx; + } + } + } + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for row-major B operands of 1byte width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kB, + Element_, + layout::TensorOpMultiplicand<8, layout::RowMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kB; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpMultiplicand<8, layout::RowMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape<1, Shape::kColumn / InstructionShape::kN>; + }; + + /// Access type + using AccessType = Array; + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride + Element* pointers_[4]; + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + int r = (lane_id / 16) * 4; + int c = lane_id % 16; + + pointers_[0] = ref.data() + ref.offset({r, c}); + pointers_[1] = ref.data() + ref.offset({r, c + 16}); + pointers_[2] = ref.data() + ref.offset({r, c + 32}); + pointers_[3] = ref.data() + ref.offset({r, c + 48}); + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row(); + iteration_column_ += tile_offset.column() * (Shape::kColumn / layout::EmShape::kColumn); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({1, 0}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({-1, 0}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int idx = 0; + int const row_offset = iteration_row_ * layout::EmShape::kRow * stride_ + ptr_offset; + + if((iteration_column_ & 3) == 3) { + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = ((iteration_column_ + c) / 4) * layout::EmShape::kCount * 4; + + dst_ptr[idx] = *reinterpret_cast(pointers_[(c + 3) & 3] + col_offset + row_offset); + ++idx; + } + } else if((iteration_column_ & 3) == 2) { + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = ((iteration_column_ + c) / 4) * layout::EmShape::kCount * 4; + + dst_ptr[idx] = *reinterpret_cast(pointers_[(c + 2) & 3] + col_offset + row_offset); + ++idx; + } + } else if((iteration_column_ & 3) == 1) { + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = ((iteration_column_ + c) / 4) * layout::EmShape::kCount * 4; + + dst_ptr[idx] = *reinterpret_cast(pointers_[(c + 1) & 3] + col_offset + row_offset); + ++idx; + } + } else { + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = ((iteration_column_ + c) / 4) * layout::EmShape::kCount * 4; + + dst_ptr[idx] = *reinterpret_cast(pointers_[c & 3] + col_offset + row_offset); + ++idx; + } + } + } + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for column-major B operands of 1byte width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kB, + Element_, + layout::TensorOpMultiplicand<8, layout::ColumnMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kB; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpMultiplicand<8, layout::ColumnMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape<1, Shape::kColumn / InstructionShape::kN>; + }; + + /// Access type + using AccessType = Array; + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride + Element* pointers_[4]; + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); + int r = (lane_id / 16) * 4; + int c = lane_id % 16; + + pointers_[0] = ptr + ref.offset({r, c}); + pointers_[1] = ptr + ref.offset({r + 16, c}); + pointers_[2] = ptr + ref.offset({r + 32, c}); + pointers_[3] = ptr + ref.offset({r + 48, c}); + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row(); + iteration_column_ += tile_offset.column() * (Shape::kColumn / layout::EmShape::kColumn); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({1, 0}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({-1, 0}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const row_offset = (iteration_row_ / 4) * layout::EmShape::kCount * 4 + ptr_offset; + int idx = 0; + + if((iteration_row_ & 3) == 3) { + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kColumn * stride_; + + dst_ptr[idx] = *reinterpret_cast( + pointers_[3] + row_offset + col_offset); + idx++; + } + } else if((iteration_row_ & 3) == 2) { + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kColumn * stride_; + + dst_ptr[idx] = *reinterpret_cast( + pointers_[2] + row_offset + col_offset); + idx++; + } + } else if((iteration_row_ & 3) == 1) { + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kColumn * stride_; + + dst_ptr[idx] = *reinterpret_cast( + pointers_[1] + row_offset + col_offset); + idx++; + } + } else { + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kColumn * stride_; + + dst_ptr[idx] = *reinterpret_cast( + pointers_[0] + row_offset + col_offset); + idx++; + } + } + + } + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// + +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Element type + typename Element_, + /// Layout of operand in memory + typename Layout_, + /// Shape of one matrix product operation (concept: MatrixShape) + typename InstructionShape_> +class MmaTensorOpAccumulatorTileIterator; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for C operands of row-major layouts +/// +/// Concept: MutableRandomAccessContiguousTileIteratorConcept | +/// WriteableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of A elements + typename Element_, + /// Shape of one matrix product operation (concept: MatrixShape) + typename InstructionShape_ +> +class MmaTensorOpAccumulatorTileIterator< + Shape_, + Element_, + layout::RowMajor, + InstructionShape_> { +public: + + /// Shape of tile to load (concept: MatrixShape) + using Shape = Shape_; + + /// Element type + using Element = Element_; + + /// Layout of accumulators in memory + using Layout = layout::RowMajor; + + using WarpThreadArrangement = layout::PitchLinearShape<16, 4>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + // + // Derived quantities + // + + static_assert( + (!(Shape::kRow % WarpThreadArrangement::kStrided)) && + (!(Shape::kColumn % WarpThreadArrangement::kContiguous)), + "Warp-level GEMM shape must be divisible by the arrangement of threads in the warp."); + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero."); + static_assert(Shape::kColumn > 0, "Shape::kColumn must be greater than zero."); + static_assert(Shape::kRow / WarpThreadArrangement::kStrided> 0, + "Shape::kRow / WarpThreadArrangement::kStrided must be greater than zero."); + static_assert(Shape::kColumn / WarpThreadArrangement::kContiguous > 0, + "Shape::kColumn / WarpThreadArrangement::kContiguous must be greater than zero."); + + /// Packed size + static int const kPackedSize = 32 / sizeof_bits::value; + + /// Access shape + using AccessShape = layout::PitchLinearShape; + + /// Shape in vectors + using ShapeVec = MatrixShape< + Shape::kRow, + Shape::kColumn / AccessShape::kContiguous + >; + + /// Thread-level shape in vec of a fragment + using ThreadShape = MatrixShape< + ShapeVec::kRow / WarpThreadArrangement::kStrided, + ShapeVec::kColumn / WarpThreadArrangement::kContiguous + >; + + /// Number of individual loads within one instruction result + using IterationsInner = MatrixShape< + InstructionShape::kM / WarpThreadArrangement::kStrided / kPackedSize, + InstructionShape::kN / WarpThreadArrangement::kContiguous + >; + + /// Number of iterations in units of instruction shape + using Iterations = MatrixShape< + Shape::kRow / InstructionShape::kM, + Shape::kColumn / InstructionShape::kN + >; + + /// Delta in units of elements + using Delta = MatrixShape< + WarpThreadArrangement::kStrided, + WarpThreadArrangement::kContiguous * AccessShape::kContiguous + >; + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + TensorRef ref_; + + MatrixCoord init_offset_; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpAccumulatorTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpAccumulatorTileIterator( + TensorRef const &ref, + int lane_id + ): ref_(ref) { + + init_offset_ = TensorCoord( + lane_id / 16 * kPackedSize, + lane_id % 16 + ); + } + + /// Adds a pointer offset to internal pointer(s) to advance through memory + CUTLASS_HOST_DEVICE + MmaTensorOpAccumulatorTileIterator &add_pointer_offset(LongIndex offset) { + ref_.add_pointer_offset(offset); + return *this; + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpAccumulatorTileIterator &add_tile_offset(TensorCoord const &coord) { + + ref_.add_coord_offset(coord * make_Coord(Shape::kRow, Shape::kColumn)); + + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpAccumulatorTileIterator & operator++() { + // deliberate no-op + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpAccumulatorTileIterator & operator--() { + // deliberate no-op + return *this; + } + + /// Loads a fragment from memory with additional logical offset + CUTLASS_HOST_DEVICE + void load_with_pointer_offset( + Fragment &frag, ///< fragment to be loaded from memory + Index pointer_offset) const { ///< linear offset (in units of Element) when loading + + CUTLASS_PRAGMA_UNROLL + for(int m = 0; m < Iterations::kRow; ++m) { + CUTLASS_PRAGMA_UNROLL + for(int n = 0; n < Iterations::kColumn; ++n) { + CUTLASS_PRAGMA_UNROLL + for(int inner_n = 0; inner_n < IterationsInner::kColumn; ++inner_n) { + CUTLASS_PRAGMA_UNROLL + for(int inner_m = 0; inner_m < IterationsInner::kRow; ++inner_m) { + TensorCoord offset(m * inner_m, n * inner_n); + + Array const * src_ptr = + reinterpret_cast const *>( + ref_.data() + pointer_offset + ref_.offset(init_offset_ + offset)); + + Array *dst_ptr = + reinterpret_cast*>(&frag) + + inner_m + inner_n * IterationsInner::kRow + + n * IterationsInner::kCount + m * Iterations::kColumn * IterationsInner::kCount; + + *dst_ptr = src_ptr[0]; + } + } + } + } + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + + /// Stores a fragment to memory at the location pointed to by the iterator + CUTLASS_HOST_DEVICE + void store_with_pointer_offset(Fragment const &frag, Index pointer_offset) const { + + CUTLASS_PRAGMA_UNROLL + for(int m = 0; m < Iterations::kRow; ++m) { + CUTLASS_PRAGMA_UNROLL + for(int n = 0; n < Iterations::kColumn; ++n) { + CUTLASS_PRAGMA_UNROLL + for(int inner_n = 0; inner_n < IterationsInner::kColumn; ++inner_n) { + CUTLASS_PRAGMA_UNROLL + for(int inner_m = 0; inner_m < IterationsInner::kRow; ++inner_m) { + TensorCoord offset((m * IterationsInner::kRow + inner_m) * Delta::kRow, + (n * IterationsInner::kColumn + inner_n) * Delta::kColumn); + Array * dst_ptr = + reinterpret_cast *>( + ref_.data() + pointer_offset + ref_.offset(offset + init_offset_)); + + Array const * src_ptr = + reinterpret_cast const *>(&frag) + + inner_m + IterationsInner::kRow * inner_n + n * IterationsInner::kCount + + m * Iterations::kColumn * IterationsInner::kCount; + + *dst_ptr = *src_ptr; + } + } + } + } + } + + /// Stores a fragment to memory at the location pointed to by the iterator + CUTLASS_HOST_DEVICE + void store(Fragment const &frag) const { + store_with_pointer_offset(frag, 0); + } +}; + +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for row-major A operands of 4bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kA, + Element_, + layout::TensorOpEm<32, layout::RowMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpEm<32, layout::RowMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert(Shape::kColumn == InstructionShape::kK, "Shape::kColumn must equal InstructionShape::kK"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape; + }; + + /// Access type +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + using AccessType = Array; +#else + using AccessType = Array; +#endif + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Offset in units of element + int offset_ = 0; + + /// Pointers holding same stride +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + Element* pointer_; +#else + Element* pointers_[4]; +#endif + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + pointer_ = ref.data(); +#else + Element* ptr = ref.data() + ref.offset({lane_id / 16, lane_id % 16}); + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + pointers_[i] = ptr + i * 64; + } +#endif + } + + /// Adds a pointer offset to interal pointer(s) to advance through memory + /// So far, isn't used anywhere. Offset must be muliple of Layout::TileShape + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_pointer_offset(LongIndex offset) { + offset_ += int(offset); + return *this; + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + offset_ += tile_offset.row() * Shape::kRow * stride_ + + tile_offset.column() * (Shape::kColumn / layout::EmShape::kColumn) * layout::EmShape::kCount; + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({0, 1}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({0, -1}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int offset = offset_ + ptr_offset; + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + auto tmp = __builtin_bi_slb_blkld_fx4((unsigned)((unsigned long long)(pointer_ + offset)), 0); + dst_ptr[r][0] = tmp[0]; + dst_ptr[r][1] = tmp[1]; + dst_ptr[r][2] = tmp[2]; + dst_ptr[r][3] = tmp[3]; + offset += stride_ * 16; + } + } +#else + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int idx = 0; + int offset = offset_ + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + dst_ptr[idx] = *reinterpret_cast(pointers_[i] + offset); + ++idx; + } + offset += stride_ * 16; + } + } +#endif + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for column-major A operands of 4bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kA, + Element_, + layout::TensorOpEm<32, layout::ColumnMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpEm<32, layout::ColumnMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert(Shape::kColumn == InstructionShape::kK, "Shape::kColumn must equal InstructionShape::kK"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape; + }; + + /// Access type +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + using AccessType = Array; +#else + using AccessType = Array; +#endif + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Offset in units of element + int offset_ = 0; + + /// Pointers holding same stride +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + Element* pointer_; +#else + Element* pointers_[4]; +#endif + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + pointer_ = ptr; +#else + int const r = lane_id / 16; + int const c = lane_id % 16; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + pointers_[i] = ptr + ref.offset({r + i * 4, c}); + } +#endif + } + + /// Adds a pointer offset to interal pointer(s) to advance through memory + /// So far, isn't used anywhere. Offset must be muliple of Layout::TileShape + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_pointer_offset(LongIndex offset) { + offset_ += int(offset); + return *this; + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + offset_ += tile_offset.column() * Shape::kColumn * stride_ + + tile_offset.row() * (Shape::kRow / layout::EmShape::kRow) * layout::EmShape::kCount; + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({0, 1}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({0, -1}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int offset = offset_ + ptr_offset; + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + auto tmp = __builtin_bi_slb_blkld_fx4((unsigned)((unsigned long long)(pointer_ + offset)), 0); + dst_ptr[r][0] = tmp[0]; + dst_ptr[r][1] = tmp[1]; + dst_ptr[r][2] = tmp[2]; + dst_ptr[r][3] = tmp[3]; + offset += layout::EmShape::kCount; + } + } +#else + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int idx = 0; + int offset = offset_ + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + dst_ptr[idx] = *reinterpret_cast(pointers_[i] + offset); + ++idx; + } + offset += layout::EmShape::kCount; + } + } +#endif + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for row-major B operands of 4bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kB, + Element_, + layout::TensorOpEm<32, layout::RowMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpEm<32, layout::RowMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert(Shape::kRow == InstructionShape::kK, "Shape::kRow must equal InstructionShape::kK"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape<1, Shape::kColumn / InstructionShape::kN>; + }; + + /// Access type +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + using AccessType = Array; +#else + using AccessType = Array; +#endif + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Offset in units of element + int offset_ = 0; + + /// Pointers holding same stride +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + Element* pointer_; +#else + Element* pointers_[4]; +#endif + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + pointer_ = ptr; +#else + int const r = lane_id / 16; + int const c = lane_id % 16; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + pointers_[i] = ptr + ref.offset({r + i * 4, c}); + } +#endif + } + + /// Adds a pointer offset to interal pointer(s) to advance through memory + /// So far, isn't used anywhere. Offset must be muliple of Layout::TileShape + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_pointer_offset(LongIndex offset) { + offset_ += int(offset); + return *this; + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + offset_ += tile_offset.row() * Shape::kRow * stride_ + + tile_offset.column() * (Shape::kColumn / layout::EmShape::kColumn) * layout::EmShape::kCount; + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({1, 0}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({-1, 0}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int offset = offset_ + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + auto tmp = __builtin_bi_slb_blkld_fx4((unsigned)((unsigned long long)(pointer_ + offset)), 0); + dst_ptr[c][0] = tmp[0]; + dst_ptr[c][1] = tmp[1]; + dst_ptr[c][2] = tmp[2]; + dst_ptr[c][3] = tmp[3]; + offset += layout::EmShape::kCount; + } + } +#else + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int idx = 0; + int offset = offset_ + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + dst_ptr[idx] = *reinterpret_cast(pointers_[i] + offset); + ++idx; + } + offset += layout::EmShape::kCount; + } + } +#endif + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for column-major B operands of 4bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kB, + Element_, + layout::TensorOpEm<32, layout::ColumnMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kB; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpEm<32, layout::ColumnMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert(Shape::kRow == InstructionShape::kK, "Shape::kRow must equal InstructionShape::kK"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape<1, Shape::kColumn / InstructionShape::kN>; + }; + + /// Access type +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + using AccessType = Array; +#else + using AccessType = Array; +#endif + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Offset in units of element + int offset_ = 0; + + /// Pointers holding same stride +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + Element* pointer_; +#else + Element* pointers_[4]; +#endif + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + pointer_ = ptr; +#else + int const r = lane_id / 16; + int const c = lane_id % 16; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + pointers_[i] = ptr + ref.offset({r + i * 4, c}); + } +#endif + } + + /// Adds a pointer offset to interal pointer(s) to advance through memory + /// So far, isn't used anywhere. Offset must be muliple of Layout::TileShape + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_pointer_offset(LongIndex offset) { + offset_ += int(offset); + return *this; + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + offset_ += tile_offset.column() * Shape::kColumn * stride_ + + tile_offset.row() * (Shape::kRow / layout::EmShape::kRow) * layout::EmShape::kCount; + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({1, 0}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({-1, 0}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int offset = offset_ + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + auto tmp = __builtin_bi_slb_blkld_fx4((unsigned)((unsigned long long)(pointer_ + offset)), 0); + dst_ptr[c][0] = tmp[0]; + dst_ptr[c][1] = tmp[1]; + dst_ptr[c][2] = tmp[2]; + dst_ptr[c][3] = tmp[3]; + offset += stride_ * 16; + } + } +#else + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int idx = 0; + int offset = offset_ + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 4; ++i) { + dst_ptr[idx] = *reinterpret_cast(pointers_[i] + offset); + idx++; + } + offset += stride_ * 16; + } + } +#endif + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +/// 2bytes (half/bhalf) /// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for row-major A operands of 2bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kA, + Element_, + layout::TensorOpEm<16, layout::RowMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpEm<16, layout::RowMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert(Shape::kColumn == InstructionShape::kK, "Shape::kColumn must equal InstructionShape::kK"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape; + }; + + /// Access type +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + using AccessType = Array; +#else + using AccessType = Array; +#endif + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + Element* pointer_; +#else + Element* pointers_[4]; +#endif + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + pointer_ = ptr; +#else + int r = (lane_id / 16) * 2; + int c = lane_id % 16; + + pointers_[0] = ptr + ref.offset({r, c}); + pointers_[1] = ptr + ref.offset({r + 8, c}); +#endif + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row() * (Shape::kRow / layout::EmShape::kRow); + iteration_column_ += tile_offset.column(); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({0, 1}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({0, -1}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const col_offset = iteration_column_ * layout::EmShape::kCount + ptr_offset; + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kRow * stride_; + + auto tmp = __builtin_bi_slb_blkld_fx2((unsigned)((unsigned long long)(pointer_ + row_offset + col_offset)), 0); + AccessType* at = reinterpret_cast(&tmp); + dst_ptr[r][0] = at->at(0).get(); + dst_ptr[r][1] = at->at(1).get(); + dst_ptr[r][2] = at->at(2).get(); + dst_ptr[r][3] = at->at(3).get(); + } + } +#else + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const col_offset = iteration_column_ * layout::EmShape::kCount + ptr_offset; + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kRow * stride_; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 2; ++i) { + dst_ptr[r * 2 + i] = *reinterpret_cast(pointers_[i] + col_offset + row_offset); + } + } + } +#endif + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for column-major A operands of 2bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kA, + Element_, + layout::TensorOpEm<16, layout::ColumnMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpEm<16, layout::ColumnMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape; + }; + + /// Access type +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + using AccessType = Array; +#else + using AccessType = Array; +#endif + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + Element* pointer_; +#else + Element* pointers_[2]; +#endif + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + pointer_ = ptr; +#else + int r = (lane_id / 16) * 2; + int c = lane_id % 16; + + pointers_[0] = ptr + ref.offset({r, c}); + pointers_[1] = ptr + ref.offset({r + 8, c}); +#endif + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row() * (Shape::kRow / layout::EmShape::kRow); + iteration_column_ += tile_offset.column(); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({0, 1}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({0, -1}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const col_offset = iteration_column_ * layout::EmShape::kColumn * stride_ + ptr_offset; + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kCount; + + auto tmp = __builtin_bi_slb_blkld_fx2((unsigned)((unsigned long long)(pointer_ + row_offset + col_offset)), 0); + AccessType* at = reinterpret_cast(&tmp); + dst_ptr[r][0] = at->at(0).get(); + dst_ptr[r][1] = at->at(1).get(); + dst_ptr[r][2] = at->at(2).get(); + dst_ptr[r][3] = at->at(3).get(); + } + } +#else + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const col_offset = iteration_column_ * layout::EmShape::kColumn * stride_ + ptr_offset; + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kCount; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 2; ++i) { + dst_ptr[r * 2 + i] = *reinterpret_cast(pointers_[i] + col_offset + row_offset); + } + } + } +#endif + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for row-major B operands of 2bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kB, + Element_, + layout::TensorOpEm<16, layout::RowMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kB; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpEm<16, layout::RowMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape<1, Shape::kColumn / InstructionShape::kN>; + }; + + /// Access type +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + using AccessType = Array; +#else + using AccessType = Array; +#endif + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + Element* pointer_; +#else + Element* pointers_[2]; +#endif + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + pointer_ = ref.data(); +#else + int r = (lane_id / 16) * 2; + int c = lane_id % 16; + + pointers_[0] = ref.data() + ref.offset({r, c}); + pointers_[1] = ref.data() + ref.offset({r + 8, c}); +#endif + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row(); + iteration_column_ += tile_offset.column() * (Shape::kColumn / layout::EmShape::kColumn); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({1, 0}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({-1, 0}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const row_offset = iteration_row_ * layout::EmShape::kRow * stride_ + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kCount; + + auto tmp = __builtin_bi_slb_blkld_fx2((unsigned)((unsigned long long)(pointer_ + row_offset + col_offset)), 0); + AccessType* at = reinterpret_cast(&tmp); + dst_ptr[c][0] = at->at(0).get(); + dst_ptr[c][1] = at->at(1).get(); + dst_ptr[c][2] = at->at(2).get(); + dst_ptr[c][3] = at->at(3).get(); + } + } +#else + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const row_offset = iteration_row_ * layout::EmShape::kRow * stride_ + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kCount; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 2; ++i) { + dst_ptr[c * 2 + i] = *reinterpret_cast(pointers_[i] + col_offset + row_offset); + } + } + } +#endif + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for column-major B operands of 2bytes width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kB, + Element_, + layout::TensorOpEm<16, layout::ColumnMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kB; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpEm<16, layout::ColumnMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape<1, Shape::kColumn / InstructionShape::kN>; + }; + + /// Access type +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + using AccessType = Array; +#else + using AccessType = Array; +#endif + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + Element* pointer_; +#else + Element* pointers_[2]; +#endif + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + pointer_ = ptr; +#else + int r = (lane_id / 16) * 2; + int c = lane_id % 16; + + pointers_[0] = ptr + int(ref.offset({r, c})); + pointers_[1] = ptr + int(ref.offset({r + 8, c})); +#endif + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row(); + iteration_column_ += tile_offset.column() * (Shape::kColumn / layout::EmShape::kColumn); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({1, 0}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({-1, 0}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const row_offset = iteration_row_ * layout::EmShape::kCount + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kColumn * stride_; + + auto tmp = __builtin_bi_slb_blkld_fx2((unsigned)((unsigned long long)(pointer_ + row_offset + col_offset)), 0); + AccessType* at = reinterpret_cast(&tmp); + dst_ptr[c][0] = at->at(0).get(); + dst_ptr[c][1] = at->at(1).get(); + dst_ptr[c][2] = at->at(2).get(); + dst_ptr[c][3] = at->at(3).get(); + } + } +#else + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const row_offset = iteration_row_ * layout::EmShape::kCount + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kColumn * stride_; + + CUTLASS_PRAGMA_UNROLL + for(int i = 0; i < 2; ++i) { + dst_ptr[c * 2 + i] = *reinterpret_cast(pointers_[i] + row_offset + col_offset); + } + } + } +#endif + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +/// 1byte (int8/uint8) /// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for row-major A operands of 1byte width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kA, + Element_, + layout::TensorOpEm<8, layout::RowMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpEm<8, layout::RowMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert(Shape::kColumn == InstructionShape::kK, "Shape::kColumn must equal InstructionShape::kK"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape; + }; + + /// Access type +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + using AccessType = Array; +#else + using AccessType = Array; +#endif + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride + Element* pointer_; + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + pointer_ = ptr; +#else + int r = (lane_id / 16) * 4; + int c = lane_id % 16; + + pointer_ = ptr + ref.offset({r, c}); +#endif + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row() * (Shape::kRow / layout::EmShape::kRow); + iteration_column_ += tile_offset.column(); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({0, 1}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({0, -1}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const col_offset = iteration_column_ * layout::EmShape::kCount + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kRow * stride_; + + auto tmp = __builtin_bi_slb_blkld_fx1((unsigned)((unsigned long long)(pointer_ + row_offset + col_offset)), 0); + AccessType* at = reinterpret_cast(&tmp); + dst_ptr[r][0] = at->at(0).get(); + dst_ptr[r][1] = at->at(1).get(); + dst_ptr[r][2] = at->at(2).get(); + dst_ptr[r][3] = at->at(3).get(); + } + } +#else + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const col_offset = iteration_column_ * layout::EmShape::kCount + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kRow * stride_; + + dst_ptr[r] = *reinterpret_cast(pointer_ + col_offset + row_offset); + } + } +#endif + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for column-major A operands of 1byte width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kA, + Element_, + layout::TensorOpEm<8, layout::ColumnMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kA; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpEm<8, layout::ColumnMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape; + }; + + /// Access type +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + using AccessType = Array; +#else + using AccessType = Array; +#endif + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride + Element* pointer_; + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + pointer_ = ptr; +#else + int r = (lane_id / 16) * 4; + int c = lane_id % 16; + + pointer_ = ptr + ref.offset({r, c}); +#endif + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row() * (Shape::kRow / layout::EmShape::kRow); + iteration_column_ += tile_offset.column(); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({0, 1}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({0, -1}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const col_offset = iteration_column_ * layout::EmShape::kColumn * stride_ + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kCount; + + auto tmp = __builtin_bi_slb_blkld_fx1((unsigned)((unsigned long long)(pointer_ + row_offset + col_offset)), 0); + AccessType* at = reinterpret_cast(&tmp); + dst_ptr[r][0] = at->at(0).get(); + dst_ptr[r][1] = at->at(1).get(); + dst_ptr[r][2] = at->at(2).get(); + dst_ptr[r][3] = at->at(3).get(); + } + } +#else + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const col_offset = iteration_column_ * layout::EmShape::kColumn * stride_ + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int r = 0; r < Detail::Iterations::kRow; ++r) { + int const row_offset = (iteration_row_ + r) * layout::EmShape::kCount; + + dst_ptr[r] = *reinterpret_cast(pointer_ + col_offset + row_offset); + } + } +#endif + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for row-major B operands of 1byte width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kB, + Element_, + layout::TensorOpEm<8, layout::RowMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kB; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpEm<8, layout::RowMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape<1, Shape::kColumn / InstructionShape::kN>; + }; + + /// Access type +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + using AccessType = Array; +#else + using AccessType = Array; +#endif + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride + Element* pointer_; + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + pointer_ = ref.data(); +#else + int r = (lane_id / 16) * 4; + int c = lane_id % 16; + + pointer_ = ref.data() + ref.offset({r, c}); +#endif + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row(); + iteration_column_ += tile_offset.column() * (Shape::kColumn / layout::EmShape::kColumn); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({1, 0}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({-1, 0}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const row_offset = iteration_row_ * layout::EmShape::kRow * stride_ + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kCount; + + auto tmp = __builtin_bi_slb_blkld_fx1((unsigned)((unsigned long long)(pointer_ + row_offset + col_offset)), 0); + AccessType* at = reinterpret_cast(&tmp); + dst_ptr[c][0] = at->at(0).get(); + dst_ptr[c][1] = at->at(1).get(); + dst_ptr[c][2] = at->at(2).get(); + dst_ptr[c][3] = at->at(3).get(); + } + } +#else + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const row_offset = iteration_row_ * layout::EmShape::kRow * stride_ + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kCount; + + dst_ptr[c] = *reinterpret_cast(pointer_ + col_offset + row_offset); + } + } +#endif + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; + +//////////////////////////////////////////////////////////////////////////////// +/// Specialization for column-major B operands of 1byte width type +/// +/// Satisfies: +/// ReadableRandomAccessContiguousTileIteratorConcept +/// +template < + /// Size of the matrix to load (concept: MatrixShape) + typename Shape_, + /// Data type of elements + typename Element_, + /// Shape of one matrix product operation (conecpt: PitchLinearShape) + typename InstructionShape_, + /// Number of partitions along K dimension + int PartitionsK> +class MmaTensorOpMultiplicandTileIterator< + Shape_, + Operand::kB, + Element_, + layout::TensorOpEm<8, layout::ColumnMajor>, + InstructionShape_, + NUM_THREADS_PER_WARP, + PartitionsK> { + +public: + + /// Shape of tile to load (Concept: MatrixShape) + using Shape = Shape_; + + /// Operand type + static Operand const kOperand = Operand::kB; + + /// Element type + using Element = Element_; + + /// Layout of source tile + using Layout = layout::TensorOpEm<8, layout::ColumnMajor>; + + /// Shape of one matrix product operation (concept: GemmShape) + using InstructionShape = InstructionShape_; + + /// Number of participating threads + static int const kThreads = NUM_THREADS_PER_WARP; + + /// Number of partitions along K dimension + static int const kPartitionsK = PartitionsK; + + /// TensorRef type for loading element from a tensor + using TensorRef = TensorRef; + + /// Index type + using Index = typename TensorRef::Index; + + /// Long Index type + using LongIndex = typename TensorRef::LongIndex; + + /// Coordinate for an element in the tensor + using TensorCoord = typename TensorRef::TensorCoord; + + /// Packed Size + static int const kPackedSize = 32 / sizeof_bits::value; + + static_assert(Shape::kRow > 0, "Shape::kRow must be greater than zero"); + static_assert(Shape::kColumn> 0, "Shape::kColumn must be greater than zero"); + static_assert((!(Shape::kRow % layout::EmShape::kRow) && + !(Shape::kColumn % layout::EmShape::kColumn)), + "Shape must be divisibile by EM shape."); + + /// Internal structure of iterator - made public to enable introspection + struct Detail { + + /// Determine access shape in units of elements per access + using AccessShape = layout::PitchLinearShape; + + /// Determine iterations + using Iterations = MatrixShape<1, Shape::kColumn / InstructionShape::kN>; + }; + + /// Access type +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + using AccessType = Array; +#else + using AccessType = Array; +#endif + +public: + + /// Fragment object holding a thread's part of a tile + using Fragment = Array; + +private: + + /// Stride + int stride_; + + /// Pointers holding same stride + Element* pointer_; + + /// Iterations along row dimension in units of em + int iteration_row_ = 0; + + /// Iterations along column dimension in units of em + int iteration_column_ = 0; + +public: + + /// Default ctor constructs null iterator + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator() { } + + /// Constructor from TensorRef + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator( + TensorRef ref, + int lane_id + ) : stride_(ref.stride(0)) { + + Element* ptr = ref.data(); +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + pointer_ = ptr; +#else + int r = (lane_id / 16) * 4; + int c = lane_id % 16; + + pointer_ = ptr + ref.offset({r, c}); +#endif + } + + /// Advances an iterator along logical dimensions of matrix in units of whole tiles + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator &add_tile_offset(TensorCoord const &tile_offset) { + iteration_row_ += tile_offset.row(); + iteration_column_ += tile_offset.column() * (Shape::kColumn / layout::EmShape::kColumn); + return *this; + } + + /// Advances the iterator along the advance dimension + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator++() { + add_tile_offset({1, 0}); + return *this; + } + + /// Advances the iterator along the opposite of the advance dimension + CUTLASS_HOST_DEVICE + MmaTensorOpMultiplicandTileIterator & operator--() { + add_tile_offset({-1, 0}); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator+=(TensorCoord const &tile_offset) { + add_tile_offset(tile_offset); + return *this; + } + + ///< advances in units of whole tiles along the logical coordinate space of the tensor + CUTLASS_DEVICE + MmaTensorOpMultiplicandTileIterator & operator-=(TensorCoord const &tile_offset) { + add_tile_offset(-tile_offset); + return *this; + } + + /// Loads a fragment from memory at the location pointed to by the iterator. + CUTLASS_HOST_DEVICE + void load(Fragment &frag) const { + load_with_pointer_offset(frag, 0); + } + +#if SLB_BLOCK_LOAD_INSTRINSIC_ENABLED + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const row_offset = iteration_row_ * layout::EmShape::kCount + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kColumn * stride_; + + auto tmp = __builtin_bi_slb_blkld_fx1((unsigned)((unsigned long long)(pointer_ + row_offset + col_offset)), 0); + AccessType* at = reinterpret_cast(&tmp); + dst_ptr[c][0] = at->at(0).get(); + dst_ptr[c][1] = at->at(1).get(); + dst_ptr[c][2] = at->at(2).get(); + dst_ptr[c][3] = at->at(3).get(); + } + } +#else + CUTLASS_HOST_DEVICE + void load_with_pointer_offset(Fragment &frag, Index ptr_offset) const { + AccessType *dst_ptr = reinterpret_cast(&frag); + + int const row_offset = iteration_row_ * layout::EmShape::kCount + ptr_offset; + + CUTLASS_PRAGMA_UNROLL + for(int c = 0; c < Detail::Iterations::kColumn; ++c) { + int const col_offset = (iteration_column_ + c) * layout::EmShape::kColumn * stride_; + + dst_ptr[c] = *reinterpret_cast(pointer_ + row_offset + col_offset); + } + } +#endif + + /// Notify the iterator which k-group it is currently pointing to. + /// + /// This does not advance the iterator. Rather, it overrides its internal + /// tracking with constant-valued k-group index to enable the compiler to + /// fold constants and achieve more efficient code. + /// + /// This is used by some nontrivial permuted layouts. + CUTLASS_DEVICE + void set_kgroup_index(int k_group) { + // no op + } +}; +} // namespace warp +} // namespace gemm +} // namespace cutlass + +////////////////////////////////////////////////////////////////////////////////