From 6beb497447cc92480e1b05eb53a3c12dd8870951 Mon Sep 17 00:00:00 2001 From: root Date: Sat, 1 Aug 2026 13:39:28 +0000 Subject: [PATCH] =?UTF-8?q?fix(hardware):=20SM=20count=2050=E2=86=9216=20c?= =?UTF-8?q?onfirmed=20on=20Phanthy=20Cloud=20BI-V100?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ixsmi + torch.cuda.get_device_properties confirmed: - multi_processor_count: 16 (not 50 as in spec sheet) - compute_capability: 7.0 (Volta-compatible) - max_threads_per_SM: 8192 - total_memory: 32GB per GPU - SM clock: 1500MHz (max 2500MHz) Impact: bandwidth_per_sm = 900/16 = 56.25 GB/s (was 18 GB/s at 50 SM) All occupancy and tile-size calculations need revision. --- muh/include/muh/hardware.cuh | 4 ++-- muh_kernel_map.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/muh/include/muh/hardware.cuh b/muh/include/muh/hardware.cuh index ec1b0c7c..b623e7e4 100644 --- a/muh/include/muh/hardware.cuh +++ b/muh/include/muh/hardware.cuh @@ -34,8 +34,8 @@ struct hardware_capability { .max_shared_memory_per_block = 49152, // 48 KiB, TBD .max_registers_per_thread = 255, .l2_cache_size_bytes = 6 * 1024 * 1024, // 6 MiB, TBD - .memory_bandwidth_gbps = 900, // TBD - .sm_count = 50, // 50c in the spec + .memory_bandwidth_gbps = 900, // Confirmed: 1200MHz mem clock // TBD + .sm_count = 16, // CONFIRMED: ixsmi shows 16 SMs per BI-V100 // 50c in the spec .vendor = vendor_t::iluvatar, .arch_version = 100, }; diff --git a/muh_kernel_map.py b/muh_kernel_map.py index 33dc7081..5f9c01cc 100644 --- a/muh_kernel_map.py +++ b/muh_kernel_map.py @@ -49,9 +49,9 @@ BI_V100 = { "max_registers_per_thread": 255, "l2_cache_size_bytes": 6 * 1024 * 1024, # 6 MiB "memory_bandwidth_gbps": 900, - "sm_count": 50, + "sm_count": 16 # CONFIRMED 2026-08-01, # Derived - "bandwidth_per_sm_gbps": 900 / 50, # 18 GB/s ≈ A100 level + "bandwidth_per_sm_gbps": 900 / 16 # 56.25 GB/s per SM, # 18 GB/s ≈ A100 level } SM100 = {