[INFRA] Import NVIDIA/CCCL upstream as optimization reference library

CCCL (CUDA C++ Core Libraries) provides:
- CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk)
- Thrust: high-level parallel algorithms (transform_reduce, sort, scan)
- libcudacxx: CUDA C++ standard library (atomics, barriers, memory)
- cudax: experimental features (memory resources, allocators)
- Tuning policies: per-SM hardware-specific algorithm parameters

Competition optimization vectors mapped to CCCL:
- Output TPS (83% weight): warp_reduce, block_reduce, device_topk
- Input TPS (14% weight): device_scan, block_load, prefetch
- Cache TPS (3% weight): prefix caching strategy patterns
- Memory (0.9 util): pooled/cached/buddy allocators

Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only)
License: Apache-2.0

cccl_upstream/thrust/benchmarks/bench/vectorized_search/base.cu

@@ -0,0 +1,43 @@
+// SPDX-FileCopyrightText: Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved.
+// SPDX-License-Identifier: BSD-3
+
+#include <thrust/binary_search.h>
+#include <thrust/device_vector.h>
+#include <thrust/execution_policy.h>
+#include <thrust/sort.h>
+
+#include "nvbench_helper.cuh"
+
+template <typename T>
+static void basic(nvbench::state& state, nvbench::type_list<T>)
+{
+  const auto elements      = static_cast<std::size_t>(state.get_int64("Elements"));
+  const auto needles_ratio = static_cast<std::size_t>(state.get_int64("NeedlesRatio"));
+  const auto needles       = needles_ratio * static_cast<std::size_t>(static_cast<double>(elements) / 100.0);
+
+  thrust::device_vector<T> data = generate(elements + needles);
+  thrust::device_vector<bool> result(needles);
+  thrust::sort(data.begin(), data.begin() + elements);
+
+  state.add_element_count(needles);
+
+  caching_allocator_t alloc;
+  state.exec(nvbench::exec_tag::gpu | nvbench::exec_tag::no_batch | nvbench::exec_tag::sync,
+             [&](nvbench::launch& launch) {
+               thrust::binary_search(
+                 policy(alloc, launch),
+                 data.begin(),
+                 data.begin() + elements,
+                 data.begin() + elements,
+                 data.end(),
+                 result.begin());
+             });
+}
+
+using types = nvbench::type_list<int8_t, int16_t, int32_t, int64_t>;
+
+NVBENCH_BENCH_TYPES(basic, NVBENCH_TYPE_AXES(types))
+  .set_name("base")
+  .set_type_axes_names({"T{ct}"})
+  .add_int64_power_of_two_axis("Elements", nvbench::range(16, 28, 4))
+  .add_int64_axis("NeedlesRatio", {1, 25, 50});

cccl_upstream/thrust/benchmarks/bench/vectorized_search/lower_bound.cu

@@ -0,0 +1,43 @@
+// SPDX-FileCopyrightText: Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved.
+// SPDX-License-Identifier: BSD-3
+
+#include <thrust/binary_search.h>
+#include <thrust/device_vector.h>
+#include <thrust/execution_policy.h>
+#include <thrust/sort.h>
+
+#include "nvbench_helper.cuh"
+
+template <typename T>
+static void basic(nvbench::state& state, nvbench::type_list<T>)
+{
+  const auto elements      = static_cast<std::size_t>(state.get_int64("Elements"));
+  const auto needles_ratio = static_cast<std::size_t>(state.get_int64("NeedlesRatio"));
+  const auto needles       = needles_ratio * static_cast<std::size_t>(static_cast<double>(elements) / 100.0);
+
+  thrust::device_vector<T> data = generate(elements + needles);
+  thrust::device_vector<T> result(needles);
+  thrust::sort(data.begin(), data.begin() + elements);
+
+  state.add_element_count(needles);
+
+  caching_allocator_t alloc;
+  state.exec(nvbench::exec_tag::gpu | nvbench::exec_tag::no_batch | nvbench::exec_tag::sync,
+             [&](nvbench::launch& launch) {
+               thrust::lower_bound(
+                 policy(alloc, launch),
+                 data.begin(),
+                 data.begin() + elements,
+                 data.begin() + elements,
+                 data.end(),
+                 result.begin());
+             });
+}
+
+using types = nvbench::type_list<int8_t, int16_t, int32_t, int64_t>;
+
+NVBENCH_BENCH_TYPES(basic, NVBENCH_TYPE_AXES(types))
+  .set_name("base")
+  .set_type_axes_names({"T{ct}"})
+  .add_int64_power_of_two_axis("Elements", nvbench::range(16, 28, 4))
+  .add_int64_axis("NeedlesRatio", {1, 25, 50});

cccl_upstream/thrust/benchmarks/bench/vectorized_search/upper_bound.cu

@@ -0,0 +1,43 @@
+// SPDX-FileCopyrightText: Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved.
+// SPDX-License-Identifier: BSD-3
+
+#include <thrust/binary_search.h>
+#include <thrust/device_vector.h>
+#include <thrust/execution_policy.h>
+#include <thrust/sort.h>
+
+#include "nvbench_helper.cuh"
+
+template <typename T>
+static void basic(nvbench::state& state, nvbench::type_list<T>)
+{
+  const auto elements      = static_cast<std::size_t>(state.get_int64("Elements"));
+  const auto needles_ratio = static_cast<std::size_t>(state.get_int64("NeedlesRatio"));
+  const auto needles       = needles_ratio * static_cast<std::size_t>(static_cast<double>(elements) / 100.0);
+
+  thrust::device_vector<T> data = generate(elements + needles);
+  thrust::device_vector<T> result(needles);
+  thrust::sort(data.begin(), data.begin() + elements);
+
+  state.add_element_count(needles);
+
+  caching_allocator_t alloc;
+  state.exec(nvbench::exec_tag::gpu | nvbench::exec_tag::no_batch | nvbench::exec_tag::sync,
+             [&](nvbench::launch& launch) {
+               thrust::upper_bound(
+                 policy(alloc, launch),
+                 data.begin(),
+                 data.begin() + elements,
+                 data.begin() + elements,
+                 data.end(),
+                 result.begin());
+             });
+}
+
+using types = nvbench::type_list<int8_t, int16_t, int32_t, int64_t>;
+
+NVBENCH_BENCH_TYPES(basic, NVBENCH_TYPE_AXES(types))
+  .set_name("base")
+  .set_type_axes_names({"T{ct}"})
+  .add_int64_power_of_two_axis("Elements", nvbench::range(16, 28, 4))
+  .add_int64_axis("NeedlesRatio", {1, 25, 50});