[INFRA] Import NVIDIA/CCCL upstream as optimization reference library

CCCL (CUDA C++ Core Libraries) provides:
- CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk)
- Thrust: high-level parallel algorithms (transform_reduce, sort, scan)
- libcudacxx: CUDA C++ standard library (atomics, barriers, memory)
- cudax: experimental features (memory resources, allocators)
- Tuning policies: per-SM hardware-specific algorithm parameters

Competition optimization vectors mapped to CCCL:
- Output TPS (83% weight): warp_reduce, block_reduce, device_topk
- Input TPS (14% weight): device_scan, block_load, prefetch
- Cache TPS (3% weight): prefix caching strategy patterns
- Memory (0.9 util): pooled/cached/buddy allocators

Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only)
License: Apache-2.0

cccl_upstream/libcudacxx/test/simd_codegen/min_max/min_max_3way_bf16.cu

@@ -0,0 +1,45 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+#if _CCCL_HAS_NVBF16()
+
+#  include <cuda_bf16.h>
+
+namespace simd = cuda::std::simd;
+
+using Vec_bf16_x1 = simd::basic_vec<__nv_bfloat16, simd::fixed_size<1>>;
+
+__device__ Vec_bf16_x1 test_min_bf16(Vec_bf16_x1 a, Vec_bf16_x1 b, Vec_bf16_x1 c)
+{
+  return simd::fmin(simd::fmin(a, b), c);
+}
+
+__device__ Vec_bf16_x1 test_max_bf16(Vec_bf16_x1 a, Vec_bf16_x1 b, Vec_bf16_x1 c)
+{
+  return simd::fmax(simd::fmax(a, b), c);
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_max_bf16.*}}
+; SM90: {{.*VHMNMX.BF16_V2.*!PT.*}}
+; SM100: {{.*VHMNMX.BF16_V2.*!PT.*}}
+; SM103: {{.*VHMNMX.BF16_V2.*!PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_min_bf16.*}}
+; SM90: {{.*VHMNMX.BF16_V2.*PT.*}}
+; SM100: {{.*VHMNMX.BF16_V2.*PT.*}}
+; SM103: {{.*VHMNMX.BF16_V2.*PT.*}}
+
+*/
+
+#endif // _CCCL_HAS_NVBF16()

cccl_upstream/libcudacxx/test/simd_codegen/min_max/min_max_3way_f16.cu

@@ -0,0 +1,45 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+#if _CCCL_HAS_NVFP16()
+
+#  include <cuda_fp16.h>
+
+namespace simd = cuda::std::simd;
+
+using Vec_f16_x1 = simd::basic_vec<__half, simd::fixed_size<1>>;
+
+__device__ Vec_f16_x1 test_min_f16(Vec_f16_x1 a, Vec_f16_x1 b, Vec_f16_x1 c)
+{
+  return simd::fmin(simd::fmin(a, b), c);
+}
+
+__device__ Vec_f16_x1 test_max_f16(Vec_f16_x1 a, Vec_f16_x1 b, Vec_f16_x1 c)
+{
+  return simd::fmax(simd::fmax(a, b), c);
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_max_f16.*}}
+; SM90: {{.*VHMNMX .*!PT.*}}
+; SM100: {{.*VHMNMX .*!PT.*}}
+; SM103: {{.*VHMNMX .*!PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_min_f16.*}}
+; SM90: {{.*VHMNMX .*PT.*}}
+; SM100: {{.*VHMNMX .*PT.*}}
+; SM103: {{.*VHMNMX .*PT.*}}
+
+*/
+
+#endif // _CCCL_HAS_NVFP16()

cccl_upstream/libcudacxx/test/simd_codegen/min_max/min_max_3way_integer.cu

@@ -0,0 +1,103 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+#include <cuda/std/cstdint>
+
+namespace simd = cuda::std::simd;
+
+using Vec_s32_x1 = simd::basic_vec<cuda::std::int32_t, simd::fixed_size<1>>;
+using Vec_u32_x1 = simd::basic_vec<cuda::std::uint32_t, simd::fixed_size<1>>;
+using Vec_s16_x2 = simd::basic_vec<cuda::std::int16_t, simd::fixed_size<2>>;
+using Vec_u16_x2 = simd::basic_vec<cuda::std::uint16_t, simd::fixed_size<2>>;
+
+__device__ Vec_u32_x1 test_min_u32(Vec_u32_x1 a, Vec_u32_x1 b, Vec_u32_x1 c)
+{
+  return simd::min(simd::min(a, b), c);
+}
+
+__device__ Vec_s32_x1 test_min_s32(Vec_s32_x1 a, Vec_s32_x1 b, Vec_s32_x1 c)
+{
+  return simd::min(simd::min(a, b), c);
+}
+
+__device__ Vec_u32_x1 test_max_u32(Vec_u32_x1 a, Vec_u32_x1 b, Vec_u32_x1 c)
+{
+  return simd::max(simd::max(a, b), c);
+}
+
+__device__ Vec_s32_x1 test_max_s32(Vec_s32_x1 a, Vec_s32_x1 b, Vec_s32_x1 c)
+{
+  return simd::max(simd::max(a, b), c);
+}
+
+__device__ Vec_u16_x2 test_min_u16_x2(Vec_u16_x2 a, Vec_u16_x2 b, Vec_u16_x2 c)
+{
+  return simd::min(simd::min(a, b), c);
+}
+
+__device__ Vec_s16_x2 test_min_s16_x2(Vec_s16_x2 a, Vec_s16_x2 b, Vec_s16_x2 c)
+{
+  return simd::min(simd::min(a, b), c);
+}
+
+__device__ Vec_u16_x2 test_max_u16_x2(Vec_u16_x2 a, Vec_u16_x2 b, Vec_u16_x2 c)
+{
+  return simd::max(simd::max(a, b), c);
+}
+
+__device__ Vec_s16_x2 test_max_s16_x2(Vec_s16_x2 a, Vec_s16_x2 b, Vec_s16_x2 c)
+{
+  return simd::max(simd::max(a, b), c);
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_max_s16_x2.*}}
+; SM90: {{.*VIMNMX3.S16x2.*!PT.*}}
+; SM100: {{.*VIMNMX3.S16x2.*!PT.*}}
+; SM103: {{.*VIMNMX3.S16x2.*!PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_max_u16_x2.*}}
+; SM90: {{.*VIMNMX3.U16x2.*!PT.*}}
+; SM100: {{.*VIMNMX3.U16x2.*!PT.*}}
+; SM103: {{.*VIMNMX3.U16x2.*!PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_min_s16_x2.*}}
+; SM90: {{.*VIMNMX3.S16x2.*PT.*}}
+; SM100: {{.*VIMNMX3.S16x2.*PT.*}}
+; SM103: {{.*VIMNMX3.S16x2.*PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_min_u16_x2.*}}
+; SM90: {{.*VIMNMX3.U16x2.*PT.*}}
+; SM100: {{.*VIMNMX3.U16x2.*PT.*}}
+; SM103: {{.*VIMNMX3.U16x2.*PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_max_s32.*}}
+; SM90: {{.*VIMNMX3 .*!PT.*}}
+; SM100: {{.*VIMNMX3 .*!PT.*}}
+; SM103: {{.*VIMNMX3 .*!PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_max_u32.*}}
+; SM90: {{.*VIMNMX3.U32.*!PT.*}}
+; SM100: {{.*VIMNMX3.U32.*!PT.*}}
+; SM103: {{.*VIMNMX3.U32.*!PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_min_s32.*}}
+; SM90: {{.*VIMNMX3 .*PT.*}}
+; SM100: {{.*VIMNMX3 .*PT.*}}
+; SM103: {{.*VIMNMX3 .*PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_min_u32.*}}
+; SM90: {{.*VIMNMX3.U32.*PT.*}}
+; SM100: {{.*VIMNMX3.U32.*PT.*}}
+; SM103: {{.*VIMNMX3.U32.*PT.*}}
+
+*/

cccl_upstream/libcudacxx/test/simd_codegen/min_max/min_max_i16x2.cu

@@ -0,0 +1,56 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+namespace simd = cuda::std::simd;
+
+using Vec_s16_x2 = simd::basic_vec<cuda::std::int16_t, simd::fixed_size<2>>;
+using Vec_u16_x2 = simd::basic_vec<cuda::std::uint16_t, simd::fixed_size<2>>;
+
+__device__ Vec_u16_x2 test_min_u16_x2(Vec_u16_x2 lhs, Vec_u16_x2 rhs)
+{
+  return simd::min(lhs, rhs);
+}
+
+__device__ Vec_s16_x2 test_min_s16_x2(Vec_s16_x2 lhs, Vec_s16_x2 rhs)
+{
+  return simd::min(lhs, rhs);
+}
+
+__device__ Vec_u16_x2 test_max_u16_x2(Vec_u16_x2 lhs, Vec_u16_x2 rhs)
+{
+  return simd::max(lhs, rhs);
+}
+
+__device__ Vec_s16_x2 test_max_s16_x2(Vec_s16_x2 lhs, Vec_s16_x2 rhs)
+{
+  return simd::max(lhs, rhs);
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_max_s16_x2.*}}
+; SM90: {{.*VIMNMX.S16x2.*!PT.*}}
+; SM1XX: {{.*VIMNMX.S16x2.*!PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_max_u16_x2.*}}
+; SM90: {{.*VIMNMX.U16x2.*!PT.*}}
+; SM1XX: {{.*VIMNMX.U16x2.*!PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_min_s16_x2.*}}
+; SM90: {{.*VIMNMX.S16x2.*PT.*}}
+; SM1XX: {{.*VIMNMX.S16x2.*PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_min_u16_x2.*}}
+; SM90: {{.*VIMNMX.U16x2.*PT.*}}
+; SM1XX: {{.*VIMNMX.U16x2.*PT.*}}
+
+*/

cccl_upstream/libcudacxx/test/simd_codegen/min_max/min_max_i8x4.cu

@@ -0,0 +1,52 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+namespace simd = cuda::std::simd;
+
+using Vec_s8_x4 = simd::basic_vec<cuda::std::int8_t, simd::fixed_size<4>>;
+using Vec_u8_x4 = simd::basic_vec<cuda::std::uint8_t, simd::fixed_size<4>>;
+
+__device__ Vec_u8_x4 test_min_u8_x4(Vec_u8_x4 lhs, Vec_u8_x4 rhs)
+{
+  return simd::min(lhs, rhs);
+}
+
+__device__ Vec_s8_x4 test_min_s8_x4(Vec_s8_x4 lhs, Vec_s8_x4 rhs)
+{
+  return simd::min(lhs, rhs);
+}
+
+__device__ Vec_u8_x4 test_max_u8_x4(Vec_u8_x4 lhs, Vec_u8_x4 rhs)
+{
+  return simd::max(lhs, rhs);
+}
+
+__device__ Vec_s8_x4 test_max_s8_x4(Vec_s8_x4 lhs, Vec_s8_x4 rhs)
+{
+  return simd::max(lhs, rhs);
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_max_s8_x4.*}}
+; SM120f: {{.*VIMNMX.S8x4.*!PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_max_u8_x4.*}}
+; SM120f: {{.*VIMNMX.U8x4.*!PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_min_s8_x4.*}}
+; SM120f: {{.*VIMNMX.S8x4.*PT.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_min_u8_x4.*}}
+; SM120f: {{.*VIMNMX.U8x4.*PT.*}}
+
+*/