[INFRA] Import NVIDIA/CCCL upstream as optimization reference library

CCCL (CUDA C++ Core Libraries) provides:
- CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk)
- Thrust: high-level parallel algorithms (transform_reduce, sort, scan)
- libcudacxx: CUDA C++ standard library (atomics, barriers, memory)
- cudax: experimental features (memory resources, allocators)
- Tuning policies: per-SM hardware-specific algorithm parameters

Competition optimization vectors mapped to CCCL:
- Output TPS (83% weight): warp_reduce, block_reduce, device_topk
- Input TPS (14% weight): device_scan, block_load, prefetch
- Cache TPS (3% weight): prefix caching strategy patterns
- Memory (0.9 util): pooled/cached/buddy allocators

Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only)
License: Apache-2.0

cccl_upstream/libcudacxx/test/simd_codegen/integer/arithmetic_u16x2.cu

@@ -0,0 +1,66 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+namespace simd = cuda::std::simd;
+
+using Vec_u16_x2 = simd::basic_vec<cuda::std::uint16_t, simd::fixed_size<2>>;
+
+__device__ Vec_u16_x2 test_operator_plus_u16_x2(Vec_u16_x2 lhs, Vec_u16_x2 rhs)
+{
+  return lhs + rhs;
+}
+
+__device__ Vec_u16_x2 test_operator_minus_u16_x2(Vec_u16_x2 lhs, Vec_u16_x2 rhs)
+{
+  return lhs - rhs;
+}
+
+__device__ Vec_u16_x2 test_operator_post_decrement_u16_x2(Vec_u16_x2 in)
+{
+  (void) in--;
+  return in;
+}
+
+__device__ Vec_u16_x2 test_operator_post_increment_u16_x2(Vec_u16_x2 in)
+{
+  (void) in++;
+  return in;
+}
+
+__device__ Vec_u16_x2 test_operator_unary_minus_u16_x2(Vec_u16_x2 in)
+{
+  return -in;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_unary_minus_u16_x2.*}}
+; SM90: {{.*VIADD.*}}
+; SM1XX: {{.*VIADD.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_post_increment_u16_x2.*}}
+; SM90: {{.*VIADD.*}}
+; SM1XX: {{.*VIADD.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_post_decrement_u16_x2.*}}
+; SM90: {{.*VIADD.*}}
+; SM1XX: {{.*VIADD.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_minus_u16_x2.*}}
+; SM90: {{.*VIADD.*}}
+; SM1XX: {{.*VIADD.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_plus_u16_x2.*}}
+; SM90: {{.*VIADD.*}}
+; SM1XX: {{.*VIADD.*}}
+
+*/

cccl_upstream/libcudacxx/test/simd_codegen/integer/arithmetic_u8x4.cu

@@ -0,0 +1,61 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+namespace simd = cuda::std::simd;
+
+using Vec_u8_x4 = simd::basic_vec<cuda::std::uint8_t, simd::fixed_size<4>>;
+
+__device__ Vec_u8_x4 test_operator_plus_u8_x4(Vec_u8_x4 lhs, Vec_u8_x4 rhs)
+{
+  return lhs + rhs;
+}
+
+__device__ Vec_u8_x4 test_operator_minus_u8_x4(Vec_u8_x4 lhs, Vec_u8_x4 rhs)
+{
+  return lhs - rhs;
+}
+
+__device__ Vec_u8_x4 test_operator_post_decrement_u8_x4(Vec_u8_x4 in)
+{
+  (void) in--;
+  return in;
+}
+
+__device__ Vec_u8_x4 test_operator_post_increment_u8_x4(Vec_u8_x4 in)
+{
+  (void) in++;
+  return in;
+}
+
+__device__ Vec_u8_x4 test_operator_unary_minus_u8_x4(Vec_u8_x4 in)
+{
+  return -in;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_unary_minus_u8_x4.*}}
+; SM120f: {{.*VIADD.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_post_increment_u8_x4.*}}
+; SM120f: {{.*VIADD.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_post_decrement_u8_x4.*}}
+; SM120f: {{.*VIADD.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_minus_u8_x4.*}}
+; SM120f: {{.*VIADD.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_plus_u8_x4.*}}
+; SM120f: {{.*VIADD.*}}
+
+*/

cccl_upstream/libcudacxx/test/simd_codegen/integer/bitwise_u16x2_u8x4.cu

@@ -0,0 +1,95 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+namespace simd = cuda::std::simd;
+
+using cuda::std::uint16_t;
+using cuda::std::uint8_t;
+
+using Vec_u16_x2 = simd::basic_vec<uint16_t, simd::fixed_size<2>>;
+using Vec_u8_x4  = simd::basic_vec<uint8_t, simd::fixed_size<4>>;
+
+__device__ void test_bitwise_and_u16_x2(Vec_u16_x2& out, Vec_u16_x2& lhs, Vec_u16_x2& rhs)
+{
+  out = lhs & rhs;
+}
+
+__device__ void test_bitwise_or_u16_x2(Vec_u16_x2& out, Vec_u16_x2& lhs, Vec_u16_x2& rhs)
+{
+  out = lhs | rhs;
+}
+
+__device__ void test_bitwise_xor_u16_x2(Vec_u16_x2& out, Vec_u16_x2& lhs, Vec_u16_x2& rhs)
+{
+  out = lhs ^ rhs;
+}
+
+__device__ void test_bitwise_not_u16_x2(Vec_u16_x2& out, Vec_u16_x2& in)
+{
+  out = ~in;
+}
+
+__device__ void test_bitwise_and_u8_x4(Vec_u8_x4& out, Vec_u8_x4& lhs, Vec_u8_x4& rhs)
+{
+  out = lhs & rhs;
+}
+
+__device__ void test_bitwise_or_u8_x4(Vec_u8_x4& out, Vec_u8_x4& lhs, Vec_u8_x4& rhs)
+{
+  out = lhs | rhs;
+}
+
+__device__ void test_bitwise_xor_u8_x4(Vec_u8_x4& out, Vec_u8_x4& lhs, Vec_u8_x4& rhs)
+{
+  out = lhs ^ rhs;
+}
+
+__device__ void test_bitwise_not_u8_x4(Vec_u8_x4& out, Vec_u8_x4& in)
+{
+  out = ~in;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_bitwise_not_u8_x4.*}}
+; SMXX-NOT: {{.*(LD\.E\.U(8|16)|PRMT|SHF|I2I|IMAD\.SHL).*}}
+; SMXX: {{.*LOP3.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_bitwise_xor_u8_x4.*}}
+; SMXX-NOT: {{.*(LD\.E\.U(8|16)|PRMT|SHF|I2I|IMAD\.SHL).*}}
+; SMXX: {{.*LOP3.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_bitwise_or_u8_x4.*}}
+; SMXX-NOT: {{.*(LD\.E\.U(8|16)|PRMT|SHF|I2I|IMAD\.SHL).*}}
+; SMXX: {{.*LOP3.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_bitwise_and_u8_x4.*}}
+; SMXX-NOT: {{.*(LD\.E\.U(8|16)|PRMT|SHF|I2I|IMAD\.SHL).*}}
+; SMXX: {{.*LOP3.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_bitwise_not_u16_x2.*}}
+; SMXX-NOT: {{.*(LD\.E\.U(8|16)|PRMT|SHF|I2I|IMAD\.SHL).*}}
+; SMXX: {{.*LOP3.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_bitwise_xor_u16_x2.*}}
+; SMXX-NOT: {{.*(LD\.E\.U(8|16)|PRMT|SHF|I2I|IMAD\.SHL).*}}
+; SMXX: {{.*LOP3.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_bitwise_or_u16_x2.*}}
+; SMXX-NOT: {{.*(LD\.E\.U(8|16)|PRMT|SHF|I2I|IMAD\.SHL).*}}
+; SMXX: {{.*LOP3.*}}
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_bitwise_and_u16_x2.*}}
+; SMXX-NOT: {{.*(LD\.E\.U(8|16)|PRMT|SHF|I2I|IMAD\.SHL).*}}
+; SMXX: {{.*LOP3.*}}
+
+*/