[INFRA] Import NVIDIA/CCCL upstream as optimization reference library

CCCL (CUDA C++ Core Libraries) provides:
- CUB: device/block/warp-level GPU primitives (reduce, scan, sort, topk)
- Thrust: high-level parallel algorithms (transform_reduce, sort, scan)
- libcudacxx: CUDA C++ standard library (atomics, barriers, memory)
- cudax: experimental features (memory resources, allocators)
- Tuning policies: per-SM hardware-specific algorithm parameters

Competition optimization vectors mapped to CCCL:
- Output TPS (83% weight): warp_reduce, block_reduce, device_topk
- Input TPS (14% weight): device_scan, block_load, prefetch
- Cache TPS (3% weight): prefix caching strategy patterns
- Memory (0.9 util): pooled/cached/buddy allocators

Source: https://github.com/NVIDIA/cccl (shallow clone, HEAD only)
License: Apache-2.0

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/decrement_f32x2.cu

@@ -0,0 +1,31 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+namespace simd = cuda::std::simd;
+
+using Vec_f32_x4 = simd::basic_vec<float, simd::fixed_size<4>>;
+
+__device__ Vec_f32_x4 test_operator_decrement_f32_x4(Vec_f32_x4 vec)
+{
+  --vec;
+  return vec;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_decrement_f32_x4.*}}
+; SM100: {{.*FADD2.*}}
+; SM100: {{.*FADD2.*}}
+; SM103: {{.*FADD2.*}}
+; SM103: {{.*FADD2.*}}
+
+*/

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/fma_bf16.cu

@@ -0,0 +1,38 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+#if _CCCL_HAS_NVBF16()
+
+#  include <cuda_bf16.h>
+
+namespace simd = cuda::std::simd;
+
+using Vec_bf16_x4 = simd::basic_vec<__nv_bfloat16, simd::fixed_size<4>>;
+
+__device__ Vec_bf16_x4 test_fma_bf16_x4(Vec_bf16_x4 lhs, Vec_bf16_x4 rhs, Vec_bf16_x4 add)
+{
+  return lhs * rhs + add;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_fma_bf16_x4.*}}
+; SM80: {{.*HFMA2.*BF16.*}}
+; SM80: {{.*HFMA2.*BF16.*}}
+; SM90: {{.*HFMA2.*BF16.*}}
+; SM90: {{.*HFMA2.*BF16.*}}
+; SM1XX: {{.*HFMA2.*BF16.*}}
+; SM1XX: {{.*HFMA2.*BF16.*}}
+
+*/
+
+#endif // _CCCL_HAS_NVBF16()

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/fma_f16.cu

@@ -0,0 +1,38 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+#if _CCCL_HAS_NVFP16()
+
+#  include <cuda_fp16.h>
+
+namespace simd = cuda::std::simd;
+
+using Vec_f16_x4 = simd::basic_vec<__half, simd::fixed_size<4>>;
+
+__device__ Vec_f16_x4 test_fma_f16_x4(Vec_f16_x4 lhs, Vec_f16_x4 rhs, Vec_f16_x4 add)
+{
+  return lhs * rhs + add;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_fma_f16_x4.*}}
+; SM80: {{.*HFMA2.*}}
+; SM80: {{.*HFMA2.*}}
+; SM90: {{.*HFMA2.*}}
+; SM90: {{.*HFMA2.*}}
+; SM1XX: {{.*HFMA2.*}}
+; SM1XX: {{.*HFMA2.*}}
+
+*/
+
+#endif // _CCCL_HAS_NVFP16()

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/fma_f32x2.cu

@@ -0,0 +1,30 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+namespace simd = cuda::std::simd;
+
+using Vec_f32_x4 = simd::basic_vec<float, simd::fixed_size<4>>;
+
+__device__ Vec_f32_x4 test_fma_f32_x4(Vec_f32_x4 lhs, Vec_f32_x4 rhs, Vec_f32_x4 add)
+{
+  return simd::fma(lhs, rhs, add);
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_fma_f32_x4.*}}
+; SM100: {{.*FFMA2.*}}
+; SM100: {{.*FFMA2.*}}
+; SM103: {{.*FFMA2.*}}
+; SM103: {{.*FFMA2.*}}
+
+*/

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/increment_f32x2.cu

@@ -0,0 +1,31 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+namespace simd = cuda::std::simd;
+
+using Vec_f32_x4 = simd::basic_vec<float, simd::fixed_size<4>>;
+
+__device__ Vec_f32_x4 test_operator_increment_f32_x4(Vec_f32_x4 vec)
+{
+  ++vec;
+  return vec;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_increment_f32_x4.*}}
+; SM100: {{.*FADD2.*}}
+; SM100: {{.*FADD2.*}}
+; SM103: {{.*FADD2.*}}
+; SM103: {{.*FADD2.*}}
+
+*/

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/less_bf16.cu

@@ -0,0 +1,41 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+#if _CCCL_HAS_NVBF16()
+
+#  include <cuda_bf16.h>
+
+namespace simd = cuda::std::simd;
+
+using Vec_bf16_x4  = simd::basic_vec<__nv_bfloat16, simd::fixed_size<4>>;
+using Mask_bf16_x4 = Vec_bf16_x4::mask_type;
+
+__device__ Mask_bf16_x4 test_less_bf16_x4(Vec_bf16_x4 lhs, Vec_bf16_x4 rhs)
+{
+  return lhs < rhs;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_less_bf16_x4.*}}
+; SM80: {{.*FSETP\.LT.*}}
+; SM80: {{.*FSETP\.LT.*}}
+; SM80: {{.*FSETP\.LT.*}}
+; SM80: {{.*FSETP\.LT.*}}
+; SM90: {{.*HSETP2.*BF16.*}}
+; SM90: {{.*HSETP2.*BF16.*}}
+; SM1XX: {{.*HSETP2.*BF16.*}}
+; SM1XX: {{.*HSETP2.*BF16.*}}
+
+*/
+
+#endif // _CCCL_HAS_NVBF16()

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/less_f16.cu

@@ -0,0 +1,39 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+#if _CCCL_HAS_NVFP16()
+
+#  include <cuda_fp16.h>
+
+namespace simd = cuda::std::simd;
+
+using Vec_f16_x4  = simd::basic_vec<__half, simd::fixed_size<4>>;
+using Mask_f16_x4 = Vec_f16_x4::mask_type;
+
+__device__ Mask_f16_x4 test_less_f16_x4(Vec_f16_x4 lhs, Vec_f16_x4 rhs)
+{
+  return lhs < rhs;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_less_f16_x4.*}}
+; SM80: {{.*HSETP2.*}}
+; SM80: {{.*HSETP2.*}}
+; SM90: {{.*HSETP2.*}}
+; SM90: {{.*HSETP2.*}}
+; SM1XX: {{.*HSETP2.*}}
+; SM1XX: {{.*HSETP2.*}}
+
+*/
+
+#endif // _CCCL_HAS_NVFP16()

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/minus_f32x2.cu

@@ -0,0 +1,30 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+namespace simd = cuda::std::simd;
+
+using Vec_f32_x4 = simd::basic_vec<float, simd::fixed_size<4>>;
+
+__device__ Vec_f32_x4 test_operator_minus_f32_x4(Vec_f32_x4 lhs, Vec_f32_x4 rhs)
+{
+  return lhs - rhs;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_minus_f32_x4.*}}
+; SM100: {{.*FADD2.*}}
+; SM100: {{.*FADD2.*}}
+; SM103: {{.*FADD2.*}}
+; SM103: {{.*FADD2.*}}
+
+*/

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/multiplies_bf16.cu

@@ -0,0 +1,38 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+#if _CCCL_HAS_NVBF16()
+
+#  include <cuda_bf16.h>
+
+namespace simd = cuda::std::simd;
+
+using Vec_bf16_x4 = simd::basic_vec<__nv_bfloat16, simd::fixed_size<4>>;
+
+__device__ Vec_bf16_x4 test_operator_multiplies_bf16_x4(Vec_bf16_x4 lhs, Vec_bf16_x4 rhs)
+{
+  return lhs * rhs;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_multiplies_bf16_x4.*}}
+; SM80: {{.*HFMA2.*BF16.*}}
+; SM80: {{.*HFMA2.*BF16.*}}
+; SM90: {{.*HFMA2.*BF16.*}}
+; SM90: {{.*HMUL2.*BF16.*}}
+; SM1XX: {{.*HFMA2.*BF16.*}}
+; SM1XX: {{.*HMUL2.*BF16.*}}
+
+*/
+
+#endif // _CCCL_HAS_NVBF16()

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/multiplies_f16.cu

@@ -0,0 +1,38 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+#if _CCCL_HAS_NVFP16()
+
+#  include <cuda_fp16.h>
+
+namespace simd = cuda::std::simd;
+
+using Vec_f16_x4 = simd::basic_vec<__half, simd::fixed_size<4>>;
+
+__device__ Vec_f16_x4 test_operator_multiplies_f16_x4(Vec_f16_x4 lhs, Vec_f16_x4 rhs)
+{
+  return lhs * rhs;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_multiplies_f16_x4.*}}
+; SM80: {{.*(HMUL2|HFMA2).*}}
+; SM80: {{.*(HMUL2|HFMA2).*}}
+; SM90: {{.*(HMUL2|HFMA2).*}}
+; SM90: {{.*(HMUL2|HFMA2).*}}
+; SM1XX: {{.*(HMUL2|HFMA2).*}}
+; SM1XX: {{.*(HMUL2|HFMA2).*}}
+
+*/
+
+#endif // _CCCL_HAS_NVFP16()

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/plus_bf16.cu

@@ -0,0 +1,38 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+#if _CCCL_HAS_NVBF16()
+
+#  include <cuda_bf16.h>
+
+namespace simd = cuda::std::simd;
+
+using Vec_bf16_x4 = simd::basic_vec<__nv_bfloat16, simd::fixed_size<4>>;
+
+__device__ Vec_bf16_x4 test_operator_plus_bf16_x4(Vec_bf16_x4 lhs, Vec_bf16_x4 rhs)
+{
+  return lhs + rhs;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_plus_bf16_x4.*}}
+; SM80: {{.*HFMA2.*BF16.*}}
+; SM80: {{.*HFMA2.*BF16.*}}
+; SM90: {{.*HFMA2.*BF16.*}}
+; SM90: {{.*HADD2.*BF16.*}}
+; SM1XX: {{.*HFMA2.*BF16.*}}
+; SM1XX: {{.*HADD2.*BF16.*}}
+
+*/
+
+#endif // _CCCL_HAS_NVBF16()

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/plus_f16.cu

@@ -0,0 +1,34 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+#if _CCCL_HAS_NVFP16()
+
+#  include <cuda_fp16.h>
+
+namespace simd = cuda::std::simd;
+
+using Vec_f16_x4 = simd::basic_vec<__half, simd::fixed_size<4>>;
+
+__device__ Vec_f16_x4 test_operator_plus_f16_x4(Vec_f16_x4 lhs, Vec_f16_x4 rhs)
+{
+  return lhs + rhs;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_plus_f16_x4.*}}
+; SMXX: {{.*(HADD2|HFMA2).*}}
+; SMXX: {{.*(HADD2|HFMA2).*}}
+
+*/
+
+#endif // _CCCL_HAS_NVFP16()

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/plus_f32x2.cu

@@ -0,0 +1,30 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+namespace simd = cuda::std::simd;
+
+using Vec_f32_x4 = simd::basic_vec<float, simd::fixed_size<4>>;
+
+__device__ Vec_f32_x4 test_operator_plus_f32_x4(Vec_f32_x4 lhs, Vec_f32_x4 rhs)
+{
+  return lhs + rhs;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_plus_f32_x4.*}}
+; SM100: {{.*FADD2.*}}
+; SM100: {{.*FADD2.*}}
+; SM103: {{.*FADD2.*}}
+; SM103: {{.*FADD2.*}}
+
+*/

cccl_upstream/libcudacxx/test/simd_codegen/floating_point/unary_minus_f32x2.cu

@@ -0,0 +1,30 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of libcu++ in the CUDA C++ Core Libraries,
+// under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+//
+//===----------------------------------------------------------------------===//
+
+#include <cuda/std/__simd_> // IWYU pragma: keep
+
+namespace simd = cuda::std::simd;
+
+using Vec_f32_x4 = simd::basic_vec<float, simd::fixed_size<4>>;
+
+__device__ Vec_f32_x4 test_operator_unary_minus_f32_x4(Vec_f32_x4 in)
+{
+  return -in;
+}
+
+/*
+
+; SMXX-LABEL: {{[[:space:]]*}}Function : {{.*test_operator_unary_minus_f32_x4.*}}
+; SM100: {{.*FADD2.*}}
+; SM100: {{.*FADD2.*}}
+; SM103: {{.*FADD2.*}}
+; SM103: {{.*FADD2.*}}
+
+*/