feat(cccl): integrate missing CCCL directories — python/, ci/, .agent/, docs/, test/
Sparse-checkout from NVIDIA/cccl main branch to complete cccl_upstream: Added: - python/cuda_cccl/ (226 files) — Python bindings for device-level algorithms Critical for muh toolchain: cuda.compute.reduce_into, scan, radix_sort, etc. Includes 204 .py files with full test coverage for all 27 algorithms - ci/ (163 files) — Build/test infrastructure build_cub.sh, test_cub.sh, build_and_test_targets.sh, matrix.yaml Directly maps to our [INFRA-CI] and [INFRA-BUILD] items - .agent/skills/ (7 files) — NVIDIA's own agent skills for CCCL cccl-style/SKILL.md, cccl-test/SKILL.md, sass-diff/SKILL.md - docs/ (491 files) — Official CCCL documentation CI references, CMake guides, Python compute docs, libcudacxx PTX docs - test/ (12 files) — Top-level integration tests (cuda_smoke, stdpar) - Root configs: .clang-format, .clang-tidy, CONTRIBUTING.md, pyproject.toml - CLAUDE.md symlink → AGENTS.md (NVIDIA's standard) cccl_upstream now mirrors full NVIDIA/cccl structure: Before: 42M (cub + thrust + libcudacxx + cudax + c + examples + benchmarks) After: 53M (+python +ci +docs +.agent +test +configs) This completes the CCCL base needed for: - [muh-bench] items: ci/util/build_and_test_targets.sh for targeted builds - [CCCL-verify] items: python/cuda_cccl/tests/ as reference implementations - [CCCL-test] items: ci/test_cub.sh, ci/test_thrust.sh - Agent workflow: .agent/skills/ for consistent style and test patterns
This commit is contained in:
muh-bot
@@ -0,0 +1,16 @@
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.. _libcudacxx-ptx-instructions-barrier-cluster:
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barrier.cluster
|
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===============
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- PTX ISA:
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`barrier.cluster <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-barrier-cluster>`__
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|
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Similar functionality is provided through the builtins
|
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``__cluster_barrier_arrive(), __cluster_barrier_arrive_relaxed(), __cluster_barrier_wait()``,
|
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as well as the ``cooperative_groups::cluster_group``
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`API <https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#cluster-group>`__.
|
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|
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The ``.aligned`` variants of the instructions are not exposed.
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|
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.. include:: generated/barrier_cluster.rst
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9
cccl_upstream/docs/libcudacxx/ptx/instructions/bfind.rst
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9
cccl_upstream/docs/libcudacxx/ptx/instructions/bfind.rst
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.. _libcudacxx-ptx-instructions-bfind:
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bfind
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=====
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- PTX ISA:
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`bfind <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-bfind>`__
|
||||
|
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.. include:: generated/bfind.rst
|
||||
9
cccl_upstream/docs/libcudacxx/ptx/instructions/bmsk.rst
Normal file
9
cccl_upstream/docs/libcudacxx/ptx/instructions/bmsk.rst
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.. _libcudacxx-ptx-instructions-bmsk:
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|
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bmsk
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====
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||||
|
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- PTX ISA:
|
||||
`bmsk <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-bmsk>`__
|
||||
|
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.. include:: generated/bmsk.rst
|
||||
@@ -0,0 +1,11 @@
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.. _libcudacxx-ptx-instructions-clusterlaunchcontrol:
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|
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clusterlaunchcontrol
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====================
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|
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- PTX ISA:
|
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`clusterlaunchcontrol.try_cancel <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel>`__
|
||||
- PTX ISA:
|
||||
`clusterlaunchcontrol.query_cancel <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-query-cancel>`__
|
||||
|
||||
.. include:: generated/clusterlaunchcontrol.rst
|
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@@ -0,0 +1,30 @@
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.. _libcudacxx-ptx-instructions-cp-async-bulk:
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cp.async.bulk
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=============
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- PTX ISA:
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`cp.async.bulk <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk>`__
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Implementation notes
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--------------------
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**NOTE.** Both ``srcMem`` and ``dstMem`` must be 16-byte aligned, and
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``size`` must be a multiple of 16.
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Changelog
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---------
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- In earlier versions, ``cp_async_bulk_multicast`` was enabled for
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SM_90. This has been changed to SM_90a.
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|
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|
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Unicast
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-------
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|
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.. include:: generated/cp_async_bulk.rst
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|
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Multicast
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---------
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|
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.. include:: generated/cp_async_bulk_multicast.rst
|
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@@ -0,0 +1,9 @@
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.. _libcudacxx-ptx-instructions-cp-async-bulk-commit_group:
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|
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cp.async.bulk.commit_group
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||||
==========================
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|
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- PTX ISA:
|
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`cp.async.bulk.commit_group <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-commit-group>`__
|
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|
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.. include:: generated/cp_async_bulk_commit_group.rst
|
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@@ -0,0 +1,28 @@
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.. _libcudacxx-ptx-instructions-cp-async-bulk-tensor:
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||||
|
||||
cp.async.bulk.tensor
|
||||
====================
|
||||
|
||||
- PTX ISA:
|
||||
`cp.async.bulk.tensor <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor>`__
|
||||
|
||||
Changelog
|
||||
---------
|
||||
|
||||
- In earlier versions, ``cp_async_bulk_tensor_multicast`` was enabled
|
||||
for SM_90. This has been changed to SM_90a.
|
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|
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Unicast
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||||
-------
|
||||
|
||||
.. include:: generated/cp_async_bulk_tensor.rst
|
||||
|
||||
Multicast
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---------
|
||||
|
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.. include:: generated/cp_async_bulk_tensor_multicast.rst
|
||||
|
||||
Scatter / Gather
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----------------
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.. include:: generated/cp_async_bulk_tensor_gather_scatter.rst
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@@ -0,0 +1,9 @@
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.. _libcudacxx-ptx-instructions-cp-async-bulk-wait_group:
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|
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cp.async.bulk.wait_group
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========================
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|
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- PTX ISA:
|
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`cp.async.bulk.wait_group <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-wait-group>`__
|
||||
|
||||
.. include:: generated/cp_async_bulk_wait_group.rst
|
||||
@@ -0,0 +1,10 @@
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.. _libcudacxx-ptx-instructions-cp-async-mbarrier-arrive:
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|
||||
cp.async.mbarrier.arrive
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========================
|
||||
|
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- PTX ISA:
|
||||
`cp.async.mbarrier.arrive <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-cp-async-mbarrier-arrive>`__
|
||||
|
||||
.. include:: generated/cp_async_mbarrier_arrive.rst
|
||||
.. include:: generated/cp_async_mbarrier_arrive_noinc.rst
|
||||
@@ -0,0 +1,61 @@
|
||||
.. _libcudacxx-ptx-instructions-cp-reduce-async-bulk:
|
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|
||||
cp.reduce.async.bulk
|
||||
====================
|
||||
|
||||
- PTX ISA:
|
||||
`cp.reduce.async.bulk <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-reduce-async-bulk>`__
|
||||
|
||||
|
||||
Integer and floating point instructions
|
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---------------------------------------
|
||||
|
||||
.. include:: generated/cp_reduce_async_bulk.rst
|
||||
|
||||
Emulation of ``.s64`` instruction
|
||||
---------------------------------
|
||||
|
||||
PTX does not currently (CTK 12.3) expose
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``cp.reduce.async.bulk.add.s64``. This exposure is emulated in
|
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``cuda::ptx`` using:
|
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.. code:: cuda
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|
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// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.u64 [dstMem], [srcMem], size, [rdsmem_bar]; // 2. PTX ISA 80, SM_90
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// .dst = { .shared::cluster }
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||||
// .src = { .shared::cta }
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||||
// .type = { .s64 }
|
||||
// .op = { .add }
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||||
template <typename=void>
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__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
int64_t* dstMem,
|
||||
const int64_t* srcMem,
|
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uint32_t size,
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uint64_t* rdsmem_bar);
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.u64 [dstMem], [srcMem], size; // 6. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .s64 }
|
||||
// .op = { .add }
|
||||
template <typename=void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
int64_t* dstMem,
|
||||
const int64_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
FP16 instructions
|
||||
-----------------
|
||||
|
||||
.. include:: generated/cp_reduce_async_bulk_f16.rst
|
||||
|
||||
BF16 instructions
|
||||
-----------------
|
||||
|
||||
.. include:: generated/cp_reduce_async_bulk_bf16.rst
|
||||
@@ -0,0 +1,9 @@
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||||
.. _libcudacxx-ptx-instructions-cp-reduce-async-bulk-tensor:
|
||||
|
||||
cp.reduce.async.bulk.tensor
|
||||
===========================
|
||||
|
||||
- PTX ISA:
|
||||
`cp.reduce.async.bulk.tensor <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-reduce-async-bulk-tensor>`__
|
||||
|
||||
.. include:: generated/cp_reduce_async_bulk_tensor.rst
|
||||
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-elect_sync:
|
||||
|
||||
elect.sync
|
||||
==========
|
||||
|
||||
- PTX ISA:
|
||||
`elect.sync <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-elect-sync>`__
|
||||
|
||||
.. include:: generated/elect_sync.rst
|
||||
9
cccl_upstream/docs/libcudacxx/ptx/instructions/exit.rst
Normal file
9
cccl_upstream/docs/libcudacxx/ptx/instructions/exit.rst
Normal file
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-exit:
|
||||
|
||||
exit
|
||||
====
|
||||
|
||||
- PTX ISA:
|
||||
`exit <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#control-flow-instructions-exit>`__
|
||||
|
||||
.. include:: generated/exit.rst
|
||||
45
cccl_upstream/docs/libcudacxx/ptx/instructions/fence.rst
Normal file
45
cccl_upstream/docs/libcudacxx/ptx/instructions/fence.rst
Normal file
@@ -0,0 +1,45 @@
|
||||
.. _libcudacxx-ptx-instructions-fence:
|
||||
|
||||
fence
|
||||
=====
|
||||
|
||||
- PTX ISA:
|
||||
`fence <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-membar-fence>`__
|
||||
|
||||
.. _fence-1:
|
||||
|
||||
fence
|
||||
-----
|
||||
|
||||
.. include:: generated/fence.rst
|
||||
|
||||
fence.sync_restrict
|
||||
-------------------
|
||||
|
||||
.. include:: generated/fence_sync_restrict.rst
|
||||
|
||||
fence.mbarrier_init
|
||||
-------------------
|
||||
|
||||
.. include:: generated/fence_mbarrier_init.rst
|
||||
|
||||
fence.proxy.alias
|
||||
-----------------
|
||||
|
||||
.. include:: generated/fence_proxy_alias.rst
|
||||
|
||||
fence.proxy.async
|
||||
-----------------
|
||||
|
||||
|
||||
.. include:: generated/fence_proxy_async.rst
|
||||
|
||||
fence.proxy.async.sync_restrict
|
||||
-------------------------------
|
||||
|
||||
.. include:: generated/fence_proxy_async_generic_sync_restrict.rst
|
||||
|
||||
fence.proxy.tensormap
|
||||
---------------------
|
||||
|
||||
.. include:: generated/fence_proxy_tensormap_generic.rst
|
||||
@@ -0,0 +1,53 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
barrier.cluster.arrive
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// barrier.cluster.arrive; // PTX ISA 78, SM_90
|
||||
// Marked volatile and as clobbering memory
|
||||
template <typename = void>
|
||||
__device__ static inline void barrier_cluster_arrive();
|
||||
|
||||
barrier.cluster.wait
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// barrier.cluster.wait; // PTX ISA 78, SM_90
|
||||
// Marked volatile and as clobbering memory
|
||||
template <typename = void>
|
||||
__device__ static inline void barrier_cluster_wait();
|
||||
|
||||
barrier.cluster.arrive.release
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// barrier.cluster.arrive.sem; // PTX ISA 80, SM_90
|
||||
// .sem = { .release }
|
||||
// Marked volatile and as clobbering memory
|
||||
template <typename = void>
|
||||
__device__ static inline void barrier_cluster_arrive(
|
||||
cuda::ptx::sem_release_t);
|
||||
|
||||
barrier.cluster.arrive.relaxed
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// barrier.cluster.arrive.sem; // PTX ISA 80, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// Marked volatile
|
||||
template <typename = void>
|
||||
__device__ static inline void barrier_cluster_arrive(
|
||||
cuda::ptx::sem_relaxed_t);
|
||||
|
||||
barrier.cluster.wait.acquire
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// barrier.cluster.wait.sem; // PTX ISA 80, SM_90
|
||||
// .sem = { .acquire }
|
||||
// Marked volatile and as clobbering memory
|
||||
template <typename = void>
|
||||
__device__ static inline void barrier_cluster_wait(
|
||||
cuda::ptx::sem_acquire_t);
|
||||
@@ -0,0 +1,74 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
bfind.u32
|
||||
^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// bfind.u32 dest, a_reg; // PTX ISA 20, SM_50
|
||||
template <typename U32, enable_if_t<sizeof(U32) == 4 && is_integral_v<U32> && is_unsigned_v<U32>, bool> = true>
|
||||
__device__ static inline uint32_t bfind(
|
||||
U32 a_reg);
|
||||
|
||||
bfind.shiftamt.u32
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// bfind.shiftamt.u32 dest, a_reg; // PTX ISA 20, SM_50
|
||||
template <typename U32, enable_if_t<sizeof(U32) == 4 && is_integral_v<U32> && is_unsigned_v<U32>, bool> = true>
|
||||
__device__ static inline uint32_t bfind_shiftamt(
|
||||
U32 a_reg);
|
||||
|
||||
bfind.u64
|
||||
^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// bfind.u64 dest, a_reg; // PTX ISA 20, SM_50
|
||||
template <typename U64, enable_if_t<sizeof(U64) == 8 && is_integral_v<U64> && is_unsigned_v<U64>, bool> = true>
|
||||
__device__ static inline uint32_t bfind(
|
||||
U64 a_reg);
|
||||
|
||||
bfind.shiftamt.u64
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// bfind.shiftamt.u64 dest, a_reg; // PTX ISA 20, SM_50
|
||||
template <typename U64, enable_if_t<sizeof(U64) == 8 && is_integral_v<U64> && is_unsigned_v<U64>, bool> = true>
|
||||
__device__ static inline uint32_t bfind_shiftamt(
|
||||
U64 a_reg);
|
||||
|
||||
bfind.s32
|
||||
^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// bfind.s32 dest, a_reg; // PTX ISA 20, SM_50
|
||||
template <typename S32, enable_if_t<sizeof(S32) == 4 && is_integral_v<S32> && is_signed_v<S32>, bool> = true>
|
||||
__device__ static inline uint32_t bfind(
|
||||
S32 a_reg);
|
||||
|
||||
bfind.shiftamt.s32
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// bfind.shiftamt.s32 dest, a_reg; // PTX ISA 20, SM_50
|
||||
template <typename S32, enable_if_t<sizeof(S32) == 4 && is_integral_v<S32> && is_signed_v<S32>, bool> = true>
|
||||
__device__ static inline uint32_t bfind_shiftamt(
|
||||
S32 a_reg);
|
||||
|
||||
bfind.s64
|
||||
^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// bfind.s64 dest, a_reg; // PTX ISA 20, SM_50
|
||||
template <typename S64, enable_if_t<sizeof(S64) == 8 && is_integral_v<S64> && is_signed_v<S64>, bool> = true>
|
||||
__device__ static inline uint32_t bfind(
|
||||
S64 a_reg);
|
||||
|
||||
bfind.shiftamt.s64
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// bfind.shiftamt.s64 dest, a_reg; // PTX ISA 20, SM_50
|
||||
template <typename S64, enable_if_t<sizeof(S64) == 8 && is_integral_v<S64> && is_signed_v<S64>, bool> = true>
|
||||
__device__ static inline uint32_t bfind_shiftamt(
|
||||
S64 a_reg);
|
||||
@@ -0,0 +1,22 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
bmsk.clamp.b32
|
||||
^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// bmsk.clamp.b32 dest, a_reg, b_reg; // PTX ISA 76, SM_70
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t bmsk_clamp(
|
||||
uint32_t a_reg,
|
||||
uint32_t b_reg);
|
||||
|
||||
bmsk.wrap.b32
|
||||
^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// bmsk.wrap.b32 dest, a_reg, b_reg; // PTX ISA 76, SM_70
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t bmsk_wrap(
|
||||
uint32_t a_reg,
|
||||
uint32_t b_reg);
|
||||
@@ -0,0 +1,68 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [addr], [smem_bar]; // PTX ISA 86, SM_100
|
||||
template <typename = void>
|
||||
__device__ static inline void clusterlaunchcontrol_try_cancel(
|
||||
void* addr,
|
||||
uint64_t* smem_bar);
|
||||
|
||||
clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 [addr], [smem_bar]; // PTX ISA 86, SM_100a, SM_110a
|
||||
template <typename = void>
|
||||
__device__ static inline void clusterlaunchcontrol_try_cancel_multicast(
|
||||
void* addr,
|
||||
uint64_t* smem_bar);
|
||||
|
||||
clusterlaunchcontrol.query_cancel.is_canceled.pred.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 pred_is_canceled, try_cancel_response; // PTX ISA 86, SM_100
|
||||
template <typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
|
||||
__device__ static inline bool clusterlaunchcontrol_query_cancel_is_canceled(
|
||||
B128 try_cancel_response);
|
||||
|
||||
clusterlaunchcontrol.query_cancel.get_first_ctaid::x.b32.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// clusterlaunchcontrol.query_cancel.get_first_ctaid::x.b32.b128 ret_dim, try_cancel_response; // PTX ISA 86, SM_100
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
|
||||
__device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_x(
|
||||
B128 try_cancel_response);
|
||||
|
||||
clusterlaunchcontrol.query_cancel.get_first_ctaid::y.b32.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// clusterlaunchcontrol.query_cancel.get_first_ctaid::y.b32.b128 ret_dim, try_cancel_response; // PTX ISA 86, SM_100
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
|
||||
__device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_y(
|
||||
B128 try_cancel_response);
|
||||
|
||||
clusterlaunchcontrol.query_cancel.get_first_ctaid::z.b32.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// clusterlaunchcontrol.query_cancel.get_first_ctaid::z.b32.b128 ret_dim, try_cancel_response; // PTX ISA 86, SM_100
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
|
||||
__device__ static inline B32 clusterlaunchcontrol_query_cancel_get_first_ctaid_z(
|
||||
B128 try_cancel_response);
|
||||
|
||||
clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 block_dim, try_cancel_response; // PTX ISA 86, SM_100
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
|
||||
__device__ static inline void clusterlaunchcontrol_query_cancel_get_first_ctaid(
|
||||
B32 (&block_dim)[4],
|
||||
B128 try_cancel_response);
|
||||
@@ -0,0 +1,99 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [smem_bar]; // PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* srcMem,
|
||||
const uint32_t& size,
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [smem_bar]; // PTX ISA 86, SM_90
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* srcMem,
|
||||
const uint32_t& size,
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes.ignore_oob
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes.ignore_oob [dstMem], [srcMem], size, ignoreBytesLeft, ignoreBytesRight, [smem_bar]; // PTX ISA 92, SM_90
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_ignore_oob(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* srcMem,
|
||||
const uint32_t& size,
|
||||
const uint32_t& ignoreBytesLeft,
|
||||
const uint32_t& ignoreBytesRight,
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [rdsmem_bar]; // PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
void* dstMem,
|
||||
const void* srcMem,
|
||||
const uint32_t& size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.async.bulk.global.shared::cta.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.dst.src.bulk_group [dstMem], [srcMem], size; // PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
void* dstMem,
|
||||
const void* srcMem,
|
||||
const uint32_t& size);
|
||||
|
||||
cp.async.bulk.global.shared::cta.bulk_group.cp_mask
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.dst.src.bulk_group.cp_mask [dstMem], [srcMem], size, byteMask; // PTX ISA 86, SM_100
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_cp_mask(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
void* dstMem,
|
||||
const void* srcMem,
|
||||
const uint32_t& size,
|
||||
const uint16_t& byteMask);
|
||||
@@ -0,0 +1,10 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
cp.async.bulk.commit_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.commit_group; // PTX ISA 80, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_commit_group();
|
||||
@@ -0,0 +1,19 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.dst.src.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [srcMem], size, [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_110a
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* srcMem,
|
||||
const uint32_t& size,
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
@@ -0,0 +1,417 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.1d.global.shared::cta.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.1d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
const void* srcMem);
|
||||
|
||||
cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.2d.global.shared::cta.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
const void* srcMem);
|
||||
|
||||
cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.3d.global.shared::cta.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.3d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
const void* srcMem);
|
||||
|
||||
cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.4d.global.shared::cta.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.4d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
const void* srcMem);
|
||||
|
||||
cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_90
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::1
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.cta_group::2
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.5d.global.shared::cta.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.5d.dst.src.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
const void* srcMem);
|
||||
@@ -0,0 +1,124 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor_tile_gather4(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.cta_group::1
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor_tile_gather4(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.cta_group::2
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cta }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor_tile_gather4(
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
uint64_t* smem_bar);
|
||||
|
||||
cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor_tile_gather4(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor_tile_gather4(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor_tile_gather4(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.2d.global.shared::cta.tile::scatter4.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile::scatter4.bulk_group [tensorMap, tensorCoords], [srcMem]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor_tile_scatter4(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
const void* srcMem);
|
||||
@@ -0,0 +1,277 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.1d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.2d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.3d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.4d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
|
||||
cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.tensor.5d.dst.src.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group [dstMem], [tensorMap, tensorCoords], [smem_bar], ctaMask; // PTX ISA 80, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .global }
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void cp_async_bulk_tensor(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
void* dstMem,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
uint64_t* smem_bar,
|
||||
const uint16_t& ctaMask);
|
||||
@@ -0,0 +1,20 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
cp.async.bulk.wait_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.wait_group N; // PTX ISA 80, SM_90
|
||||
template <int N32>
|
||||
__device__ static inline void cp_async_bulk_wait_group(
|
||||
cuda::ptx::n32_t<N32> N);
|
||||
|
||||
cp.async.bulk.wait_group.read
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.bulk.wait_group.read N; // PTX ISA 80, SM_90
|
||||
template <int N32>
|
||||
__device__ static inline void cp_async_bulk_wait_group_read(
|
||||
cuda::ptx::n32_t<N32> N);
|
||||
@@ -0,0 +1,11 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
cp.async.mbarrier.arrive.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.mbarrier.arrive.b64 [addr]; // PTX ISA 70, SM_80
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_mbarrier_arrive(
|
||||
uint64_t* addr);
|
||||
@@ -0,0 +1,11 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
cp.async.mbarrier.arrive.noinc.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.async.mbarrier.arrive.noinc.b64 [addr]; // PTX ISA 70, SM_80
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_async_mbarrier_arrive_noinc(
|
||||
uint64_t* addr);
|
||||
@@ -0,0 +1,645 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.and.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .b32 }
|
||||
// .op = { .and }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_and_op_t,
|
||||
B32* dstMem,
|
||||
const B32* srcMem,
|
||||
uint32_t size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.or.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .b32 }
|
||||
// .op = { .or }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_or_op_t,
|
||||
B32* dstMem,
|
||||
const B32* srcMem,
|
||||
uint32_t size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.xor.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .b32 }
|
||||
// .op = { .xor }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_xor_op_t,
|
||||
B32* dstMem,
|
||||
const B32* srcMem,
|
||||
uint32_t size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.min.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u32 }
|
||||
// .op = { .min }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_min_t,
|
||||
uint32_t* dstMem,
|
||||
const uint32_t* srcMem,
|
||||
uint32_t size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.max.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u32 }
|
||||
// .op = { .max }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_max_t,
|
||||
uint32_t* dstMem,
|
||||
const uint32_t* srcMem,
|
||||
uint32_t size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u32 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
uint32_t* dstMem,
|
||||
const uint32_t* srcMem,
|
||||
uint32_t size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.inc.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u32 }
|
||||
// .op = { .inc }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_inc_t,
|
||||
uint32_t* dstMem,
|
||||
const uint32_t* srcMem,
|
||||
uint32_t size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.dec.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u32 }
|
||||
// .op = { .dec }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_dec_t,
|
||||
uint32_t* dstMem,
|
||||
const uint32_t* srcMem,
|
||||
uint32_t size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.min.s32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .s32 }
|
||||
// .op = { .min }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_min_t,
|
||||
int32_t* dstMem,
|
||||
const int32_t* srcMem,
|
||||
uint32_t size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.max.s32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .s32 }
|
||||
// .op = { .max }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_max_t,
|
||||
int32_t* dstMem,
|
||||
const int32_t* srcMem,
|
||||
uint32_t size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.s32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .s32 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
int32_t* dstMem,
|
||||
const int32_t* srcMem,
|
||||
uint32_t size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.type [dstMem], [srcMem], size, [rdsmem_bar]; // 1. PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u64 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
uint64_t* dstMem,
|
||||
const uint64_t* srcMem,
|
||||
uint32_t size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.add.u64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.mbarrier::complete_tx::bytes.op.u64 [dstMem], [srcMem], size, [rdsmem_bar]; // 2. PTX ISA 80, SM_90
|
||||
// .dst = { .shared::cluster }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .s64 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
int64_t* dstMem,
|
||||
const int64_t* srcMem,
|
||||
uint32_t size,
|
||||
uint64_t* rdsmem_bar);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.and.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 3. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .b32, .b64 }
|
||||
// .op = { .and }
|
||||
template <typename Type>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_and_op_t,
|
||||
Type* dstMem,
|
||||
const Type* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.and.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 3. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .b32, .b64 }
|
||||
// .op = { .and }
|
||||
template <typename Type>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_and_op_t,
|
||||
Type* dstMem,
|
||||
const Type* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.or.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 3. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .b32, .b64 }
|
||||
// .op = { .or }
|
||||
template <typename Type>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_or_op_t,
|
||||
Type* dstMem,
|
||||
const Type* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.or.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 3. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .b32, .b64 }
|
||||
// .op = { .or }
|
||||
template <typename Type>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_or_op_t,
|
||||
Type* dstMem,
|
||||
const Type* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.xor.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 3. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .b32, .b64 }
|
||||
// .op = { .xor }
|
||||
template <typename Type>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_xor_op_t,
|
||||
Type* dstMem,
|
||||
const Type* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.xor.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 3. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .b32, .b64 }
|
||||
// .op = { .xor }
|
||||
template <typename Type>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_xor_op_t,
|
||||
Type* dstMem,
|
||||
const Type* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.min.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u32 }
|
||||
// .op = { .min }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_min_t,
|
||||
uint32_t* dstMem,
|
||||
const uint32_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.max.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u32 }
|
||||
// .op = { .max }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_max_t,
|
||||
uint32_t* dstMem,
|
||||
const uint32_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u32 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
uint32_t* dstMem,
|
||||
const uint32_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.inc.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u32 }
|
||||
// .op = { .inc }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_inc_t,
|
||||
uint32_t* dstMem,
|
||||
const uint32_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.dec.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u32 }
|
||||
// .op = { .dec }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_dec_t,
|
||||
uint32_t* dstMem,
|
||||
const uint32_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.min.s32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .s32 }
|
||||
// .op = { .min }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_min_t,
|
||||
int32_t* dstMem,
|
||||
const int32_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.max.s32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .s32 }
|
||||
// .op = { .max }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_max_t,
|
||||
int32_t* dstMem,
|
||||
const int32_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.add.s32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .s32 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
int32_t* dstMem,
|
||||
const int32_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.min.u64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u64 }
|
||||
// .op = { .min }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_min_t,
|
||||
uint64_t* dstMem,
|
||||
const uint64_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.max.u64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u64 }
|
||||
// .op = { .max }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_max_t,
|
||||
uint64_t* dstMem,
|
||||
const uint64_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .u64 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
uint64_t* dstMem,
|
||||
const uint64_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.min.s64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .s64 }
|
||||
// .op = { .min }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_min_t,
|
||||
int64_t* dstMem,
|
||||
const int64_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.max.s64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .s64 }
|
||||
// .op = { .max }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_max_t,
|
||||
int64_t* dstMem,
|
||||
const int64_t* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.add.f32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .f32 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
float* dstMem,
|
||||
const float* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.add.f64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .f64 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
double* dstMem,
|
||||
const double* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.add.u64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.u64 [dstMem], [srcMem], size; // 6. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .s64 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
int64_t* dstMem,
|
||||
const int64_t* srcMem,
|
||||
uint32_t size);
|
||||
@@ -0,0 +1,56 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.min.bf16
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .bf16 }
|
||||
// .op = { .min }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_min_t,
|
||||
__nv_bfloat16* dstMem,
|
||||
const __nv_bfloat16* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.max.bf16
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .bf16 }
|
||||
// .op = { .max }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_max_t,
|
||||
__nv_bfloat16* dstMem,
|
||||
const __nv_bfloat16* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.bf16
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.noftz.type [dstMem], [srcMem], size; // 5. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .bf16 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
__nv_bfloat16* dstMem,
|
||||
const __nv_bfloat16* srcMem,
|
||||
uint32_t size);
|
||||
@@ -0,0 +1,56 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.min.f16
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .f16 }
|
||||
// .op = { .min }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_min_t,
|
||||
__half* dstMem,
|
||||
const __half* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.max.f16
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.type [dstMem], [srcMem], size; // 4. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .f16 }
|
||||
// .op = { .max }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_max_t,
|
||||
__half* dstMem,
|
||||
const __half* srcMem,
|
||||
uint32_t size);
|
||||
|
||||
cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.f16
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.dst.src.bulk_group.op.noftz.type [dstMem], [srcMem], size; // 5. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .type = { .f16 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void cp_reduce_async_bulk(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_add_t,
|
||||
__half* dstMem,
|
||||
const __half* srcMem,
|
||||
uint32_t size);
|
||||
@@ -0,0 +1,682 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
cp.reduce.async.bulk.tensor.1d.global.shared::cta.add.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.1d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1a. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.1d.global.shared::cta.min.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.1d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1a. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.1d.global.shared::cta.max.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.1d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1a. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.1d.global.shared::cta.inc.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.1d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1a. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.1d.global.shared::cta.dec.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.1d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1a. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.1d.global.shared::cta.and.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.1d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1a. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.1d.global.shared::cta.or.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.1d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1a. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.1d.global.shared::cta.xor.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.1d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1a. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[1],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.2d.global.shared::cta.add.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.2d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1b. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.2d.global.shared::cta.min.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.2d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1b. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.2d.global.shared::cta.max.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.2d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1b. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.2d.global.shared::cta.inc.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.2d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1b. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.2d.global.shared::cta.dec.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.2d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1b. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.2d.global.shared::cta.and.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.2d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1b. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.2d.global.shared::cta.or.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.2d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1b. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.2d.global.shared::cta.xor.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.2d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1b. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[2],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.3d.global.shared::cta.add.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.3d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1c. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.3d.global.shared::cta.min.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.3d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1c. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.3d.global.shared::cta.max.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.3d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1c. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.3d.global.shared::cta.inc.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.3d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1c. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.3d.global.shared::cta.dec.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.3d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1c. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.3d.global.shared::cta.and.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.3d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1c. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.3d.global.shared::cta.or.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.3d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1c. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.3d.global.shared::cta.xor.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.3d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1c. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[3],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.4d.global.shared::cta.add.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.4d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1d. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.4d.global.shared::cta.min.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.4d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1d. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.4d.global.shared::cta.max.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.4d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1d. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.4d.global.shared::cta.inc.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.4d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1d. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.4d.global.shared::cta.dec.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.4d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1d. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.4d.global.shared::cta.and.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.4d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1d. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.4d.global.shared::cta.or.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.4d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1d. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.4d.global.shared::cta.xor.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.4d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1d. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[4],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.5d.global.shared::cta.add.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.5d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1e. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.5d.global.shared::cta.min.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.5d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1e. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.5d.global.shared::cta.max.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.5d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1e. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.5d.global.shared::cta.inc.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.5d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1e. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.5d.global.shared::cta.dec.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.5d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1e. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.5d.global.shared::cta.and.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.5d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1e. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.5d.global.shared::cta.or.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.5d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1e. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
const void* srcMem);
|
||||
|
||||
cp.reduce.async.bulk.tensor.5d.global.shared::cta.xor.tile.bulk_group
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// cp.reduce.async.bulk.tensor.5d.dst.src.op.tile.bulk_group [tensorMap, tensorCoords], [srcMem]; // 1e. PTX ISA 80, SM_90
|
||||
// .dst = { .global }
|
||||
// .src = { .shared::cta }
|
||||
// .op = { .add, .min, .max, .inc, .dec, .and, .or, .xor }
|
||||
template <cuda::ptx::dot_op Op>
|
||||
__device__ static inline void cp_reduce_async_bulk_tensor(
|
||||
cuda::ptx::space_global_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::op_t<Op> op,
|
||||
const void* tensorMap,
|
||||
const int32_t (&tensorCoords)[5],
|
||||
const void* srcMem);
|
||||
@@ -0,0 +1,11 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
elect.sync
|
||||
^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// elect.sync _|is_elected, membermask; // PTX ISA 80, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline bool elect_sync(
|
||||
const uint32_t& membermask);
|
||||
@@ -0,0 +1,10 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
exit
|
||||
^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// exit; // PTX ISA 10, SM_50
|
||||
template <typename = void>
|
||||
__device__ static inline void exit();
|
||||
@@ -0,0 +1,194 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
fence.sc.cta
|
||||
^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // 1. PTX ISA 60, SM_70
|
||||
// .sem = { .sc }
|
||||
// .scope = { .cta, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_sc_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.sc.gpu
|
||||
^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // 1. PTX ISA 60, SM_70
|
||||
// .sem = { .sc }
|
||||
// .scope = { .cta, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_sc_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.sc.sys
|
||||
^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // 1. PTX ISA 60, SM_70
|
||||
// .sem = { .sc }
|
||||
// .scope = { .cta, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_sc_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.sc.cluster
|
||||
^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // 2. PTX ISA 78, SM_90
|
||||
// .sem = { .sc }
|
||||
// .scope = { .cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_sc_t,
|
||||
cuda::ptx::scope_cluster_t);
|
||||
|
||||
fence.acq_rel.cta
|
||||
^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // 1. PTX ISA 60, SM_70
|
||||
// .sem = { .acq_rel }
|
||||
// .scope = { .cta, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_acq_rel_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.acq_rel.gpu
|
||||
^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // 1. PTX ISA 60, SM_70
|
||||
// .sem = { .acq_rel }
|
||||
// .scope = { .cta, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_acq_rel_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.acq_rel.sys
|
||||
^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // 1. PTX ISA 60, SM_70
|
||||
// .sem = { .acq_rel }
|
||||
// .scope = { .cta, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_acq_rel_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.acq_rel.cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // 2. PTX ISA 78, SM_90
|
||||
// .sem = { .acq_rel }
|
||||
// .scope = { .cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_acq_rel_t,
|
||||
cuda::ptx::scope_cluster_t);
|
||||
|
||||
fence.acquire.cta
|
||||
^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // PTX ISA 86, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.acquire.cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // PTX ISA 86, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.acquire.gpu
|
||||
^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // PTX ISA 86, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.acquire.sys
|
||||
^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // PTX ISA 86, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.release.cta
|
||||
^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // PTX ISA 86, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.release.cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // PTX ISA 86, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.release.gpu
|
||||
^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // PTX ISA 86, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.release.sys
|
||||
^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.scope; // PTX ISA 86, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
@@ -0,0 +1,14 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
fence.mbarrier_init.release.cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.mbarrier_init.sem.scope; // 3. PTX ISA 80, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline void fence_mbarrier_init(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_cluster_t);
|
||||
@@ -0,0 +1,10 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
fence.proxy.alias
|
||||
^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.alias; // 4. PTX ISA 75, SM_70
|
||||
template <typename = void>
|
||||
__device__ static inline void fence_proxy_alias();
|
||||
@@ -0,0 +1,40 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
fence.proxy.async
|
||||
^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.async; // 5. PTX ISA 80, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline void fence_proxy_async();
|
||||
|
||||
fence.proxy.async.global
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.async.space; // 6. PTX ISA 80, SM_90
|
||||
// .space = { .global, .shared::cluster, .shared::cta }
|
||||
template <cuda::ptx::dot_space Space>
|
||||
__device__ static inline void fence_proxy_async(
|
||||
cuda::ptx::space_t<Space> space);
|
||||
|
||||
fence.proxy.async.shared::cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.async.space; // 6. PTX ISA 80, SM_90
|
||||
// .space = { .global, .shared::cluster, .shared::cta }
|
||||
template <cuda::ptx::dot_space Space>
|
||||
__device__ static inline void fence_proxy_async(
|
||||
cuda::ptx::space_t<Space> space);
|
||||
|
||||
fence.proxy.async.shared::cta
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.async.space; // 6. PTX ISA 80, SM_90
|
||||
// .space = { .global, .shared::cluster, .shared::cta }
|
||||
template <cuda::ptx::dot_space Space>
|
||||
__device__ static inline void fence_proxy_async(
|
||||
cuda::ptx::space_t<Space> space);
|
||||
@@ -0,0 +1,30 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.async::generic.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .space = { .shared::cluster }
|
||||
// .scope = { .cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline void fence_proxy_async_generic_sync_restrict(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::scope_cluster_t);
|
||||
|
||||
fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.async::generic.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90
|
||||
// .sem = { .release }
|
||||
// .space = { .shared::cta }
|
||||
// .scope = { .cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline void fence_proxy_async_generic_sync_restrict(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::scope_cluster_t);
|
||||
@@ -0,0 +1,106 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
fence.proxy.tensormap::generic.release.cta
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.tensormap::generic.release.scope; // 7. PTX ISA 83, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence_proxy_tensormap_generic(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.proxy.tensormap::generic.release.cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.tensormap::generic.release.scope; // 7. PTX ISA 83, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence_proxy_tensormap_generic(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.proxy.tensormap::generic.release.gpu
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.tensormap::generic.release.scope; // 7. PTX ISA 83, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence_proxy_tensormap_generic(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.proxy.tensormap::generic.release.sys
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.tensormap::generic.release.scope; // 7. PTX ISA 83, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence_proxy_tensormap_generic(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope);
|
||||
|
||||
fence.proxy.tensormap::generic.acquire.cta
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.tensormap::generic.sem.scope [addr], size; // 8. PTX ISA 83, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <int N32, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence_proxy_tensormap_generic(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
const void* addr,
|
||||
cuda::ptx::n32_t<N32> size);
|
||||
|
||||
fence.proxy.tensormap::generic.acquire.cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.tensormap::generic.sem.scope [addr], size; // 8. PTX ISA 83, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <int N32, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence_proxy_tensormap_generic(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
const void* addr,
|
||||
cuda::ptx::n32_t<N32> size);
|
||||
|
||||
fence.proxy.tensormap::generic.acquire.gpu
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.tensormap::generic.sem.scope [addr], size; // 8. PTX ISA 83, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <int N32, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence_proxy_tensormap_generic(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
const void* addr,
|
||||
cuda::ptx::n32_t<N32> size);
|
||||
|
||||
fence.proxy.tensormap::generic.acquire.sys
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.proxy.tensormap::generic.sem.scope [addr], size; // 8. PTX ISA 83, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <int N32, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void fence_proxy_tensormap_generic(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
const void* addr,
|
||||
cuda::ptx::n32_t<N32> size);
|
||||
@@ -0,0 +1,30 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
fence.acquire.sync_restrict::shared::cluster.cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .space = { .shared::cluster }
|
||||
// .scope = { .cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline void fence_sync_restrict(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::space_cluster_t,
|
||||
cuda::ptx::scope_cluster_t);
|
||||
|
||||
fence.release.sync_restrict::shared::cta.cluster
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// fence.sem.sync_restrict::space.scope; // PTX ISA 86, SM_90
|
||||
// .sem = { .release }
|
||||
// .space = { .shared::cta }
|
||||
// .scope = { .cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline void fence_sync_restrict(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::space_shared_t,
|
||||
cuda::ptx::scope_cluster_t);
|
||||
@@ -0,0 +1,386 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
tid.x
|
||||
^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%tid.x; // PTX ISA 20
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_tid_x();
|
||||
|
||||
tid.y
|
||||
^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%tid.y; // PTX ISA 20
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_tid_y();
|
||||
|
||||
tid.z
|
||||
^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%tid.z; // PTX ISA 20
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_tid_z();
|
||||
|
||||
ntid.x
|
||||
^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%ntid.x; // PTX ISA 20
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_ntid_x();
|
||||
|
||||
ntid.y
|
||||
^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%ntid.y; // PTX ISA 20
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_ntid_y();
|
||||
|
||||
ntid.z
|
||||
^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%ntid.z; // PTX ISA 20
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_ntid_z();
|
||||
|
||||
laneid
|
||||
^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%laneid; // PTX ISA 13
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_laneid();
|
||||
|
||||
warpid
|
||||
^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%warpid; // PTX ISA 13
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_warpid();
|
||||
|
||||
nwarpid
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%nwarpid; // PTX ISA 20, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_nwarpid();
|
||||
|
||||
ctaid.x
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%ctaid.x; // PTX ISA 20
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_ctaid_x();
|
||||
|
||||
ctaid.y
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%ctaid.y; // PTX ISA 20
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_ctaid_y();
|
||||
|
||||
ctaid.z
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%ctaid.z; // PTX ISA 20
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_ctaid_z();
|
||||
|
||||
nctaid.x
|
||||
^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%nctaid.x; // PTX ISA 20
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_nctaid_x();
|
||||
|
||||
nctaid.y
|
||||
^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%nctaid.y; // PTX ISA 20
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_nctaid_y();
|
||||
|
||||
nctaid.z
|
||||
^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%nctaid.z; // PTX ISA 20
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_nctaid_z();
|
||||
|
||||
smid
|
||||
^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%smid; // PTX ISA 13
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_smid();
|
||||
|
||||
nsmid
|
||||
^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%nsmid; // PTX ISA 20, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_nsmid();
|
||||
|
||||
gridid
|
||||
^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u64 sreg_value, %%gridid; // PTX ISA 30
|
||||
template <typename = void>
|
||||
__device__ static inline uint64_t get_sreg_gridid();
|
||||
|
||||
is_explicit_cluster
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.pred sreg_value, %%is_explicit_cluster; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline bool get_sreg_is_explicit_cluster();
|
||||
|
||||
clusterid.x
|
||||
^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%clusterid.x; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_clusterid_x();
|
||||
|
||||
clusterid.y
|
||||
^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%clusterid.y; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_clusterid_y();
|
||||
|
||||
clusterid.z
|
||||
^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%clusterid.z; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_clusterid_z();
|
||||
|
||||
nclusterid.x
|
||||
^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%nclusterid.x; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_nclusterid_x();
|
||||
|
||||
nclusterid.y
|
||||
^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%nclusterid.y; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_nclusterid_y();
|
||||
|
||||
nclusterid.z
|
||||
^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%nclusterid.z; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_nclusterid_z();
|
||||
|
||||
cluster_ctaid.x
|
||||
^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%cluster_ctaid.x; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_cluster_ctaid_x();
|
||||
|
||||
cluster_ctaid.y
|
||||
^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%cluster_ctaid.y; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_cluster_ctaid_y();
|
||||
|
||||
cluster_ctaid.z
|
||||
^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%cluster_ctaid.z; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_cluster_ctaid_z();
|
||||
|
||||
cluster_nctaid.x
|
||||
^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%cluster_nctaid.x; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_cluster_nctaid_x();
|
||||
|
||||
cluster_nctaid.y
|
||||
^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%cluster_nctaid.y; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_cluster_nctaid_y();
|
||||
|
||||
cluster_nctaid.z
|
||||
^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%cluster_nctaid.z; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_cluster_nctaid_z();
|
||||
|
||||
cluster_ctarank
|
||||
^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%cluster_ctarank; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_cluster_ctarank();
|
||||
|
||||
cluster_nctarank
|
||||
^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%cluster_nctarank; // PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_cluster_nctarank();
|
||||
|
||||
lanemask_eq
|
||||
^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%lanemask_eq; // PTX ISA 20, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_lanemask_eq();
|
||||
|
||||
lanemask_le
|
||||
^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%lanemask_le; // PTX ISA 20, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_lanemask_le();
|
||||
|
||||
lanemask_lt
|
||||
^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%lanemask_lt; // PTX ISA 20, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_lanemask_lt();
|
||||
|
||||
lanemask_ge
|
||||
^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%lanemask_ge; // PTX ISA 20, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_lanemask_ge();
|
||||
|
||||
lanemask_gt
|
||||
^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%lanemask_gt; // PTX ISA 20, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_lanemask_gt();
|
||||
|
||||
clock
|
||||
^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%clock; // PTX ISA 10
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_clock();
|
||||
|
||||
clock_hi
|
||||
^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%clock_hi; // PTX ISA 50, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_clock_hi();
|
||||
|
||||
clock64
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u64 sreg_value, %%clock64; // PTX ISA 20, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint64_t get_sreg_clock64();
|
||||
|
||||
globaltimer
|
||||
^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u64 sreg_value, %%globaltimer; // PTX ISA 31, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint64_t get_sreg_globaltimer();
|
||||
|
||||
globaltimer_lo
|
||||
^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%globaltimer_lo; // PTX ISA 31, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_globaltimer_lo();
|
||||
|
||||
globaltimer_hi
|
||||
^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%globaltimer_hi; // PTX ISA 31, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_globaltimer_hi();
|
||||
|
||||
total_smem_size
|
||||
^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%total_smem_size; // PTX ISA 41, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_total_smem_size();
|
||||
|
||||
aggr_smem_size
|
||||
^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%aggr_smem_size; // PTX ISA 81, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_aggr_smem_size();
|
||||
|
||||
dynamic_smem_size
|
||||
^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u32 sreg_value, %%dynamic_smem_size; // PTX ISA 41, SM_35
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t get_sreg_dynamic_smem_size();
|
||||
|
||||
current_graph_exec
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mov.u64 sreg_value, %%current_graph_exec; // PTX ISA 80, SM_50
|
||||
template <typename = void>
|
||||
__device__ static inline uint64_t get_sreg_current_graph_exec();
|
||||
@@ -0,0 +1,13 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
getctarank.shared::cluster.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// getctarank.space.u32 dest, addr; // PTX ISA 78, SM_90
|
||||
// .space = { .shared::cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline uint32_t getctarank(
|
||||
cuda::ptx::space_cluster_t,
|
||||
const void* addr);
|
||||
2026
cccl_upstream/docs/libcudacxx/ptx/instructions/generated/ld.rst
Normal file
2026
cccl_upstream/docs/libcudacxx/ptx/instructions/generated/ld.rst
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,207 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
mbarrier.arrive.shared.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.shared.b64 state, [addr]; // 1. PTX ISA 70, SM_80
|
||||
template <typename = void>
|
||||
__device__ static inline uint64_t mbarrier_arrive(
|
||||
uint64_t* addr);
|
||||
|
||||
mbarrier.arrive.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.shared::cta.b64 state, [addr], count; // 2. PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline uint64_t mbarrier_arrive(
|
||||
uint64_t* addr,
|
||||
const uint32_t& count);
|
||||
|
||||
mbarrier.arrive.release.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.sem.scope.space.b64 state, [addr]; // 3a. PTX ISA 80, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline uint64_t mbarrier_arrive(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr);
|
||||
|
||||
mbarrier.arrive.release.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.sem.scope.space.b64 state, [addr]; // 3a. PTX ISA 80, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline uint64_t mbarrier_arrive(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr);
|
||||
|
||||
mbarrier.arrive.release.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.sem.scope.space.b64 state, [addr], count; // 3b. PTX ISA 80, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline uint64_t mbarrier_arrive(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr,
|
||||
const uint32_t& count);
|
||||
|
||||
mbarrier.arrive.release.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.sem.scope.space.b64 state, [addr], count; // 3b. PTX ISA 80, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline uint64_t mbarrier_arrive(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr,
|
||||
const uint32_t& count);
|
||||
|
||||
mbarrier.arrive.release.cluster.shared::cluster.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.sem.scope.space.b64 _, [addr]; // 4a. PTX ISA 80, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cluster }
|
||||
// .space = { .shared::cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline void mbarrier_arrive(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_cluster_t,
|
||||
cuda::ptx::space_cluster_t,
|
||||
uint64_t* addr);
|
||||
|
||||
mbarrier.arrive.release.cluster.shared::cluster.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.sem.scope.space.b64 _, [addr], count; // 4b. PTX ISA 80, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cluster }
|
||||
// .space = { .shared::cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline void mbarrier_arrive(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_cluster_t,
|
||||
cuda::ptx::space_cluster_t,
|
||||
uint64_t* addr,
|
||||
const uint32_t& count);
|
||||
|
||||
mbarrier.arrive.relaxed.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.sem.scope.space.b64 state, [addr], count; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline uint64_t mbarrier_arrive(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr,
|
||||
const uint32_t& count);
|
||||
|
||||
mbarrier.arrive.relaxed.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.sem.scope.space.b64 state, [addr], count; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline uint64_t mbarrier_arrive(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr,
|
||||
const uint32_t& count);
|
||||
|
||||
mbarrier.arrive.relaxed.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.sem.scope.space.b64 state, [addr]; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline uint64_t mbarrier_arrive(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr);
|
||||
|
||||
mbarrier.arrive.relaxed.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.sem.scope.space.b64 state, [addr]; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline uint64_t mbarrier_arrive(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr);
|
||||
|
||||
mbarrier.arrive.relaxed.cluster.shared::cluster.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.sem.scope.space.b64 _, [addr], count; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cluster }
|
||||
// .space = { .shared::cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline void mbarrier_arrive(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_cluster_t,
|
||||
cuda::ptx::space_cluster_t,
|
||||
uint64_t* addr,
|
||||
const uint32_t& count);
|
||||
|
||||
mbarrier.arrive.relaxed.cluster.shared::cluster.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.sem.scope.space.b64 _, [addr]; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cluster }
|
||||
// .space = { .shared::cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline void mbarrier_arrive(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_cluster_t,
|
||||
cuda::ptx::space_cluster_t,
|
||||
uint64_t* addr);
|
||||
@@ -0,0 +1,98 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
mbarrier.arrive.expect_tx.release.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.expect_tx.sem.scope.space.b64 state, [addr], tx_count; // 8. PTX ISA 80, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline uint64_t mbarrier_arrive_expect_tx(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr,
|
||||
const uint32_t& tx_count);
|
||||
|
||||
mbarrier.arrive.expect_tx.release.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.expect_tx.sem.scope.space.b64 state, [addr], tx_count; // 8. PTX ISA 80, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline uint64_t mbarrier_arrive_expect_tx(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr,
|
||||
const uint32_t& tx_count);
|
||||
|
||||
mbarrier.arrive.expect_tx.release.cluster.shared::cluster.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.expect_tx.sem.scope.space.b64 _, [addr], tx_count; // 9. PTX ISA 80, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cluster }
|
||||
// .space = { .shared::cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline void mbarrier_arrive_expect_tx(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_cluster_t,
|
||||
cuda::ptx::space_cluster_t,
|
||||
uint64_t* addr,
|
||||
const uint32_t& tx_count);
|
||||
|
||||
mbarrier.arrive.expect_tx.relaxed.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.expect_tx.sem.scope.space.b64 state, [addr], txCount; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline uint64_t mbarrier_arrive_expect_tx(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr,
|
||||
const uint32_t& txCount);
|
||||
|
||||
mbarrier.arrive.expect_tx.relaxed.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.expect_tx.sem.scope.space.b64 state, [addr], txCount; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline uint64_t mbarrier_arrive_expect_tx(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr,
|
||||
const uint32_t& txCount);
|
||||
|
||||
mbarrier.arrive.expect_tx.relaxed.cluster.shared::cluster.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.expect_tx.sem.scope.space.b64 _, [addr], txCount; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cluster }
|
||||
// .space = { .shared::cluster }
|
||||
template <typename = void>
|
||||
__device__ static inline void mbarrier_arrive_expect_tx(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_cluster_t,
|
||||
cuda::ptx::space_cluster_t,
|
||||
uint64_t* addr,
|
||||
const uint32_t& txCount);
|
||||
@@ -0,0 +1,12 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
mbarrier.arrive.noComplete.shared.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.arrive.noComplete.shared.b64 state, [addr], count; // 5. PTX ISA 70, SM_80
|
||||
template <typename = void>
|
||||
__device__ static inline uint64_t mbarrier_arrive_no_complete(
|
||||
uint64_t* addr,
|
||||
const uint32_t& count);
|
||||
@@ -0,0 +1,66 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
mbarrier.expect_tx.relaxed.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.expect_tx.sem.scope.space.b64 [addr], txCount; // 1. PTX ISA 80, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void mbarrier_expect_tx(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr,
|
||||
uint32_t txCount);
|
||||
|
||||
mbarrier.expect_tx.relaxed.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.expect_tx.sem.scope.space.b64 [addr], txCount; // 1. PTX ISA 80, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cta }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void mbarrier_expect_tx(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_shared_t,
|
||||
uint64_t* addr,
|
||||
uint32_t txCount);
|
||||
|
||||
mbarrier.expect_tx.relaxed.cta.shared::cluster.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.expect_tx.sem.scope.space.b64 [addr], txCount; // 2. PTX ISA 80, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void mbarrier_expect_tx(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_cluster_t,
|
||||
uint64_t* addr,
|
||||
uint32_t txCount);
|
||||
|
||||
mbarrier.expect_tx.relaxed.cluster.shared::cluster.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.expect_tx.sem.scope.space.b64 [addr], txCount; // 2. PTX ISA 80, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
// .space = { .shared::cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void mbarrier_expect_tx(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
cuda::ptx::space_cluster_t,
|
||||
uint64_t* addr,
|
||||
uint32_t txCount);
|
||||
@@ -0,0 +1,12 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
mbarrier.init.shared.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.init.shared.b64 [addr], count; // PTX ISA 70, SM_80
|
||||
template <typename = void>
|
||||
__device__ static inline void mbarrier_init(
|
||||
uint64_t* addr,
|
||||
const uint32_t& count);
|
||||
@@ -0,0 +1,11 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
mbarrier.inval.shared.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.inval.shared.b64 [addr]; // PTX ISA 70, SM_80
|
||||
template <typename = void>
|
||||
__device__ static inline void mbarrier_inval(
|
||||
uint64_t* addr);
|
||||
@@ -0,0 +1,68 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
mbarrier.test_wait.shared.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.test_wait.shared.b64 waitComplete, [addr], state; // 1. PTX ISA 70, SM_80
|
||||
template <typename = void>
|
||||
__device__ static inline bool mbarrier_test_wait(
|
||||
uint64_t* addr,
|
||||
const uint64_t& state);
|
||||
|
||||
mbarrier.test_wait.acquire.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.test_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // 2. PTX ISA 80, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_test_wait(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint64_t& state);
|
||||
|
||||
mbarrier.test_wait.acquire.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.test_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // 2. PTX ISA 80, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_test_wait(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint64_t& state);
|
||||
|
||||
mbarrier.test_wait.relaxed.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.test_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_test_wait(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint64_t& state);
|
||||
|
||||
mbarrier.test_wait.relaxed.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.test_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_test_wait(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint64_t& state);
|
||||
@@ -0,0 +1,68 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
mbarrier.test_wait.parity.shared.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.test_wait.parity.shared.b64 waitComplete, [addr], phaseParity; // 3. PTX ISA 71, SM_80
|
||||
template <typename = void>
|
||||
__device__ static inline bool mbarrier_test_wait_parity(
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity);
|
||||
|
||||
mbarrier.test_wait.parity.acquire.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.test_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // 4. PTX ISA 80, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_test_wait_parity(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity);
|
||||
|
||||
mbarrier.test_wait.parity.acquire.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.test_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // 4. PTX ISA 80, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_test_wait_parity(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity);
|
||||
|
||||
mbarrier.test_wait.parity.relaxed.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.test_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_test_wait_parity(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity);
|
||||
|
||||
mbarrier.test_wait.parity.relaxed.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.test_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_test_wait_parity(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity);
|
||||
@@ -0,0 +1,139 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
mbarrier.try_wait.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.shared::cta.b64 waitComplete, [addr], state; // 5a. PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline bool mbarrier_try_wait(
|
||||
uint64_t* addr,
|
||||
const uint64_t& state);
|
||||
|
||||
mbarrier.try_wait.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.shared::cta.b64 waitComplete, [addr], state, suspendTimeHint; // 5b. PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline bool mbarrier_try_wait(
|
||||
uint64_t* addr,
|
||||
const uint64_t& state,
|
||||
const uint32_t& suspendTimeHint);
|
||||
|
||||
mbarrier.try_wait.acquire.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // 6a. PTX ISA 80, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint64_t& state);
|
||||
|
||||
mbarrier.try_wait.acquire.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // 6a. PTX ISA 80, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint64_t& state);
|
||||
|
||||
mbarrier.try_wait.acquire.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state , suspendTimeHint; // 6b. PTX ISA 80, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint64_t& state,
|
||||
const uint32_t& suspendTimeHint);
|
||||
|
||||
mbarrier.try_wait.acquire.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state , suspendTimeHint; // 6b. PTX ISA 80, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint64_t& state,
|
||||
const uint32_t& suspendTimeHint);
|
||||
|
||||
mbarrier.try_wait.relaxed.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state, suspendTimeHint; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint64_t& state,
|
||||
const uint32_t& suspendTimeHint);
|
||||
|
||||
mbarrier.try_wait.relaxed.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state, suspendTimeHint; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint64_t& state,
|
||||
const uint32_t& suspendTimeHint);
|
||||
|
||||
mbarrier.try_wait.relaxed.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint64_t& state);
|
||||
|
||||
mbarrier.try_wait.relaxed.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.sem.scope.shared::cta.b64 waitComplete, [addr], state; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint64_t& state);
|
||||
@@ -0,0 +1,139 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
mbarrier.try_wait.parity.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.parity.shared::cta.b64 waitComplete, [addr], phaseParity; // 7a. PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline bool mbarrier_try_wait_parity(
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity);
|
||||
|
||||
mbarrier.try_wait.parity.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.parity.shared::cta.b64 waitComplete, [addr], phaseParity, suspendTimeHint; // 7b. PTX ISA 78, SM_90
|
||||
template <typename = void>
|
||||
__device__ static inline bool mbarrier_try_wait_parity(
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity,
|
||||
const uint32_t& suspendTimeHint);
|
||||
|
||||
mbarrier.try_wait.parity.acquire.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // 8a. PTX ISA 80, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait_parity(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity);
|
||||
|
||||
mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // 8a. PTX ISA 80, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait_parity(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity);
|
||||
|
||||
mbarrier.try_wait.parity.acquire.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity, suspendTimeHint; // 8b. PTX ISA 80, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait_parity(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity,
|
||||
const uint32_t& suspendTimeHint);
|
||||
|
||||
mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity, suspendTimeHint; // 8b. PTX ISA 80, SM_90
|
||||
// .sem = { .acquire }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait_parity(
|
||||
cuda::ptx::sem_acquire_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity,
|
||||
const uint32_t& suspendTimeHint);
|
||||
|
||||
mbarrier.try_wait.parity.relaxed.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity, suspendTimeHint; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait_parity(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity,
|
||||
const uint32_t& suspendTimeHint);
|
||||
|
||||
mbarrier.try_wait.parity.relaxed.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity, suspendTimeHint; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait_parity(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity,
|
||||
const uint32_t& suspendTimeHint);
|
||||
|
||||
mbarrier.try_wait.parity.relaxed.cta.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait_parity(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity);
|
||||
|
||||
mbarrier.try_wait.parity.relaxed.cluster.shared::cta.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// mbarrier.try_wait.parity.sem.scope.shared::cta.b64 waitComplete, [addr], phaseParity; // PTX ISA 86, SM_90
|
||||
// .sem = { .relaxed }
|
||||
// .scope = { .cta, .cluster }
|
||||
template <cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline bool mbarrier_try_wait_parity(
|
||||
cuda::ptx::sem_relaxed_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
uint64_t* addr,
|
||||
const uint32_t& phaseParity);
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,250 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
multimem.st.weak.global.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.global.b32 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .weak }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_weak_t,
|
||||
B32* addr,
|
||||
B32 val);
|
||||
|
||||
multimem.st.relaxed.cta.global.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B32* addr,
|
||||
B32 val);
|
||||
|
||||
multimem.st.relaxed.cluster.global.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B32* addr,
|
||||
B32 val);
|
||||
|
||||
multimem.st.relaxed.gpu.global.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B32* addr,
|
||||
B32 val);
|
||||
|
||||
multimem.st.relaxed.sys.global.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B32* addr,
|
||||
B32 val);
|
||||
|
||||
multimem.st.release.cta.global.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B32* addr,
|
||||
B32 val);
|
||||
|
||||
multimem.st.release.cluster.global.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B32* addr,
|
||||
B32 val);
|
||||
|
||||
multimem.st.release.gpu.global.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B32* addr,
|
||||
B32 val);
|
||||
|
||||
multimem.st.release.sys.global.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b32 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B32* addr,
|
||||
B32 val);
|
||||
|
||||
multimem.st.weak.global.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.global.b64 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .weak }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_weak_t,
|
||||
B64* addr,
|
||||
B64 val);
|
||||
|
||||
multimem.st.relaxed.cta.global.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B64* addr,
|
||||
B64 val);
|
||||
|
||||
multimem.st.relaxed.cluster.global.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B64* addr,
|
||||
B64 val);
|
||||
|
||||
multimem.st.relaxed.gpu.global.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B64* addr,
|
||||
B64 val);
|
||||
|
||||
multimem.st.relaxed.sys.global.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B64* addr,
|
||||
B64 val);
|
||||
|
||||
multimem.st.release.cta.global.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B64* addr,
|
||||
B64 val);
|
||||
|
||||
multimem.st.release.cluster.global.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B64* addr,
|
||||
B64 val);
|
||||
|
||||
multimem.st.release.gpu.global.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B64* addr,
|
||||
B64 val);
|
||||
|
||||
multimem.st.release.sys.global.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// multimem.st.sem.scope.global.b64 [addr], val; // PTX ISA 81, SM_90
|
||||
// .sem = { .relaxed, .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true, cuda::ptx::dot_sem Sem, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void multimem_st(
|
||||
cuda::ptx::sem_t<Sem> sem,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
B64* addr,
|
||||
B64 val);
|
||||
@@ -0,0 +1,79 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
prmt.b32
|
||||
^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// prmt.b32 dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline uint32_t prmt(
|
||||
B32 a_reg,
|
||||
B32 b_reg,
|
||||
uint32_t c_reg);
|
||||
|
||||
prmt.b32.f4e
|
||||
^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// prmt.b32.f4e dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline uint32_t prmt_f4e(
|
||||
B32 a_reg,
|
||||
B32 b_reg,
|
||||
uint32_t c_reg);
|
||||
|
||||
prmt.b32.b4e
|
||||
^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// prmt.b32.b4e dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline uint32_t prmt_b4e(
|
||||
B32 a_reg,
|
||||
B32 b_reg,
|
||||
uint32_t c_reg);
|
||||
|
||||
prmt.b32.rc8
|
||||
^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// prmt.b32.rc8 dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline uint32_t prmt_rc8(
|
||||
B32 a_reg,
|
||||
B32 b_reg,
|
||||
uint32_t c_reg);
|
||||
|
||||
prmt.b32.ecl
|
||||
^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// prmt.b32.ecl dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline uint32_t prmt_ecl(
|
||||
B32 a_reg,
|
||||
B32 b_reg,
|
||||
uint32_t c_reg);
|
||||
|
||||
prmt.b32.ecr
|
||||
^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// prmt.b32.ecr dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline uint32_t prmt_ecr(
|
||||
B32 a_reg,
|
||||
B32 b_reg,
|
||||
uint32_t c_reg);
|
||||
|
||||
prmt.b32.rc16
|
||||
^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// prmt.b32.rc16 dest, a_reg, b_reg, c_reg; // PTX ISA 20, SM_50
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline uint32_t prmt_rc16(
|
||||
B32 a_reg,
|
||||
B32 b_reg,
|
||||
uint32_t c_reg);
|
||||
@@ -0,0 +1,183 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.inc.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90
|
||||
// .type = { .u32 }
|
||||
// .op = { .inc }
|
||||
template <typename = void>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_inc_t,
|
||||
uint32_t* dest,
|
||||
const uint32_t& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.dec.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90
|
||||
// .type = { .u32 }
|
||||
// .op = { .dec }
|
||||
template <typename = void>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_dec_t,
|
||||
uint32_t* dest,
|
||||
const uint32_t& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.min.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90
|
||||
// .type = { .u32 }
|
||||
// .op = { .min }
|
||||
template <typename = void>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_min_t,
|
||||
uint32_t* dest,
|
||||
const uint32_t& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.max.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90
|
||||
// .type = { .u32 }
|
||||
// .op = { .max }
|
||||
template <typename = void>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_max_t,
|
||||
uint32_t* dest,
|
||||
const uint32_t& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90
|
||||
// .type = { .u32 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_add_t,
|
||||
uint32_t* dest,
|
||||
const uint32_t& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.min.s32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90
|
||||
// .type = { .s32 }
|
||||
// .op = { .min }
|
||||
template <typename = void>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_min_t,
|
||||
int32_t* dest,
|
||||
const int32_t& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.max.s32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90
|
||||
// .type = { .s32 }
|
||||
// .op = { .max }
|
||||
template <typename = void>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_max_t,
|
||||
int32_t* dest,
|
||||
const int32_t& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.s32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90
|
||||
// .type = { .s32 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_add_t,
|
||||
int32_t* dest,
|
||||
const int32_t& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.and.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90
|
||||
// .type = { .b32 }
|
||||
// .op = { .and }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_and_op_t,
|
||||
B32* dest,
|
||||
const B32& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.or.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90
|
||||
// .type = { .b32 }
|
||||
// .op = { .or }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_or_op_t,
|
||||
B32* dest,
|
||||
const B32& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.xor.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90
|
||||
// .type = { .b32 }
|
||||
// .op = { .xor }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_xor_op_t,
|
||||
B32* dest,
|
||||
const B32& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.type [dest], value, [remote_bar]; // PTX ISA 81, SM_90
|
||||
// .type = { .u64 }
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_add_t,
|
||||
uint64_t* dest,
|
||||
const uint64_t& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.add.u64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes.op.u64 [dest], value, [remote_bar]; // .u64 intentional PTX ISA 81, SM_90
|
||||
// .op = { .add }
|
||||
template <typename = void>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_add_t,
|
||||
int64_t* dest,
|
||||
const int64_t& value,
|
||||
int64_t* remote_bar);
|
||||
@@ -0,0 +1,20 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
setmaxnreg.inc.sync.aligned.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// setmaxnreg.inc.sync.aligned.u32 imm_reg_count; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
template <int N32>
|
||||
__device__ static inline void setmaxnreg_inc(
|
||||
cuda::ptx::n32_t<N32> imm_reg_count);
|
||||
|
||||
setmaxnreg.dec.sync.aligned.u32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// setmaxnreg.dec.sync.aligned.u32 imm_reg_count; // PTX ISA 80, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
template <int N32>
|
||||
__device__ static inline void setmaxnreg_dec(
|
||||
cuda::ptx::n32_t<N32> imm_reg_count);
|
||||
@@ -0,0 +1,32 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
shl.b16
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// shl.b16 dest, a_reg, b_reg; // PTX ISA 10, SM_50
|
||||
template <typename B16, enable_if_t<sizeof(B16) == 2, bool> = true>
|
||||
__device__ static inline B16 shl(
|
||||
B16 a_reg,
|
||||
uint32_t b_reg);
|
||||
|
||||
shl.b32
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// shl.b32 dest, a_reg, b_reg; // PTX ISA 10, SM_50
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline B32 shl(
|
||||
B32 a_reg,
|
||||
uint32_t b_reg);
|
||||
|
||||
shl.b64
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// shl.b64 dest, a_reg, b_reg; // PTX ISA 10, SM_50
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline B64 shl(
|
||||
B64 a_reg,
|
||||
uint32_t b_reg);
|
||||
@@ -0,0 +1,62 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
shr.b16
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// shr.b16 dest, a_reg, b_reg; // PTX ISA 10, SM_50
|
||||
template <typename B16, enable_if_t<sizeof(B16) == 2, bool> = true>
|
||||
__device__ static inline B16 shr(
|
||||
B16 a_reg,
|
||||
uint32_t b_reg);
|
||||
|
||||
shr.b32
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// shr.b32 dest, a_reg, b_reg; // PTX ISA 10, SM_50
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4 && !(is_integral_v<B32> && is_signed_v<B32>), bool> = true>
|
||||
__device__ static inline B32 shr(
|
||||
B32 a_reg,
|
||||
uint32_t b_reg);
|
||||
|
||||
shr.b64
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// shr.b64 dest, a_reg, b_reg; // PTX ISA 10, SM_50
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8 && !(is_integral_v<B64> && is_signed_v<B64>), bool> = true>
|
||||
__device__ static inline B64 shr(
|
||||
B64 a_reg,
|
||||
uint32_t b_reg);
|
||||
|
||||
shr.s16
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// shr.s16 dest, a_reg, b_reg; // PTX ISA 10, SM_50
|
||||
template <typename = void>
|
||||
__device__ static inline int16_t shr(
|
||||
int16_t a_reg,
|
||||
uint32_t b_reg);
|
||||
|
||||
shr.s32
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// shr.s32 dest, a_reg, b_reg; // PTX ISA 10, SM_50
|
||||
template <typename S32, enable_if_t<sizeof(S32) == 4 && is_integral_v<S32> && is_signed_v<S32>, bool> = true>
|
||||
__device__ static inline S32 shr(
|
||||
S32 a_reg,
|
||||
uint32_t b_reg);
|
||||
|
||||
shr.s64
|
||||
^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// shr.s64 dest, a_reg, b_reg; // PTX ISA 10, SM_50
|
||||
template <typename S64, enable_if_t<sizeof(S64) == 8 && is_integral_v<S64> && is_signed_v<S64>, bool> = true>
|
||||
__device__ static inline S64 shr(
|
||||
S64 a_reg,
|
||||
uint32_t b_reg);
|
||||
602
cccl_upstream/docs/libcudacxx/ptx/instructions/generated/st.rst
Normal file
602
cccl_upstream/docs/libcudacxx/ptx/instructions/generated/st.rst
Normal file
@@ -0,0 +1,602 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
st.global.b8
|
||||
^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.b8 [addr], src; // PTX ISA 10, SM_50
|
||||
// .space = { .global }
|
||||
template <typename B8, enable_if_t<sizeof(B8) == 1, bool> = true>
|
||||
__device__ static inline void st(
|
||||
cuda::ptx::space_global_t,
|
||||
B8* addr,
|
||||
B8 src);
|
||||
|
||||
st.global.b16
|
||||
^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.b16 [addr], src; // PTX ISA 10, SM_50
|
||||
// .space = { .global }
|
||||
template <typename B16, enable_if_t<sizeof(B16) == 2, bool> = true>
|
||||
__device__ static inline void st(
|
||||
cuda::ptx::space_global_t,
|
||||
B16* addr,
|
||||
B16 src);
|
||||
|
||||
st.global.b32
|
||||
^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.b32 [addr], src; // PTX ISA 10, SM_50
|
||||
// .space = { .global }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void st(
|
||||
cuda::ptx::space_global_t,
|
||||
B32* addr,
|
||||
B32 src);
|
||||
|
||||
st.global.b64
|
||||
^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.b64 [addr], src; // PTX ISA 10, SM_50
|
||||
// .space = { .global }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline void st(
|
||||
cuda::ptx::space_global_t,
|
||||
B64* addr,
|
||||
B64 src);
|
||||
|
||||
st.global.b128
|
||||
^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.b128 [addr], src; // PTX ISA 83, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
|
||||
__device__ static inline void st(
|
||||
cuda::ptx::space_global_t,
|
||||
B128* addr,
|
||||
B128 src);
|
||||
|
||||
st.global.v4.b64
|
||||
^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.v4.b64 [addr], src; // PTX ISA 88, SM_100
|
||||
// .space = { .global }
|
||||
template <typename B256, enable_if_t<sizeof(B256) == 32, bool> = true>
|
||||
__device__ static inline void st(
|
||||
cuda::ptx::space_global_t,
|
||||
B256* addr,
|
||||
B256 src);
|
||||
|
||||
st.global.L2::cache_hint.b8
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L2::cache_hint.b8 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B8, enable_if_t<sizeof(B8) == 1, bool> = true>
|
||||
__device__ static inline void st_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B8* addr,
|
||||
B8 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L2::cache_hint.b16
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L2::cache_hint.b16 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B16, enable_if_t<sizeof(B16) == 2, bool> = true>
|
||||
__device__ static inline void st_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B16* addr,
|
||||
B16 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L2::cache_hint.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L2::cache_hint.b32 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void st_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B32* addr,
|
||||
B32 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L2::cache_hint.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L2::cache_hint.b64 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline void st_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B64* addr,
|
||||
B64 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L2::cache_hint.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L2::cache_hint.b128 [addr], src, cache_policy; // PTX ISA 83, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
|
||||
__device__ static inline void st_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B128* addr,
|
||||
B128 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L2::cache_hint.v4.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L2::cache_hint.v4.b64 [addr], src, cache_policy; // PTX ISA 88, SM_100
|
||||
// .space = { .global }
|
||||
template <typename B256, enable_if_t<sizeof(B256) == 32, bool> = true>
|
||||
__device__ static inline void st_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B256* addr,
|
||||
B256 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::evict_first.b8
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_first.b8 [addr], src; // PTX ISA 74, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B8, enable_if_t<sizeof(B8) == 1, bool> = true>
|
||||
__device__ static inline void st_L1_evict_first(
|
||||
cuda::ptx::space_global_t,
|
||||
B8* addr,
|
||||
B8 src);
|
||||
|
||||
st.global.L1::evict_first.b16
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_first.b16 [addr], src; // PTX ISA 74, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B16, enable_if_t<sizeof(B16) == 2, bool> = true>
|
||||
__device__ static inline void st_L1_evict_first(
|
||||
cuda::ptx::space_global_t,
|
||||
B16* addr,
|
||||
B16 src);
|
||||
|
||||
st.global.L1::evict_first.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_first.b32 [addr], src; // PTX ISA 74, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void st_L1_evict_first(
|
||||
cuda::ptx::space_global_t,
|
||||
B32* addr,
|
||||
B32 src);
|
||||
|
||||
st.global.L1::evict_first.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_first.b64 [addr], src; // PTX ISA 74, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline void st_L1_evict_first(
|
||||
cuda::ptx::space_global_t,
|
||||
B64* addr,
|
||||
B64 src);
|
||||
|
||||
st.global.L1::evict_first.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_first.b128 [addr], src; // PTX ISA 83, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
|
||||
__device__ static inline void st_L1_evict_first(
|
||||
cuda::ptx::space_global_t,
|
||||
B128* addr,
|
||||
B128 src);
|
||||
|
||||
st.global.L1::evict_first.v4.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_first.v4.b64 [addr], src; // PTX ISA 88, SM_100
|
||||
// .space = { .global }
|
||||
template <typename B256, enable_if_t<sizeof(B256) == 32, bool> = true>
|
||||
__device__ static inline void st_L1_evict_first(
|
||||
cuda::ptx::space_global_t,
|
||||
B256* addr,
|
||||
B256 src);
|
||||
|
||||
st.global.L1::evict_first.L2::cache_hint.b8
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_first.L2::cache_hint.b8 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B8, enable_if_t<sizeof(B8) == 1, bool> = true>
|
||||
__device__ static inline void st_L1_evict_first_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B8* addr,
|
||||
B8 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::evict_first.L2::cache_hint.b16
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_first.L2::cache_hint.b16 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B16, enable_if_t<sizeof(B16) == 2, bool> = true>
|
||||
__device__ static inline void st_L1_evict_first_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B16* addr,
|
||||
B16 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::evict_first.L2::cache_hint.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_first.L2::cache_hint.b32 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void st_L1_evict_first_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B32* addr,
|
||||
B32 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::evict_first.L2::cache_hint.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_first.L2::cache_hint.b64 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline void st_L1_evict_first_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B64* addr,
|
||||
B64 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::evict_first.L2::cache_hint.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_first.L2::cache_hint.b128 [addr], src, cache_policy; // PTX ISA 83, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
|
||||
__device__ static inline void st_L1_evict_first_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B128* addr,
|
||||
B128 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::evict_first.L2::cache_hint.v4.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_first.L2::cache_hint.v4.b64 [addr], src, cache_policy; // PTX ISA 88, SM_100
|
||||
// .space = { .global }
|
||||
template <typename B256, enable_if_t<sizeof(B256) == 32, bool> = true>
|
||||
__device__ static inline void st_L1_evict_first_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B256* addr,
|
||||
B256 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::evict_last.b8
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_last.b8 [addr], src; // PTX ISA 74, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B8, enable_if_t<sizeof(B8) == 1, bool> = true>
|
||||
__device__ static inline void st_L1_evict_last(
|
||||
cuda::ptx::space_global_t,
|
||||
B8* addr,
|
||||
B8 src);
|
||||
|
||||
st.global.L1::evict_last.b16
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_last.b16 [addr], src; // PTX ISA 74, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B16, enable_if_t<sizeof(B16) == 2, bool> = true>
|
||||
__device__ static inline void st_L1_evict_last(
|
||||
cuda::ptx::space_global_t,
|
||||
B16* addr,
|
||||
B16 src);
|
||||
|
||||
st.global.L1::evict_last.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_last.b32 [addr], src; // PTX ISA 74, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void st_L1_evict_last(
|
||||
cuda::ptx::space_global_t,
|
||||
B32* addr,
|
||||
B32 src);
|
||||
|
||||
st.global.L1::evict_last.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_last.b64 [addr], src; // PTX ISA 74, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline void st_L1_evict_last(
|
||||
cuda::ptx::space_global_t,
|
||||
B64* addr,
|
||||
B64 src);
|
||||
|
||||
st.global.L1::evict_last.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_last.b128 [addr], src; // PTX ISA 83, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
|
||||
__device__ static inline void st_L1_evict_last(
|
||||
cuda::ptx::space_global_t,
|
||||
B128* addr,
|
||||
B128 src);
|
||||
|
||||
st.global.L1::evict_last.v4.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_last.v4.b64 [addr], src; // PTX ISA 88, SM_100
|
||||
// .space = { .global }
|
||||
template <typename B256, enable_if_t<sizeof(B256) == 32, bool> = true>
|
||||
__device__ static inline void st_L1_evict_last(
|
||||
cuda::ptx::space_global_t,
|
||||
B256* addr,
|
||||
B256 src);
|
||||
|
||||
st.global.L1::evict_last.L2::cache_hint.b8
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_last.L2::cache_hint.b8 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B8, enable_if_t<sizeof(B8) == 1, bool> = true>
|
||||
__device__ static inline void st_L1_evict_last_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B8* addr,
|
||||
B8 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::evict_last.L2::cache_hint.b16
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_last.L2::cache_hint.b16 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B16, enable_if_t<sizeof(B16) == 2, bool> = true>
|
||||
__device__ static inline void st_L1_evict_last_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B16* addr,
|
||||
B16 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::evict_last.L2::cache_hint.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_last.L2::cache_hint.b32 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void st_L1_evict_last_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B32* addr,
|
||||
B32 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::evict_last.L2::cache_hint.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_last.L2::cache_hint.b64 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline void st_L1_evict_last_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B64* addr,
|
||||
B64 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::evict_last.L2::cache_hint.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_last.L2::cache_hint.b128 [addr], src, cache_policy; // PTX ISA 83, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
|
||||
__device__ static inline void st_L1_evict_last_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B128* addr,
|
||||
B128 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::evict_last.L2::cache_hint.v4.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::evict_last.L2::cache_hint.v4.b64 [addr], src, cache_policy; // PTX ISA 88, SM_100
|
||||
// .space = { .global }
|
||||
template <typename B256, enable_if_t<sizeof(B256) == 32, bool> = true>
|
||||
__device__ static inline void st_L1_evict_last_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B256* addr,
|
||||
B256 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::no_allocate.b8
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::no_allocate.b8 [addr], src; // PTX ISA 74, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B8, enable_if_t<sizeof(B8) == 1, bool> = true>
|
||||
__device__ static inline void st_L1_no_allocate(
|
||||
cuda::ptx::space_global_t,
|
||||
B8* addr,
|
||||
B8 src);
|
||||
|
||||
st.global.L1::no_allocate.b16
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::no_allocate.b16 [addr], src; // PTX ISA 74, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B16, enable_if_t<sizeof(B16) == 2, bool> = true>
|
||||
__device__ static inline void st_L1_no_allocate(
|
||||
cuda::ptx::space_global_t,
|
||||
B16* addr,
|
||||
B16 src);
|
||||
|
||||
st.global.L1::no_allocate.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::no_allocate.b32 [addr], src; // PTX ISA 74, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void st_L1_no_allocate(
|
||||
cuda::ptx::space_global_t,
|
||||
B32* addr,
|
||||
B32 src);
|
||||
|
||||
st.global.L1::no_allocate.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::no_allocate.b64 [addr], src; // PTX ISA 74, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline void st_L1_no_allocate(
|
||||
cuda::ptx::space_global_t,
|
||||
B64* addr,
|
||||
B64 src);
|
||||
|
||||
st.global.L1::no_allocate.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::no_allocate.b128 [addr], src; // PTX ISA 83, SM_70
|
||||
// .space = { .global }
|
||||
template <typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
|
||||
__device__ static inline void st_L1_no_allocate(
|
||||
cuda::ptx::space_global_t,
|
||||
B128* addr,
|
||||
B128 src);
|
||||
|
||||
st.global.L1::no_allocate.v4.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::no_allocate.v4.b64 [addr], src; // PTX ISA 88, SM_100
|
||||
// .space = { .global }
|
||||
template <typename B256, enable_if_t<sizeof(B256) == 32, bool> = true>
|
||||
__device__ static inline void st_L1_no_allocate(
|
||||
cuda::ptx::space_global_t,
|
||||
B256* addr,
|
||||
B256 src);
|
||||
|
||||
st.global.L1::no_allocate.L2::cache_hint.b8
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::no_allocate.L2::cache_hint.b8 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B8, enable_if_t<sizeof(B8) == 1, bool> = true>
|
||||
__device__ static inline void st_L1_no_allocate_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B8* addr,
|
||||
B8 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::no_allocate.L2::cache_hint.b16
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::no_allocate.L2::cache_hint.b16 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B16, enable_if_t<sizeof(B16) == 2, bool> = true>
|
||||
__device__ static inline void st_L1_no_allocate_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B16* addr,
|
||||
B16 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::no_allocate.L2::cache_hint.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::no_allocate.L2::cache_hint.b32 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void st_L1_no_allocate_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B32* addr,
|
||||
B32 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::no_allocate.L2::cache_hint.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::no_allocate.L2::cache_hint.b64 [addr], src, cache_policy; // PTX ISA 74, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline void st_L1_no_allocate_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B64* addr,
|
||||
B64 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::no_allocate.L2::cache_hint.b128
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::no_allocate.L2::cache_hint.b128 [addr], src, cache_policy; // PTX ISA 83, SM_80
|
||||
// .space = { .global }
|
||||
template <typename B128, enable_if_t<sizeof(B128) == 16, bool> = true>
|
||||
__device__ static inline void st_L1_no_allocate_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B128* addr,
|
||||
B128 src,
|
||||
uint64_t cache_policy);
|
||||
|
||||
st.global.L1::no_allocate.L2::cache_hint.v4.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.space.L1::no_allocate.L2::cache_hint.v4.b64 [addr], src, cache_policy; // PTX ISA 88, SM_100
|
||||
// .space = { .global }
|
||||
template <typename B256, enable_if_t<sizeof(B256) == 32, bool> = true>
|
||||
__device__ static inline void st_L1_no_allocate_L2_cache_hint(
|
||||
cuda::ptx::space_global_t,
|
||||
B256* addr,
|
||||
B256 src,
|
||||
uint64_t cache_policy);
|
||||
@@ -0,0 +1,61 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.type [addr], value, [remote_bar]; // 1. PTX ISA 81, SM_90
|
||||
// .type = { .b32, .b64 }
|
||||
template <typename Type>
|
||||
__device__ static inline void st_async(
|
||||
Type* addr,
|
||||
const Type& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.type [addr], value, [remote_bar]; // 1. PTX ISA 81, SM_90
|
||||
// .type = { .b32, .b64 }
|
||||
template <typename Type>
|
||||
__device__ static inline void st_async(
|
||||
Type* addr,
|
||||
const Type& value,
|
||||
uint64_t* remote_bar);
|
||||
|
||||
st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.type [addr], value, [remote_bar]; // 2. PTX ISA 81, SM_90
|
||||
// .type = { .b32, .b64 }
|
||||
template <typename Type>
|
||||
__device__ static inline void st_async(
|
||||
Type* addr,
|
||||
const Type (&value)[2],
|
||||
uint64_t* remote_bar);
|
||||
|
||||
st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v2.type [addr], value, [remote_bar]; // 2. PTX ISA 81, SM_90
|
||||
// .type = { .b32, .b64 }
|
||||
template <typename Type>
|
||||
__device__ static inline void st_async(
|
||||
Type* addr,
|
||||
const Type (&value)[2],
|
||||
uint64_t* remote_bar);
|
||||
|
||||
st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v4.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.async.weak.shared::cluster.mbarrier::complete_tx::bytes.v4.b32 [addr], value, [remote_bar]; // 3. PTX ISA 81, SM_90
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void st_async(
|
||||
B32* addr,
|
||||
const B32 (&value)[4],
|
||||
uint64_t* remote_bar);
|
||||
@@ -0,0 +1,13 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
st.bulk.weak.shared::cta
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// st.bulk.weak.shared::cta [addr], size, initval; // PTX ISA 86, SM_100
|
||||
template <int N32>
|
||||
__device__ static inline void st_bulk(
|
||||
void* addr,
|
||||
uint64_t size,
|
||||
cuda::ptx::n32_t<N32> initval);
|
||||
@@ -0,0 +1,70 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.alloc.cta_group.sync.aligned.shared::cta.b32 [dst], nCols; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_alloc(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t* dst,
|
||||
const uint32_t& nCols);
|
||||
|
||||
tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.alloc.cta_group.sync.aligned.shared::cta.b32 [dst], nCols; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_alloc(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t* dst,
|
||||
const uint32_t& nCols);
|
||||
|
||||
tcgen05.dealloc.cta_group::1.sync.aligned.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.dealloc.cta_group.sync.aligned.b32 taddr, nCols; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_dealloc(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
const uint32_t& nCols);
|
||||
|
||||
tcgen05.dealloc.cta_group::2.sync.aligned.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.dealloc.cta_group.sync.aligned.b32 taddr, nCols; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_dealloc(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
const uint32_t& nCols);
|
||||
|
||||
tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.relinquish_alloc_permit.cta_group.sync.aligned; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_relinquish_alloc_permit(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group);
|
||||
|
||||
tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.relinquish_alloc_permit.cta_group.sync.aligned; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_relinquish_alloc_permit(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group);
|
||||
@@ -0,0 +1,48 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.commit.cta_group.mbarrier::arrive::one.shared::cluster.b64 [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_commit(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint64_t* smem_bar);
|
||||
|
||||
tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.commit.cta_group.mbarrier::arrive::one.shared::cluster.b64 [smem_bar]; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_commit(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint64_t* smem_bar);
|
||||
|
||||
tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.commit.cta_group.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_commit_multicast(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint64_t* smem_bar,
|
||||
uint16_t ctaMask);
|
||||
|
||||
tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.commit.cta_group.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [smem_bar], ctaMask; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_commit_multicast(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint64_t* smem_bar,
|
||||
uint16_t ctaMask);
|
||||
@@ -0,0 +1,434 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
tcgen05.cp.cta_group::1.128x256b
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.128x256b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_128x256b(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.128x256b
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.128x256b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_128x256b(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.4x256b
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.4x256b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_4x256b(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.4x256b
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.4x256b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_4x256b(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.128x128b
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.128x128b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_128x128b(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.128x128b
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.128x128b [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_128x128b(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.64x128b.warpx2::02_13
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.64x128b.warpx2::02_13 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.64x128b.warpx2::02_13
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.64x128b.warpx2::02_13 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.64x128b.warpx2::01_23
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.64x128b.warpx2::01_23 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.64x128b.warpx2::01_23
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.64x128b.warpx2::01_23 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.32x128b.warpx4
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.32x128b.warpx4 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_32x128b_warpx4(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.32x128b.warpx4
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.32x128b.warpx4 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_32x128b_warpx4(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.128x256b.b8x16.b6x16_p32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.128x256b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_128x256b_b8x16_b6x16_p32(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.128x256b.b8x16.b6x16_p32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.128x256b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_128x256b_b8x16_b6x16_p32(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.4x256b.b8x16.b6x16_p32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.4x256b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_4x256b_b8x16_b6x16_p32(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.4x256b.b8x16.b6x16_p32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.4x256b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_4x256b_b8x16_b6x16_p32(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.128x128b.b8x16.b6x16_p32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.128x128b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_128x128b_b8x16_b6x16_p32(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.128x128b.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_128x128b_b8x16_b6x16_p32(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b6x16_p32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.64x128b.warpx2::02_13.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b6x16_p32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.64x128b.warpx2::02_13.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b6x16_p32(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b6x16_p32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.64x128b.warpx2::01_23.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.64x128b.warpx2::01_23.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b6x16_p32(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b6x16_p32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.32x128b.warpx4.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b6x16_p32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.32x128b.warpx4.b8x16.b6x16_p32 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b6x16_p32(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.128x256b.b8x16.b4x16_p64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.128x256b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_128x256b_b8x16_b4x16_p64(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.128x256b.b8x16.b4x16_p64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.128x256b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_128x256b_b8x16_b4x16_p64(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.4x256b.b8x16.b4x16_p64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.4x256b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_4x256b_b8x16_b4x16_p64(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.4x256b.b8x16.b4x16_p64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.4x256b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_4x256b_b8x16_b4x16_p64(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.128x128b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_128x128b_b8x16_b4x16_p64(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.128x128b.b8x16.b4x16_p64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.128x128b.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_128x128b_b8x16_b4x16_p64(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b4x16_p64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.64x128b.warpx2::02_13.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b4x16_p64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.64x128b.warpx2::02_13.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_64x128b_warpx2_02_13_b8x16_b4x16_p64(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b4x16_p64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.64x128b.warpx2::01_23.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b4x16_p64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.64x128b.warpx2::01_23.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_64x128b_warpx2_01_23_b8x16_b4x16_p64(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b4x16_p64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.32x128b.warpx4.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
|
||||
tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b4x16_p64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.cp.cta_group.32x128b.warpx4.b8x16.b4x16_p64 [taddr], s_desc; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_cp_32x128b_warpx4_b8x16_b4x16_p64(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr,
|
||||
uint64_t s_desc);
|
||||
@@ -0,0 +1,18 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
tcgen05.fence::before_thread_sync
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.fence::before_thread_sync; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename = void>
|
||||
__device__ static inline void tcgen05_fence_before_thread_sync();
|
||||
|
||||
tcgen05.fence::after_thread_sync
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.fence::after_thread_sync; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename = void>
|
||||
__device__ static inline void tcgen05_fence_after_thread_sync();
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,24 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
tcgen05.shift.cta_group::1.down
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.shift.cta_group.down [taddr]; // PTX ISA 86, SM_100a, SM_103a, SM_110a
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_shift_down(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr);
|
||||
|
||||
tcgen05.shift.cta_group::2.down
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.shift.cta_group.down [taddr]; // PTX ISA 86, SM_100a, SM_103a, SM_110a
|
||||
// .cta_group = { .cta_group::1, .cta_group::2 }
|
||||
template <cuda::ptx::dot_cta_group Cta_Group>
|
||||
__device__ static inline void tcgen05_shift_down(
|
||||
cuda::ptx::cta_group_t<Cta_Group> cta_group,
|
||||
uint32_t taddr);
|
||||
@@ -0,0 +1,758 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x1.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[1]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x1.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[1]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x2.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[2]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x2.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[2]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x4.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[4]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x4.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[4]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x8.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[8]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x8.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[8]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x16.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[16]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x16.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[16]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x32.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[32]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x32.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[32]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x64.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x64.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[64]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x64.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x64.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[64]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x128.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x128.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[128]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x64b.x128.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x64b.x128.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x64b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[128]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x1.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[2]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[2]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x2.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[4]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x2.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[4]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x4.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[8]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x4.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[8]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x8.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[16]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x8.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[16]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x16.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[32]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x16.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[32]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x32.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[64]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x32.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[64]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x64.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x64.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[128]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x128b.x64.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x128b.x64.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x128b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[128]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x256b.x1.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x256b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x256b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[4]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x256b.x1.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x256b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x256b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[4]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x256b.x2.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x256b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x256b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[8]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x256b.x2.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x256b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x256b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[8]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x256b.x4.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x256b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x256b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[16]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x256b.x4.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x256b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x256b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[16]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x256b.x8.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x256b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x256b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[32]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x256b.x8.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x256b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x256b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[32]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x256b.x16.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x256b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x256b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[64]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x256b.x16.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x256b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x256b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[64]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x256b.x32.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x256b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x256b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[128]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x256b.x32.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x256b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x256b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[128]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x1.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x1.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[1]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x1.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x1.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[1]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x2.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x2.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[2]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x2.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x2.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[2]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x4.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x4.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[4]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x4.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x4.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[4]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x8.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x8.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[8]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x8.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x8.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[8]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x16.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x16.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[16]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x16.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x16.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[16]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x32.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x32.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[32]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x32.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x32.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[32]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x64.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x64.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[64]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x64.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x64.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[64]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x128.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x128.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[128]);
|
||||
|
||||
tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32 [taddr], values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_32x32b_unpack_16b(
|
||||
uint32_t taddr,
|
||||
const B32 (&values)[128]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x1.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x1.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[1]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[1]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x2.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x2.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[2]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x2.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x2.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[2]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x4.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x4.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[4]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x4.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x4.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[4]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x8.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x8.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[8]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x8.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x8.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[8]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x16.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x16.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[16]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x16.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x16.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[16]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x32.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x32.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[32]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x32.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x32.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[32]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x64.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x64.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[64]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x64.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x64.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[64]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x128.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x128.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[128]);
|
||||
|
||||
tcgen05.st.sync.aligned.16x32bx2.x128.unpack::16b.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.st.sync.aligned.16x32bx2.x128.unpack::16b.b32 [taddr], immHalfSplitoff, values; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tcgen05_st_16x32bx2_unpack_16b(
|
||||
uint32_t taddr,
|
||||
cuda::ptx::n32_t<N32> immHalfSplitoff,
|
||||
const B32 (&values)[128]);
|
||||
@@ -0,0 +1,18 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
tcgen05.wait::ld.sync.aligned
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.wait::ld.sync.aligned; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename = void>
|
||||
__device__ static inline void tcgen05_wait_ld();
|
||||
|
||||
tcgen05.wait::st.sync.aligned
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tcgen05.wait::st.sync.aligned; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f
|
||||
template <typename = void>
|
||||
__device__ static inline void tcgen05_wait_st();
|
||||
@@ -0,0 +1,62 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.cta.sync.aligned
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.sem.scope.sync.aligned [dst], [src], size; // PTX ISA 83, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <int N32, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void tensormap_cp_fenceproxy(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
void* dst,
|
||||
const void* src,
|
||||
cuda::ptx::n32_t<N32> size);
|
||||
|
||||
tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.cluster.sync.aligned
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.sem.scope.sync.aligned [dst], [src], size; // PTX ISA 83, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <int N32, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void tensormap_cp_fenceproxy(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
void* dst,
|
||||
const void* src,
|
||||
cuda::ptx::n32_t<N32> size);
|
||||
|
||||
tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.gpu.sync.aligned
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.sem.scope.sync.aligned [dst], [src], size; // PTX ISA 83, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <int N32, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void tensormap_cp_fenceproxy(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
void* dst,
|
||||
const void* src,
|
||||
cuda::ptx::n32_t<N32> size);
|
||||
|
||||
tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.sys.sync.aligned
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.sem.scope.sync.aligned [dst], [src], size; // PTX ISA 83, SM_90
|
||||
// .sem = { .release }
|
||||
// .scope = { .cta, .cluster, .gpu, .sys }
|
||||
template <int N32, cuda::ptx::dot_scope Scope>
|
||||
__device__ static inline void tensormap_cp_fenceproxy(
|
||||
cuda::ptx::sem_release_t,
|
||||
cuda::ptx::scope_t<Scope> scope,
|
||||
void* dst,
|
||||
const void* src,
|
||||
cuda::ptx::n32_t<N32> size);
|
||||
@@ -0,0 +1,300 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
tensormap.replace.tile.global_address.global.b1024.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.global_address.space.b1024.b64 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .global }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline void tensormap_replace_global_address(
|
||||
cuda::ptx::space_global_t,
|
||||
void* tm_addr,
|
||||
B64 new_val);
|
||||
|
||||
tensormap.replace.tile.global_address.shared::cta.b1024.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.global_address.space.b1024.b64 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .shared::cta }
|
||||
template <typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline void tensormap_replace_global_address(
|
||||
cuda::ptx::space_shared_t,
|
||||
void* tm_addr,
|
||||
B64 new_val);
|
||||
|
||||
tensormap.replace.tile.rank.global.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.rank.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .global }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tensormap_replace_rank(
|
||||
cuda::ptx::space_global_t,
|
||||
void* tm_addr,
|
||||
B32 new_val);
|
||||
|
||||
tensormap.replace.tile.rank.shared::cta.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.rank.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .shared::cta }
|
||||
template <typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tensormap_replace_rank(
|
||||
cuda::ptx::space_shared_t,
|
||||
void* tm_addr,
|
||||
B32 new_val);
|
||||
|
||||
tensormap.replace.tile.box_dim.global.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.box_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .global }
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tensormap_replace_box_dim(
|
||||
cuda::ptx::space_global_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> ord,
|
||||
B32 new_val);
|
||||
|
||||
tensormap.replace.tile.box_dim.shared::cta.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.box_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .shared::cta }
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tensormap_replace_box_dim(
|
||||
cuda::ptx::space_shared_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> ord,
|
||||
B32 new_val);
|
||||
|
||||
tensormap.replace.tile.global_dim.global.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.global_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .global }
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tensormap_replace_global_dim(
|
||||
cuda::ptx::space_global_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> ord,
|
||||
B32 new_val);
|
||||
|
||||
tensormap.replace.tile.global_dim.shared::cta.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.global_dim.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .shared::cta }
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tensormap_replace_global_dim(
|
||||
cuda::ptx::space_shared_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> ord,
|
||||
B32 new_val);
|
||||
|
||||
tensormap.replace.tile.global_stride.global.b1024.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.global_stride.space.b1024.b64 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .global }
|
||||
template <int N32, typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline void tensormap_replace_global_stride(
|
||||
cuda::ptx::space_global_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> ord,
|
||||
B64 new_val);
|
||||
|
||||
tensormap.replace.tile.global_stride.shared::cta.b1024.b64
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.global_stride.space.b1024.b64 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .shared::cta }
|
||||
template <int N32, typename B64, enable_if_t<sizeof(B64) == 8, bool> = true>
|
||||
__device__ static inline void tensormap_replace_global_stride(
|
||||
cuda::ptx::space_shared_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> ord,
|
||||
B64 new_val);
|
||||
|
||||
tensormap.replace.tile.element_stride.global.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .global }
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tensormap_replace_element_stride(
|
||||
cuda::ptx::space_global_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> ord,
|
||||
B32 new_val);
|
||||
|
||||
tensormap.replace.tile.element_stride.shared::cta.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .shared::cta }
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tensormap_replace_element_stride(
|
||||
cuda::ptx::space_shared_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> ord,
|
||||
B32 new_val);
|
||||
|
||||
tensormap.replace.tile.element_stride.global.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .global }
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tensormap_replace_element_size(
|
||||
cuda::ptx::space_global_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> ord,
|
||||
B32 new_val);
|
||||
|
||||
tensormap.replace.tile.element_stride.shared::cta.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.element_stride.space.b1024.b32 [tm_addr], ord, new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .shared::cta }
|
||||
template <int N32, typename B32, enable_if_t<sizeof(B32) == 4, bool> = true>
|
||||
__device__ static inline void tensormap_replace_element_size(
|
||||
cuda::ptx::space_shared_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> ord,
|
||||
B32 new_val);
|
||||
|
||||
tensormap.replace.tile.elemtype.global.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.elemtype.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .global }
|
||||
template <int N32>
|
||||
__device__ static inline void tensormap_replace_elemtype(
|
||||
cuda::ptx::space_global_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> new_val);
|
||||
|
||||
tensormap.replace.tile.elemtype.shared::cta.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.elemtype.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .shared::cta }
|
||||
template <int N32>
|
||||
__device__ static inline void tensormap_replace_elemtype(
|
||||
cuda::ptx::space_shared_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> new_val);
|
||||
|
||||
tensormap.replace.tile.interleave_layout.global.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.interleave_layout.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .global }
|
||||
template <int N32>
|
||||
__device__ static inline void tensormap_replace_interleave_layout(
|
||||
cuda::ptx::space_global_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> new_val);
|
||||
|
||||
tensormap.replace.tile.interleave_layout.shared::cta.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.interleave_layout.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .shared::cta }
|
||||
template <int N32>
|
||||
__device__ static inline void tensormap_replace_interleave_layout(
|
||||
cuda::ptx::space_shared_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> new_val);
|
||||
|
||||
tensormap.replace.tile.swizzle_mode.global.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.swizzle_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .global }
|
||||
template <int N32>
|
||||
__device__ static inline void tensormap_replace_swizzle_mode(
|
||||
cuda::ptx::space_global_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> new_val);
|
||||
|
||||
tensormap.replace.tile.swizzle_mode.shared::cta.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.swizzle_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .shared::cta }
|
||||
template <int N32>
|
||||
__device__ static inline void tensormap_replace_swizzle_mode(
|
||||
cuda::ptx::space_shared_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> new_val);
|
||||
|
||||
tensormap.replace.tile.fill_mode.global.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.fill_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .global }
|
||||
template <int N32>
|
||||
__device__ static inline void tensormap_replace_fill_mode(
|
||||
cuda::ptx::space_global_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> new_val);
|
||||
|
||||
tensormap.replace.tile.fill_mode.shared::cta.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.fill_mode.space.b1024.b32 [tm_addr], new_val; // PTX ISA 83, SM_90a, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .shared::cta }
|
||||
template <int N32>
|
||||
__device__ static inline void tensormap_replace_fill_mode(
|
||||
cuda::ptx::space_shared_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> new_val);
|
||||
|
||||
tensormap.replace.tile.swizzle_atomicity.global.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.swizzle_atomicity.space.b1024.b32 [tm_addr], new_val; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .global }
|
||||
template <int N32>
|
||||
__device__ static inline void tensormap_replace_swizzle_atomicity(
|
||||
cuda::ptx::space_global_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> new_val);
|
||||
|
||||
tensormap.replace.tile.swizzle_atomicity.shared::cta.b1024.b32
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// tensormap.replace.tile.swizzle_atomicity.space.b1024.b32 [tm_addr], new_val; // PTX ISA 86, SM_100a, SM_100f, SM_103a, SM_103f, SM_110a, SM_110f, SM_120a, SM_120f, SM_121a, SM_121f
|
||||
// .space = { .shared::cta }
|
||||
template <int N32>
|
||||
__device__ static inline void tensormap_replace_swizzle_atomicity(
|
||||
cuda::ptx::space_shared_t,
|
||||
void* tm_addr,
|
||||
cuda::ptx::n32_t<N32> new_val);
|
||||
@@ -0,0 +1,10 @@
|
||||
..
|
||||
This file was automatically generated. Do not edit.
|
||||
|
||||
trap
|
||||
^^^^
|
||||
.. code-block:: cuda
|
||||
|
||||
// trap; // PTX ISA 10, SM_50
|
||||
template <typename = void>
|
||||
__device__ static inline void trap();
|
||||
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-getctarank:
|
||||
|
||||
getctarank
|
||||
==========
|
||||
|
||||
- PTX ISA:
|
||||
`getctarank <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-getctarank>`__
|
||||
|
||||
.. include:: generated/getctarank.rst
|
||||
9
cccl_upstream/docs/libcudacxx/ptx/instructions/ld.rst
Normal file
9
cccl_upstream/docs/libcudacxx/ptx/instructions/ld.rst
Normal file
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-ld:
|
||||
|
||||
ld
|
||||
==
|
||||
|
||||
- PTX ISA:
|
||||
`ld <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld>`__
|
||||
|
||||
.. include:: generated/ld.rst
|
||||
@@ -0,0 +1,80 @@
|
||||
|
||||
shfl.sync
|
||||
^^^^^^^^^
|
||||
|
||||
.. code:: cuda
|
||||
|
||||
// PTX ISA 6.0
|
||||
// shfl.sync.mode.b32 d[|p], a, b, c, membermask;
|
||||
// .mode = { .up, .down, .bfly, .idx };
|
||||
|
||||
template<typename T>
|
||||
[[nodiscard]] __device__ static inline
|
||||
T shfl_sync_idx(T data,
|
||||
uint32_t lane_idx_offset,
|
||||
uint32_t clamp_segmask,
|
||||
uint32_t lane_mask) noexcept;
|
||||
|
||||
template<typename T>
|
||||
[[nodiscard]] __device__ static inline
|
||||
T shfl_sync_idx(T data,
|
||||
bool& pred,
|
||||
uint32_t lane_idx_offset,
|
||||
uint32_t clamp_segmask,
|
||||
uint32_t lane_mask) noexcept;
|
||||
|
||||
template<typename T>
|
||||
[[nodiscard]] __device__ static inline
|
||||
T shfl_sync_up(T data,
|
||||
uint32_t lane_idx_offset,
|
||||
uint32_t clamp_segmask,
|
||||
uint32_t lane_mask) noexcept;
|
||||
|
||||
template<typename T>
|
||||
[[nodiscard]] __device__ static inline
|
||||
T shfl_sync_up(T data,
|
||||
bool& pred,
|
||||
uint32_t lane_idx_offset,
|
||||
uint32_t clamp_segmask,
|
||||
uint32_t lane_mask) noexcept;
|
||||
|
||||
template<typename T>
|
||||
[[nodiscard]] __device__ static inline
|
||||
T shfl_sync_down(T data,
|
||||
uint32_t lane_idx_offset,
|
||||
uint32_t clamp_segmask,
|
||||
uint32_t lane_mask) noexcept;
|
||||
|
||||
template<typename T>
|
||||
[[nodiscard]] __device__ static inline
|
||||
T shfl_sync_down(T data,
|
||||
bool& pred,
|
||||
uint32_t lane_idx_offset,
|
||||
uint32_t clamp_segmask,
|
||||
uint32_t lane_mask) noexcept;
|
||||
|
||||
template<typename T>
|
||||
[[nodiscard]] __device__ static inline
|
||||
T shfl_sync_bfly(T data,
|
||||
uint32_t lane_idx_offset,
|
||||
uint32_t clamp_segmask,
|
||||
uint32_t lane_mask) noexcept;
|
||||
|
||||
template<typename T>
|
||||
[[nodiscard]] __device__ static inline
|
||||
T shfl_sync_bfly(T data,
|
||||
bool& pred,
|
||||
uint32_t lane_idx_offset,
|
||||
uint32_t clamp_segmask,
|
||||
uint32_t lane_mask) noexcept;
|
||||
|
||||
**Constrains and checks**
|
||||
|
||||
The following conditions are checked at *run-time* in debug mode:
|
||||
|
||||
- ``T`` must have 32-bit size (compile-time)
|
||||
- ``lane_idx_offset`` must be less than the warp size
|
||||
- ``clamp_segmask`` must use the bit positions [0:4] and [8:12])
|
||||
- ``lane_mask`` must be a subset of the active mask
|
||||
- All lanes must have the same value for ``lane_mask``
|
||||
- The destination lane must be a member of the ``lane_mask``
|
||||
37
cccl_upstream/docs/libcudacxx/ptx/instructions/mapa.rst
Normal file
37
cccl_upstream/docs/libcudacxx/ptx/instructions/mapa.rst
Normal file
@@ -0,0 +1,37 @@
|
||||
.. _libcudacxx-ptx-instructions-mapa:
|
||||
|
||||
mapa
|
||||
====
|
||||
|
||||
- PTX ISA:
|
||||
`mapa <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mapa>`__
|
||||
|
||||
This instruction can `currently not be
|
||||
implemented <https://github.com/NVIDIA/cccl/issues/1414>`__ by libcu++.
|
||||
The instruction can be accessed through the cooperative groups
|
||||
`cluster_group <https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#cluster-group>`__
|
||||
API:
|
||||
|
||||
Usage:
|
||||
------
|
||||
|
||||
.. code:: cuda
|
||||
|
||||
#include <cooperative_groups.h>
|
||||
|
||||
__cluster_dims__(2)
|
||||
__global__ void kernel() {
|
||||
__shared__ int x;
|
||||
x = 1;
|
||||
namespace cg = cooperative_groups;
|
||||
cg::cluster_group cluster = cg::this_cluster();
|
||||
|
||||
cluster.sync();
|
||||
|
||||
// Get address of remote shared memory value:
|
||||
unsigned int other_block_rank = cluster.block_rank() ^ 1;
|
||||
int * remote_x = cluster.map_shared_rank(&bar, other_block_rank);
|
||||
|
||||
// Write to remote value:
|
||||
*remote_x = 2;
|
||||
}
|
||||
@@ -0,0 +1,68 @@
|
||||
.. _libcudacxx-ptx-instructions-mbarrier-arrive:
|
||||
|
||||
mbarrier.arrive
|
||||
===============
|
||||
|
||||
- PTX ISA:
|
||||
`mbarrier.arrive <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-arrive>`__
|
||||
|
||||
.. _mbarrier.arrive-1:
|
||||
|
||||
mbarrier.arrive
|
||||
---------------
|
||||
|
||||
Some of the listed PTX instructions below are semantically equivalent.
|
||||
They differ in one important way: the shorter instructions are typically
|
||||
supported on older compilers.
|
||||
|
||||
.. include:: generated/mbarrier_arrive.rst
|
||||
|
||||
mbarrier.arrive.no_complete
|
||||
---------------------------
|
||||
|
||||
.. include:: generated/mbarrier_arrive_no_complete.rst
|
||||
|
||||
mbarrier.arrive.expect_tx
|
||||
-------------------------
|
||||
|
||||
.. include:: generated/mbarrier_arrive_expect_tx.rst
|
||||
|
||||
Usage
|
||||
-----
|
||||
|
||||
.. code:: cuda
|
||||
|
||||
#include <cuda/ptx>
|
||||
#include <cuda/barrier>
|
||||
#include <cooperative_groups.h>
|
||||
|
||||
__global__ void kernel() {
|
||||
using cuda::ptx::sem_release;
|
||||
using cuda::ptx::space_cluster;
|
||||
using cuda::ptx::space_shared;
|
||||
using cuda::ptx::scope_cluster;
|
||||
using cuda::ptx::scope_cta;
|
||||
|
||||
using barrier_t = cuda::barrier<cuda::thread_scope_block>;
|
||||
__shared__ barrier_t bar;
|
||||
init(&bar, blockDim.x);
|
||||
__syncthreads();
|
||||
|
||||
NV_IF_TARGET(NV_PROVIDES_SM_90, (
|
||||
// Arrive on local shared memory barrier:
|
||||
uint64_t token;
|
||||
token = cuda::ptx::mbarrier_arrive_expect_tx(sem_release, scope_cluster, space_shared, &bar, 1);
|
||||
|
||||
// Get address of remote cluster barrier:
|
||||
namespace cg = cooperative_groups;
|
||||
cg::cluster_group cluster = cg::this_cluster();
|
||||
unsigned int other_block_rank = cluster.block_rank() ^ 1;
|
||||
uint64_t * remote_bar = cluster.map_shared_rank(&bar, other_block_rank);
|
||||
|
||||
// Sync cluster to ensure remote barrier is initialized.
|
||||
cluster.sync();
|
||||
|
||||
// Arrive on remote cluster barrier:
|
||||
cuda::ptx::mbarrier_arrive_expect_tx(sem_release, scope_cluster, space_cluster, remote_bar, 1);
|
||||
)
|
||||
}
|
||||
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-mbarrier-expect_tx:
|
||||
|
||||
mbarrier.expect_tx
|
||||
==================
|
||||
|
||||
- PTX ISA:
|
||||
`mbarrier.expect_tx <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-expect-tx>`__
|
||||
|
||||
.. include:: generated/mbarrier_expect_tx.rst
|
||||
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-mbarrier-init:
|
||||
|
||||
mbarrier.init
|
||||
=============
|
||||
|
||||
- PTX ISA:
|
||||
`mbarrier.arrive <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-init>`__
|
||||
|
||||
.. include:: generated/mbarrier_init.rst
|
||||
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-mbarrier_inval:
|
||||
|
||||
mbarrier.inval
|
||||
==============
|
||||
|
||||
- PTX ISA:
|
||||
`mbarrier.inval <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-inval>`__
|
||||
|
||||
.. include:: generated/mbarrier_inval.rst
|
||||
@@ -0,0 +1,19 @@
|
||||
.. _libcudacxx-ptx-instructions-mbarrier-test_wait:
|
||||
|
||||
mbarrier.test_wait
|
||||
==================
|
||||
|
||||
- PTX ISA:
|
||||
`mbarrier.test_wait <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-mbarrier-try-wait>`__
|
||||
|
||||
.. _mbarrier.test_wait-1:
|
||||
|
||||
mbarrier.test_wait
|
||||
------------------
|
||||
|
||||
.. include:: generated/mbarrier_test_wait.rst
|
||||
|
||||
mbarrier.test_wait.parity
|
||||
-------------------------
|
||||
|
||||
.. include:: generated/mbarrier_test_wait_parity.rst
|
||||
@@ -0,0 +1,20 @@
|
||||
.. _libcudacxx-ptx-instructions-mbarrier-try_wait:
|
||||
|
||||
mbarrier.try_wait
|
||||
=================
|
||||
|
||||
- PTX ISA:
|
||||
`mbarrier.try_wait <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-mbarrier-test-wait-mbarrier-try-wait>`__
|
||||
|
||||
|
||||
.. _mbarrier.try_wait-1:
|
||||
|
||||
mbarrier.try_wait
|
||||
-----------------
|
||||
|
||||
.. include:: generated/mbarrier_try_wait.rst
|
||||
|
||||
mbarrier.try_wait.parity
|
||||
------------------------
|
||||
|
||||
.. include:: generated/mbarrier_try_wait_parity.rst
|
||||
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-multimem-ld_reduce:
|
||||
|
||||
multimem.ld_reduce
|
||||
==================
|
||||
|
||||
- PTX ISA:
|
||||
`multimem.ld_reduce <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-multimem-ld-reduce-multimem-st-multimem-red>`__
|
||||
|
||||
.. include:: generated/multimem_ld_reduce.rst
|
||||
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-multimem-red:
|
||||
|
||||
multimem.red
|
||||
============
|
||||
|
||||
- PTX ISA:
|
||||
`multimem.red <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-multimem-ld-reduce-multimem-st-multimem-red>`__
|
||||
|
||||
.. include:: generated/multimem_red.rst
|
||||
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-multimem-st:
|
||||
|
||||
multimem.st
|
||||
===========
|
||||
|
||||
- PTX ISA:
|
||||
`multimem.st <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-multimem-ld-reduce-multimem-st-multimem-red>`__
|
||||
|
||||
.. include:: generated/multimem_st.rst
|
||||
9
cccl_upstream/docs/libcudacxx/ptx/instructions/prmt.rst
Normal file
9
cccl_upstream/docs/libcudacxx/ptx/instructions/prmt.rst
Normal file
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-prmt:
|
||||
|
||||
prmt
|
||||
====
|
||||
|
||||
- PTX ISA:
|
||||
`prmt <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-prmt>`__
|
||||
|
||||
.. include:: generated/prmt.rst
|
||||
31
cccl_upstream/docs/libcudacxx/ptx/instructions/red_async.rst
Normal file
31
cccl_upstream/docs/libcudacxx/ptx/instructions/red_async.rst
Normal file
@@ -0,0 +1,31 @@
|
||||
.. _libcudacxx-ptx-instructions-mbarrier-red-async:
|
||||
|
||||
red.async
|
||||
=========
|
||||
|
||||
- PTX ISA:
|
||||
`red.async <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-red-async>`__
|
||||
|
||||
.. _red.async-1:
|
||||
|
||||
red.async
|
||||
---------
|
||||
|
||||
.. include:: generated/red_async.rst
|
||||
|
||||
red.async ``.s64`` emulation
|
||||
----------------------------
|
||||
|
||||
PTX does not currently (CTK 12.3) expose ``red.async.add.s64``. This
|
||||
exposure is emulated in ``cuda::ptx`` using
|
||||
|
||||
.. code:: cuda
|
||||
|
||||
// red.async.relaxed.cluster.shared::cluster.mbarrier::complete_tx::bytes{.op}.u64 [dest], value, [remote_bar]; // .u64 intentional PTX ISA 81, SM_90
|
||||
// .op = { .add }
|
||||
template <typename=void>
|
||||
__device__ static inline void red_async(
|
||||
cuda::ptx::op_add_t,
|
||||
int64_t* dest,
|
||||
const int64_t& value,
|
||||
int64_t* remote_bar);
|
||||
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-setmaxnreg:
|
||||
|
||||
setmaxnreg
|
||||
==========
|
||||
|
||||
- PTX ISA:
|
||||
`setmaxnreg <https://docs.nvidia.com/cuda/parallel-thread-execution/#miscellaneous-instructions-setmaxnreg>`__
|
||||
|
||||
.. include:: generated/setmaxnreg.rst
|
||||
10
cccl_upstream/docs/libcudacxx/ptx/instructions/shfl_sync.rst
Normal file
10
cccl_upstream/docs/libcudacxx/ptx/instructions/shfl_sync.rst
Normal file
@@ -0,0 +1,10 @@
|
||||
|
||||
.. _libcudacxx-ptx-instructions-shfl_sync:
|
||||
|
||||
shfl.sync
|
||||
=========
|
||||
|
||||
- PTX ISA:
|
||||
`shfl.sync <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-shfl-sync>`__
|
||||
|
||||
.. include:: manual/shfl_sync.rst
|
||||
9
cccl_upstream/docs/libcudacxx/ptx/instructions/shl.rst
Normal file
9
cccl_upstream/docs/libcudacxx/ptx/instructions/shl.rst
Normal file
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-shl:
|
||||
|
||||
shl
|
||||
===
|
||||
|
||||
- PTX ISA:
|
||||
`shl <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-shl>`__
|
||||
|
||||
.. include:: generated/shl.rst
|
||||
9
cccl_upstream/docs/libcudacxx/ptx/instructions/shr.rst
Normal file
9
cccl_upstream/docs/libcudacxx/ptx/instructions/shr.rst
Normal file
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-shr:
|
||||
|
||||
shr
|
||||
===
|
||||
|
||||
- PTX ISA:
|
||||
`shr <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-shr>`__
|
||||
|
||||
.. include:: generated/shr.rst
|
||||
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-special-registers:
|
||||
|
||||
Special registers
|
||||
=================
|
||||
|
||||
- PTX ISA:
|
||||
`Special Register <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#special-registers>`__
|
||||
|
||||
.. include:: generated/get_sreg.rst
|
||||
9
cccl_upstream/docs/libcudacxx/ptx/instructions/st.rst
Normal file
9
cccl_upstream/docs/libcudacxx/ptx/instructions/st.rst
Normal file
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-st:
|
||||
|
||||
st
|
||||
==
|
||||
|
||||
- PTX ISA:
|
||||
`st <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-st>`__
|
||||
|
||||
.. include:: generated/st.rst
|
||||
14
cccl_upstream/docs/libcudacxx/ptx/instructions/st_async.rst
Normal file
14
cccl_upstream/docs/libcudacxx/ptx/instructions/st_async.rst
Normal file
@@ -0,0 +1,14 @@
|
||||
.. _libcudacxx-ptx-instructions-st-async:
|
||||
|
||||
st.async
|
||||
========
|
||||
|
||||
- PTX ISA:
|
||||
`st.async <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-st-async>`__
|
||||
- Used in: :ref:`How to use st.async <libcudacxx-ptx-examples-st-async>`
|
||||
|
||||
**NOTE.** Alignment of ``addr`` must be a multiple of vector size. For
|
||||
instance, the ``addr`` supplied to the ``v2.b32`` variant must be
|
||||
aligned to ``2 x 4 = 8`` bytes.
|
||||
|
||||
.. include:: generated/st_async.rst
|
||||
@@ -0,0 +1,9 @@
|
||||
.. _libcudacxx-ptx-instructions-st-bulk:
|
||||
|
||||
st.bulk
|
||||
========
|
||||
|
||||
- PTX ISA:
|
||||
`st.bulk <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-st-bulk>`__
|
||||
|
||||
.. include:: generated/st_bulk.rst
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user