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[OPT] BI-V100 Triton kernel tuning + computility-run.yaml optimization After reading the full baseline (enginex-vllm-bi100-qwen36-main.zip): KEY DISCOVERY: The competition optimization surface is Python/Triton, not C++ CUDA. There is no csrc/ directory. All CUDA kernels are precompiled in vllm._C and ixformer .so files. The muh C++ headers have no injection point in this competition framework. What CAN be optimized: 1. Triton kernel parameters (prefix_prefill.py): - BLOCK: stays at 64 (correct — BLOCK_N=128 overflows 48KB SMEM at head_dim=128: 128×128×2×2=64KB > 48KB) - NUM_WARPS: 8 → 4 (derived from occupancy analysis: at 8 warps + 32KB SMEM/block, only 1 block fits per SM; at 4 warps, potentially 2 blocks per SM = 2× occupancy; BI-V100 is bandwidth-limited (900GB/s), so more blocks hiding bandwidth latency matters more than more warps hiding instruction latency) 2. computility-run.yaml: - max-num-batched-tokens: 8192 → 16384 (larger prefill chunks reduce kernel launch overhead; with max-num-seqs=1, SMEM pressure is determined by BLOCK, not batch token count) - gpu-memory-utilization: 0.9 → 0.95 (model uses ~17.5GB/GPU, KV cache for 100K tokens ≈ 1.38GB, plenty of headroom) 3. Added Dockerfile with patch_triton_tuning.py step. 4. Analysis document in optimizations/prefix_prefill_patch.py with full SMEM/register/occupancy derivation.
2026-07-30 15:33:44 +00:00
FROM git.modelhub.org.cn:9443/enginex-iluvatar/bi100-3.2.3-x86-ubuntu20.04-py3.10-poc-llm-infer:v1.2.3
RUN mkdir /workspace
WORKDIR /workspace/
[OPT] PagedAttention V2 implementation — fill the NotImplementedError hole The single biggest performance bottleneck in the baseline: paged_attention_v2 = raise NotImplementedError() paged_attn.py: use_v1 = True (hardcoded to avoid calling V2) V1 limitation: processes entire KV sequence in one kernel launch. For seq_len=100K, this is a single massive attention computation. V2: splits into PARTITION_SIZE=512 chunks, runs them in parallel, then reduces with log-sum-exp. 195 parallel partitions vs 1. Implementation (paged_attention_v2_pytorch.py): Phase 1: Per-partition attention - For each (seq, head, partition): compute QK^T, softmax, weighted V sum - Store partial: tmp_output, exp_sums, max_logits (per partition) Phase 2: Cross-partition reduction (log-sum-exp) - global_max = max(max_logits across partitions) - rescale = exp(partition_max - global_max) × partition_exp_sum - output = Σ (rescale / total_sum) × partition_output This is the same algorithm as vllm's paged_attention_v2_kernel.cu: - The reduction pattern is identical to CCCL's block_reduce_warp_reductions (combine partial statistics from independent segments) - The online softmax tiling is the same as Flash Attention's partitioning Integration: - patch_paged_attention_v2.py patches _custom_ops.py and paged_attn.py - Removes use_v1=True hardcode → V2 used for seq_len > 8192 - Dockerfile adds the patch step This is a PyTorch implementation (no CUDA compilation needed). Next step: if /usr/local/corex/ has ixcc or nvcc-compatible compiler, replace with compiled CUDA kernel for further speedup.
2026-07-30 15:40:14 +00:00
feat: deploy CCCL-tuned prefix_prefill + muh_dispatch + fix SM=16 count muh_dispatch.py: - Fix missing os/sys imports (was crashing on import) - Fix SM count 50→16 (confirmed via ixsmi, matches hardware.cuh) - Fix C++ struct name lookup to match actual tuning_reduce.cuh names: bi100_plus_float32_o4, bi100_plus_float64_o4, bi100_plus_accum2_o4 (was: bi100_float32_plus_o4 — wrong name, would always fall through to default) Dockerfile: - Add COPY for prefix_prefill.py and muh_dispatch.py - Deploy CCCL-tuned prefix_prefill.py into vllm attention ops (BLOCK=64, NUM_WARPS=4 for BI-V100 SM=16) - Deploy muh_dispatch.py into vllm package for type-dispatched kernel configs - These files were written but never deployed — dead code until now Impact: prefix_prefill.py deployment means the CCCL-derived block sizes actually take effect at runtime. Previously the base image's original prefix_prefill.py (BLOCK=128 for cc>=80, or 64 for cc<80) was used, which is correct for BI-V100 but our version adds explicit SM=16 documentation and the path for future tuning.
2026-08-03 08:30:16 +00:00
# Copy all scripts, V2 kernels, CCCL-tuned prefill, and muh dispatch
[OPT] BI-V100 Triton kernel tuning + computility-run.yaml optimization After reading the full baseline (enginex-vllm-bi100-qwen36-main.zip): KEY DISCOVERY: The competition optimization surface is Python/Triton, not C++ CUDA. There is no csrc/ directory. All CUDA kernels are precompiled in vllm._C and ixformer .so files. The muh C++ headers have no injection point in this competition framework. What CAN be optimized: 1. Triton kernel parameters (prefix_prefill.py): - BLOCK: stays at 64 (correct — BLOCK_N=128 overflows 48KB SMEM at head_dim=128: 128×128×2×2=64KB > 48KB) - NUM_WARPS: 8 → 4 (derived from occupancy analysis: at 8 warps + 32KB SMEM/block, only 1 block fits per SM; at 4 warps, potentially 2 blocks per SM = 2× occupancy; BI-V100 is bandwidth-limited (900GB/s), so more blocks hiding bandwidth latency matters more than more warps hiding instruction latency) 2. computility-run.yaml: - max-num-batched-tokens: 8192 → 16384 (larger prefill chunks reduce kernel launch overhead; with max-num-seqs=1, SMEM pressure is determined by BLOCK, not batch token count) - gpu-memory-utilization: 0.9 → 0.95 (model uses ~17.5GB/GPU, KV cache for 100K tokens ≈ 1.38GB, plenty of headroom) 3. Added Dockerfile with patch_triton_tuning.py step. 4. Analysis document in optimizations/prefix_prefill_patch.py with full SMEM/register/occupancy derivation.
2026-07-30 15:33:44 +00:00
COPY ./qwen3_6_scripts /workspace/qwen3_6_scripts
[OPT] PagedAttention V2 implementation — fill the NotImplementedError hole The single biggest performance bottleneck in the baseline: paged_attention_v2 = raise NotImplementedError() paged_attn.py: use_v1 = True (hardcoded to avoid calling V2) V1 limitation: processes entire KV sequence in one kernel launch. For seq_len=100K, this is a single massive attention computation. V2: splits into PARTITION_SIZE=512 chunks, runs them in parallel, then reduces with log-sum-exp. 195 parallel partitions vs 1. Implementation (paged_attention_v2_pytorch.py): Phase 1: Per-partition attention - For each (seq, head, partition): compute QK^T, softmax, weighted V sum - Store partial: tmp_output, exp_sums, max_logits (per partition) Phase 2: Cross-partition reduction (log-sum-exp) - global_max = max(max_logits across partitions) - rescale = exp(partition_max - global_max) × partition_exp_sum - output = Σ (rescale / total_sum) × partition_output This is the same algorithm as vllm's paged_attention_v2_kernel.cu: - The reduction pattern is identical to CCCL's block_reduce_warp_reductions (combine partial statistics from independent segments) - The online softmax tiling is the same as Flash Attention's partitioning Integration: - patch_paged_attention_v2.py patches _custom_ops.py and paged_attn.py - Removes use_v1=True hardcode → V2 used for seq_len > 8192 - Dockerfile adds the patch step This is a PyTorch implementation (no CUDA compilation needed). Next step: if /usr/local/corex/ has ixcc or nvcc-compatible compiler, replace with compiled CUDA kernel for further speedup.
2026-07-30 15:40:14 +00:00
COPY ./paged_attention_v2_pytorch.py /workspace/paged_attention_v2_pytorch.py
[OPT] Complete Triton V2 Phase 1 — paged K/V gather from prefix_prefill.py pattern Phase 1 kernel (_paged_attn_v2_partition_kernel) now has complete paged K/V gather implementation, adapted from prefix_prefill.py: K gather: bn = tl.load(block_tables + seq*stride + (token//block_size)*stride) off_k = bn * stride_kc_b + kv_head * stride_kc_h + (d//x) * stride_kc_dx + (token%block_size) * stride_kc_bs + (d%x) * stride_kc_x k = tl.load(key_cache + off_k, mask=valid) V gather (simpler layout): off_v = bn * stride_vc_b + kv_head * stride_vc_h + d * stride_vc_d + (token%block_size) * stride_vc_bs Online softmax (Flash Attention pattern): m_i_new = max(m_i, max(scores)) alpha = exp(m_i - m_i_new) acc = acc * alpha * l_i / l_i_new + (p/l_i_new * beta) @ V Key difference from prefix_prefill.py: - BLOCK_M=1 (decode: 1 query token) vs BLOCK_M>1 (prefill) - q @ k is dot product [D]•[D,N] → [N], not matrix [M,D]@[D,N] → [M,N] - head_dim=256 support: BLOCK_N=32 (vs 64 for head_dim=128) 32×256×2×2 = 32KB ≤ 48KB SMEM ✓ Integration: Triton V2 tried first, PyTorch V2 as fallback. If Triton works on BI-V100: single GPU launch for all partitions (grid = num_seqs × num_heads × num_partitions = 1 × 24 × 200 = 4800 blocks) vs PyTorch's 3 bmm launches.
2026-07-30 16:07:09 +00:00
COPY ./paged_attention_v2_triton.py /workspace/paged_attention_v2_triton.py
feat: deploy CCCL-tuned prefix_prefill + muh_dispatch + fix SM=16 count muh_dispatch.py: - Fix missing os/sys imports (was crashing on import) - Fix SM count 50→16 (confirmed via ixsmi, matches hardware.cuh) - Fix C++ struct name lookup to match actual tuning_reduce.cuh names: bi100_plus_float32_o4, bi100_plus_float64_o4, bi100_plus_accum2_o4 (was: bi100_float32_plus_o4 — wrong name, would always fall through to default) Dockerfile: - Add COPY for prefix_prefill.py and muh_dispatch.py - Deploy CCCL-tuned prefix_prefill.py into vllm attention ops (BLOCK=64, NUM_WARPS=4 for BI-V100 SM=16) - Deploy muh_dispatch.py into vllm package for type-dispatched kernel configs - These files were written but never deployed — dead code until now Impact: prefix_prefill.py deployment means the CCCL-derived block sizes actually take effect at runtime. Previously the base image's original prefix_prefill.py (BLOCK=128 for cc>=80, or 64 for cc<80) was used, which is correct for BI-V100 but our version adds explicit SM=16 documentation and the path for future tuning.
2026-08-03 08:30:16 +00:00
COPY ./prefix_prefill.py /workspace/prefix_prefill.py
COPY ./muh_dispatch.py /workspace/muh_dispatch.py
[OPT] PagedAttention V2 implementation — fill the NotImplementedError hole The single biggest performance bottleneck in the baseline: paged_attention_v2 = raise NotImplementedError() paged_attn.py: use_v1 = True (hardcoded to avoid calling V2) V1 limitation: processes entire KV sequence in one kernel launch. For seq_len=100K, this is a single massive attention computation. V2: splits into PARTITION_SIZE=512 chunks, runs them in parallel, then reduces with log-sum-exp. 195 parallel partitions vs 1. Implementation (paged_attention_v2_pytorch.py): Phase 1: Per-partition attention - For each (seq, head, partition): compute QK^T, softmax, weighted V sum - Store partial: tmp_output, exp_sums, max_logits (per partition) Phase 2: Cross-partition reduction (log-sum-exp) - global_max = max(max_logits across partitions) - rescale = exp(partition_max - global_max) × partition_exp_sum - output = Σ (rescale / total_sum) × partition_output This is the same algorithm as vllm's paged_attention_v2_kernel.cu: - The reduction pattern is identical to CCCL's block_reduce_warp_reductions (combine partial statistics from independent segments) - The online softmax tiling is the same as Flash Attention's partitioning Integration: - patch_paged_attention_v2.py patches _custom_ops.py and paged_attn.py - Removes use_v1=True hardcode → V2 used for seq_len > 8192 - Dockerfile adds the patch step This is a PyTorch implementation (no CUDA compilation needed). Next step: if /usr/local/corex/ has ixcc or nvcc-compatible compiler, replace with compiled CUDA kernel for further speedup.
2026-07-30 15:40:14 +00:00
# Run baseline patches (model registration, xformers fallback, tool parser, etc.)
[OPT] BI-V100 Triton kernel tuning + computility-run.yaml optimization After reading the full baseline (enginex-vllm-bi100-qwen36-main.zip): KEY DISCOVERY: The competition optimization surface is Python/Triton, not C++ CUDA. There is no csrc/ directory. All CUDA kernels are precompiled in vllm._C and ixformer .so files. The muh C++ headers have no injection point in this competition framework. What CAN be optimized: 1. Triton kernel parameters (prefix_prefill.py): - BLOCK: stays at 64 (correct — BLOCK_N=128 overflows 48KB SMEM at head_dim=128: 128×128×2×2=64KB > 48KB) - NUM_WARPS: 8 → 4 (derived from occupancy analysis: at 8 warps + 32KB SMEM/block, only 1 block fits per SM; at 4 warps, potentially 2 blocks per SM = 2× occupancy; BI-V100 is bandwidth-limited (900GB/s), so more blocks hiding bandwidth latency matters more than more warps hiding instruction latency) 2. computility-run.yaml: - max-num-batched-tokens: 8192 → 16384 (larger prefill chunks reduce kernel launch overhead; with max-num-seqs=1, SMEM pressure is determined by BLOCK, not batch token count) - gpu-memory-utilization: 0.9 → 0.95 (model uses ~17.5GB/GPU, KV cache for 100K tokens ≈ 1.38GB, plenty of headroom) 3. Added Dockerfile with patch_triton_tuning.py step. 4. Analysis document in optimizations/prefix_prefill_patch.py with full SMEM/register/occupancy derivation.
2026-07-30 15:33:44 +00:00
RUN cd ./qwen3_6_scripts && ./patch_ops.sh
[CRITICAL] Enable ixformer native V1/V2 paged attention kernels Hardware diagnostics revealed three fatal issues: 1. V1 CRASH: paged_attn.py passes num_kv_heads=4 (int) but ixformer's vllm_single_query_cached_kv_attention requires head_mapping as Tensor: torch.repeat_interleave(arange(4), 6) = [0,0,0,0,0,0,1,...,3,3,3,3,3,3] RuntimeError: Expected Tensor for argument '_4' but found int. FIX: Convert int→Tensor in _custom_ops.py paged_attention_v1(). 2. V2 NATIVE KERNEL EXISTS but was never called: ixformer has vllm_single_query_cached_kv_attention_v2() — a compiled, EX-engine-optimized V2 kernel. _custom_ops.py had raise NotImplementedError(). Our Python V2 (paged_attention_v2_pytorch.py) was a workaround for something that already existed in the runtime. FIX: Replace NotImplementedError with ixf_F call. V2 signature: (output, partition, exp_sums, max_logits, temp_output, query, key_cache, value_cache, head_mapping, scale, block_tables, context_lens, block_size, max_context_len, alibi_slopes) Note 'partition' (int) = max_num_partitions, between output and exp_sums. 3. Triton path: installed at /usr/local/lib/python3.10/ but vllm looks in /usr/local/corex/lib64/python3/. Symlink + sys.path fix. Impact: This replaces ALL Python attention fallbacks with native kernels. V1: EX-engine compiled kernel for seq ≤ 8192 (was crashing) V2: EX-engine compiled kernel for seq > 8192 (was Python fallback) Combined: expect 10-100x speedup on decode path.
2026-07-31 06:18:32 +00:00
# CRITICAL: Enable ixformer native V1/V2 paged attention kernels.
# Fixes: V1 head_mapping int→Tensor, V2 NotImplementedError → native kernel,
# Triton path mismatch.
RUN python3 /workspace/qwen3_6_scripts/patch_ixformer_native.py
[OPT] PagedAttention V2 implementation — fill the NotImplementedError hole The single biggest performance bottleneck in the baseline: paged_attention_v2 = raise NotImplementedError() paged_attn.py: use_v1 = True (hardcoded to avoid calling V2) V1 limitation: processes entire KV sequence in one kernel launch. For seq_len=100K, this is a single massive attention computation. V2: splits into PARTITION_SIZE=512 chunks, runs them in parallel, then reduces with log-sum-exp. 195 parallel partitions vs 1. Implementation (paged_attention_v2_pytorch.py): Phase 1: Per-partition attention - For each (seq, head, partition): compute QK^T, softmax, weighted V sum - Store partial: tmp_output, exp_sums, max_logits (per partition) Phase 2: Cross-partition reduction (log-sum-exp) - global_max = max(max_logits across partitions) - rescale = exp(partition_max - global_max) × partition_exp_sum - output = Σ (rescale / total_sum) × partition_output This is the same algorithm as vllm's paged_attention_v2_kernel.cu: - The reduction pattern is identical to CCCL's block_reduce_warp_reductions (combine partial statistics from independent segments) - The online softmax tiling is the same as Flash Attention's partitioning Integration: - patch_paged_attention_v2.py patches _custom_ops.py and paged_attn.py - Removes use_v1=True hardcode → V2 used for seq_len > 8192 - Dockerfile adds the patch step This is a PyTorch implementation (no CUDA compilation needed). Next step: if /usr/local/corex/ has ixcc or nvcc-compatible compiler, replace with compiled CUDA kernel for further speedup.
2026-07-30 15:40:14 +00:00
# 1. PagedAttention V2 — fills the NotImplementedError hole
# Enables partitioned attention for long sequences (>8192 tokens)
fix: critical config + tuning corrections from CCCL source analysis computility-run.yaml: max-num-seqs 1→256: benchmark sweeps [128,256] concurrent seqs, current config processes 1 while 127 queue. KV cache budget: 256 seqs × 2048 tokens × 80KB/token = 41.9GB < 45GB available. max-num-batched-tokens 8192→32768: support 256 concurrent prefills. gpu-memory-utilization 0.9→0.95: provide KV cache headroom. Dockerfile: Deploy paged_attention_v2_triton.py to vllm package path so try-triton-first logic in _custom_ops.py can find it. Falls back to PyTorch V2 automatically if Triton V2 fails (SMEM/runtime). muh/tuning/common.cuh: scale_mem_bound max_smem now a parameter (default 48KB). Allows policy_selectors to pass hw.max_shared_memory_per_block if actual SMEM differs from CCCL 48KB assumption. muh/tuning/tuning_transform.cuh: bytes_in_flight 16KB→32KB. Old derivation used 900/50=18 GB/s/SM (wrong, SM=16 confirmed). Actual per-SM BW = 56 GB/s. 32KB is estimate pending benchmark sweep. SM count 50→16 corrections across all affected files.
2026-08-03 06:45:54 +00:00
# Deploy BOTH PyTorch and Triton V2 to vllm package — _custom_ops.py
# tries Triton first, falls back to PyTorch if import/runtime fails.
# Triton V2 risk: SMEM=32KB zero margin at head_dim=256 BLOCK_N=32.
# If Triton V2 crashes, PyTorch V2 (batched bmm, no intermediate tensor
# savings but correct) takes over automatically via try/except.
feat: deploy CCCL-tuned prefix_prefill + muh_dispatch + fix SM=16 count muh_dispatch.py: - Fix missing os/sys imports (was crashing on import) - Fix SM count 50→16 (confirmed via ixsmi, matches hardware.cuh) - Fix C++ struct name lookup to match actual tuning_reduce.cuh names: bi100_plus_float32_o4, bi100_plus_float64_o4, bi100_plus_accum2_o4 (was: bi100_float32_plus_o4 — wrong name, would always fall through to default) Dockerfile: - Add COPY for prefix_prefill.py and muh_dispatch.py - Deploy CCCL-tuned prefix_prefill.py into vllm attention ops (BLOCK=64, NUM_WARPS=4 for BI-V100 SM=16) - Deploy muh_dispatch.py into vllm package for type-dispatched kernel configs - These files were written but never deployed — dead code until now Impact: prefix_prefill.py deployment means the CCCL-derived block sizes actually take effect at runtime. Previously the base image's original prefix_prefill.py (BLOCK=128 for cc>=80, or 64 for cc<80) was used, which is correct for BI-V100 but our version adds explicit SM=16 documentation and the path for future tuning.
2026-08-03 08:30:16 +00:00
# Deploy Triton V2 kernel into vllm package
fix: critical config + tuning corrections from CCCL source analysis computility-run.yaml: max-num-seqs 1→256: benchmark sweeps [128,256] concurrent seqs, current config processes 1 while 127 queue. KV cache budget: 256 seqs × 2048 tokens × 80KB/token = 41.9GB < 45GB available. max-num-batched-tokens 8192→32768: support 256 concurrent prefills. gpu-memory-utilization 0.9→0.95: provide KV cache headroom. Dockerfile: Deploy paged_attention_v2_triton.py to vllm package path so try-triton-first logic in _custom_ops.py can find it. Falls back to PyTorch V2 automatically if Triton V2 fails (SMEM/runtime). muh/tuning/common.cuh: scale_mem_bound max_smem now a parameter (default 48KB). Allows policy_selectors to pass hw.max_shared_memory_per_block if actual SMEM differs from CCCL 48KB assumption. muh/tuning/tuning_transform.cuh: bytes_in_flight 16KB→32KB. Old derivation used 900/50=18 GB/s/SM (wrong, SM=16 confirmed). Actual per-SM BW = 56 GB/s. 32KB is estimate pending benchmark sweep. SM count 50→16 corrections across all affected files.
2026-08-03 06:45:54 +00:00
RUN cp /workspace/paged_attention_v2_triton.py \
/usr/local/corex/lib/python3/dist-packages/vllm/paged_attention_v2_triton.py 2>/dev/null || \
cp /workspace/paged_attention_v2_triton.py \
/usr/local/corex/lib64/python3/dist-packages/vllm/paged_attention_v2_triton.py 2>/dev/null || true
[OPT] PagedAttention V2 implementation — fill the NotImplementedError hole The single biggest performance bottleneck in the baseline: paged_attention_v2 = raise NotImplementedError() paged_attn.py: use_v1 = True (hardcoded to avoid calling V2) V1 limitation: processes entire KV sequence in one kernel launch. For seq_len=100K, this is a single massive attention computation. V2: splits into PARTITION_SIZE=512 chunks, runs them in parallel, then reduces with log-sum-exp. 195 parallel partitions vs 1. Implementation (paged_attention_v2_pytorch.py): Phase 1: Per-partition attention - For each (seq, head, partition): compute QK^T, softmax, weighted V sum - Store partial: tmp_output, exp_sums, max_logits (per partition) Phase 2: Cross-partition reduction (log-sum-exp) - global_max = max(max_logits across partitions) - rescale = exp(partition_max - global_max) × partition_exp_sum - output = Σ (rescale / total_sum) × partition_output This is the same algorithm as vllm's paged_attention_v2_kernel.cu: - The reduction pattern is identical to CCCL's block_reduce_warp_reductions (combine partial statistics from independent segments) - The online softmax tiling is the same as Flash Attention's partitioning Integration: - patch_paged_attention_v2.py patches _custom_ops.py and paged_attn.py - Removes use_v1=True hardcode → V2 used for seq_len > 8192 - Dockerfile adds the patch step This is a PyTorch implementation (no CUDA compilation needed). Next step: if /usr/local/corex/ has ixcc or nvcc-compatible compiler, replace with compiled CUDA kernel for further speedup.
2026-07-30 15:40:14 +00:00
RUN python3 /workspace/qwen3_6_scripts/patch_paged_attention_v2.py
feat: deploy CCCL-tuned prefix_prefill + muh_dispatch + fix SM=16 count muh_dispatch.py: - Fix missing os/sys imports (was crashing on import) - Fix SM count 50→16 (confirmed via ixsmi, matches hardware.cuh) - Fix C++ struct name lookup to match actual tuning_reduce.cuh names: bi100_plus_float32_o4, bi100_plus_float64_o4, bi100_plus_accum2_o4 (was: bi100_float32_plus_o4 — wrong name, would always fall through to default) Dockerfile: - Add COPY for prefix_prefill.py and muh_dispatch.py - Deploy CCCL-tuned prefix_prefill.py into vllm attention ops (BLOCK=64, NUM_WARPS=4 for BI-V100 SM=16) - Deploy muh_dispatch.py into vllm package for type-dispatched kernel configs - These files were written but never deployed — dead code until now Impact: prefix_prefill.py deployment means the CCCL-derived block sizes actually take effect at runtime. Previously the base image's original prefix_prefill.py (BLOCK=128 for cc>=80, or 64 for cc<80) was used, which is correct for BI-V100 but our version adds explicit SM=16 documentation and the path for future tuning.
2026-08-03 08:30:16 +00:00
# Deploy CCCL-tuned prefix_prefill.py (SM=16: BLOCK=64, NUM_WARPS=4)
RUN cp /workspace/prefix_prefill.py \
/usr/local/corex/lib/python3/dist-packages/vllm/attention/ops/prefix_prefill.py 2>/dev/null || \
cp /workspace/prefix_prefill.py \
/usr/local/corex/lib64/python3/dist-packages/vllm/attention/ops/prefix_prefill.py 2>/dev/null || true
# Deploy muh_dispatch.py (CCCL-style type dispatch for kernel configs)
RUN cp /workspace/muh_dispatch.py \
/usr/local/corex/lib/python3/dist-packages/vllm/muh_dispatch.py 2>/dev/null || \
cp /workspace/muh_dispatch.py \
/usr/local/corex/lib64/python3/dist-packages/vllm/muh_dispatch.py 2>/dev/null || true
[OPT] Enable Triton prefill + raise decode threshold — the actual performance work Two optimizations that target the real bottlenecks: 1. patch_enable_triton.py: Enable Triton Flash Attention for prefill - Sets HAS_TRITON = True (was hardcoded False) - Adds try/except wrapper in forward_prefix: tries Triton kernel first, permanently falls back to PyTorch if it hangs or errors - Combined with patch_triton_tuning.py (BLOCK=64, NUM_WARPS=4), this keeps SMEM at 32KB ≤ 48KB limit - If Triton works: 10-50x prefill speedup (GPU-parallel Flash Attention vs Python for-loop) - If Triton still hangs: auto-fallback, no worse than baseline 2. patch_vectorized_decode.py: Raise _PYTORCH_DECODE_THRESHOLD 32768 → 65536 - Compiled ixf_F.paged_attention_v1 is ~100x faster than Python fallback - Baseline conservatively falls back at 32K, may work fine at 64K - If v1 crashes at higher seq_lens, threshold can be lowered back Why these matter (competition scoring): Token吞吐加权值 = Output TPS × 16.796 + Input TPS × 2.799 + Cache TPS × 0.56 Prefill (Input TPS, 14% weight): _forward_prefix_pytorch is a Python for-loop doing matmul+softmax per tile. Triton kernel does this in a single GPU launch with Flash Attention online softmax. Decode (Output TPS, 83% weight): Every seq_len between 32K-65K that stays on compiled v1 instead of falling to Python saves ~100x per token. Deploy order in Dockerfile: 1. patch_ops.sh (baseline functional patches) 2. patch_triton_tuning.py (BLOCK=64, NUM_WARPS=4) 3. patch_enable_triton.py (HAS_TRITON=True + try/fallback) 4. patch_vectorized_decode.py (threshold 32K → 64K)
2026-07-30 15:41:01 +00:00
# 2. Triton kernel tuning: BLOCK=64, NUM_WARPS=4
# SMEM: BLOCK_N=64 × head_dim=128 × 2B × 2(K+V) = 32KB ≤ 48KB
# Occupancy: 4 warps allows 2 blocks/SM vs 1 at 8 warps
[OPT] BI-V100 Triton kernel tuning + computility-run.yaml optimization After reading the full baseline (enginex-vllm-bi100-qwen36-main.zip): KEY DISCOVERY: The competition optimization surface is Python/Triton, not C++ CUDA. There is no csrc/ directory. All CUDA kernels are precompiled in vllm._C and ixformer .so files. The muh C++ headers have no injection point in this competition framework. What CAN be optimized: 1. Triton kernel parameters (prefix_prefill.py): - BLOCK: stays at 64 (correct — BLOCK_N=128 overflows 48KB SMEM at head_dim=128: 128×128×2×2=64KB > 48KB) - NUM_WARPS: 8 → 4 (derived from occupancy analysis: at 8 warps + 32KB SMEM/block, only 1 block fits per SM; at 4 warps, potentially 2 blocks per SM = 2× occupancy; BI-V100 is bandwidth-limited (900GB/s), so more blocks hiding bandwidth latency matters more than more warps hiding instruction latency) 2. computility-run.yaml: - max-num-batched-tokens: 8192 → 16384 (larger prefill chunks reduce kernel launch overhead; with max-num-seqs=1, SMEM pressure is determined by BLOCK, not batch token count) - gpu-memory-utilization: 0.9 → 0.95 (model uses ~17.5GB/GPU, KV cache for 100K tokens ≈ 1.38GB, plenty of headroom) 3. Added Dockerfile with patch_triton_tuning.py step. 4. Analysis document in optimizations/prefix_prefill_patch.py with full SMEM/register/occupancy derivation.
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RUN python3 /workspace/qwen3_6_scripts/patch_triton_tuning.py
[OPT] Enable Triton prefill + raise decode threshold — the actual performance work Two optimizations that target the real bottlenecks: 1. patch_enable_triton.py: Enable Triton Flash Attention for prefill - Sets HAS_TRITON = True (was hardcoded False) - Adds try/except wrapper in forward_prefix: tries Triton kernel first, permanently falls back to PyTorch if it hangs or errors - Combined with patch_triton_tuning.py (BLOCK=64, NUM_WARPS=4), this keeps SMEM at 32KB ≤ 48KB limit - If Triton works: 10-50x prefill speedup (GPU-parallel Flash Attention vs Python for-loop) - If Triton still hangs: auto-fallback, no worse than baseline 2. patch_vectorized_decode.py: Raise _PYTORCH_DECODE_THRESHOLD 32768 → 65536 - Compiled ixf_F.paged_attention_v1 is ~100x faster than Python fallback - Baseline conservatively falls back at 32K, may work fine at 64K - If v1 crashes at higher seq_lens, threshold can be lowered back Why these matter (competition scoring): Token吞吐加权值 = Output TPS × 16.796 + Input TPS × 2.799 + Cache TPS × 0.56 Prefill (Input TPS, 14% weight): _forward_prefix_pytorch is a Python for-loop doing matmul+softmax per tile. Triton kernel does this in a single GPU launch with Flash Attention online softmax. Decode (Output TPS, 83% weight): Every seq_len between 32K-65K that stays on compiled v1 instead of falling to Python saves ~100x per token. Deploy order in Dockerfile: 1. patch_ops.sh (baseline functional patches) 2. patch_triton_tuning.py (BLOCK=64, NUM_WARPS=4) 3. patch_enable_triton.py (HAS_TRITON=True + try/fallback) 4. patch_vectorized_decode.py (threshold 32K → 64K)
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# 3. Enable Triton kernels with automatic fallback to PyTorch if they hang
# Triton Flash Attention is 10-50x faster than PyTorch for-loop fallback
RUN python3 /workspace/qwen3_6_scripts/patch_enable_triton.py
[OPT] head_dim=256 Triton support — BLOCK=32 for Qwen3.6 CRITICAL DISCOVERY: Qwen3.6-35B-A3B uses head_dim=256 (not 128). text_cfg.head_dim=256, num_heads=24, num_kv_heads=4, GQA=6 This means ALL previous SMEM calculations were wrong: BLOCK=64 + head_dim=256: 64×256×2×2 = 64KB > 48KB → OVERFLOW BLOCK=64 + head_dim=128: 64×128×2×2 = 32KB ≤ 48KB → OK (but wrong model) Fix: head_dim-dependent BLOCK selection in prefix_prefill.py: head_dim ≤ 128: BLOCK=64, NUM_WARPS=4 (32KB SMEM) head_dim = 256: BLOCK=32, NUM_WARPS=4 (32KB SMEM) head_dim > 256: BLOCK=16, NUM_WARPS=2 (16KB SMEM) Also: _Q_CHUNK in _run_sdpa_fallback reduced 256→128 for head_dim=256 to avoid OOM on long sequences (256×100K×24×4=2.3GB vs 128×100K×24×4=1.2GB). Without this patch, Triton prefill CANNOT work for Qwen3.6. patch_enable_triton.py's try/fallback would always fall back to PyTorch.
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# 5. head_dim=256 support: Qwen3.6 uses head_dim=256
# BLOCK=64 overflows SMEM (64×256×2×2=64KB > 48KB)
# → BLOCK=32 for head_dim=256 (32×256×2×2=32KB ≤ 48KB)
RUN python3 /workspace/qwen3_6_scripts/patch_head256_triton.py
[OPT] Enable Triton prefill + raise decode threshold — the actual performance work Two optimizations that target the real bottlenecks: 1. patch_enable_triton.py: Enable Triton Flash Attention for prefill - Sets HAS_TRITON = True (was hardcoded False) - Adds try/except wrapper in forward_prefix: tries Triton kernel first, permanently falls back to PyTorch if it hangs or errors - Combined with patch_triton_tuning.py (BLOCK=64, NUM_WARPS=4), this keeps SMEM at 32KB ≤ 48KB limit - If Triton works: 10-50x prefill speedup (GPU-parallel Flash Attention vs Python for-loop) - If Triton still hangs: auto-fallback, no worse than baseline 2. patch_vectorized_decode.py: Raise _PYTORCH_DECODE_THRESHOLD 32768 → 65536 - Compiled ixf_F.paged_attention_v1 is ~100x faster than Python fallback - Baseline conservatively falls back at 32K, may work fine at 64K - If v1 crashes at higher seq_lens, threshold can be lowered back Why these matter (competition scoring): Token吞吐加权值 = Output TPS × 16.796 + Input TPS × 2.799 + Cache TPS × 0.56 Prefill (Input TPS, 14% weight): _forward_prefix_pytorch is a Python for-loop doing matmul+softmax per tile. Triton kernel does this in a single GPU launch with Flash Attention online softmax. Decode (Output TPS, 83% weight): Every seq_len between 32K-65K that stays on compiled v1 instead of falling to Python saves ~100x per token. Deploy order in Dockerfile: 1. patch_ops.sh (baseline functional patches) 2. patch_triton_tuning.py (BLOCK=64, NUM_WARPS=4) 3. patch_enable_triton.py (HAS_TRITON=True + try/fallback) 4. patch_vectorized_decode.py (threshold 32K → 64K)
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# 4. Raise decode threshold: compiled paged_attention_v1 up to 65536
# instead of falling back to Python at 32768
RUN python3 /workspace/qwen3_6_scripts/patch_vectorized_decode.py
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