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project_6/muh/schema/transform_tile.yaml

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[MUH] Bootstrap muh toolchain — extract/parse/gen_yaml/gen_patch + baseline.muh Pipeline: 1. extract.py: Parses all 26 CCCL tuning_*.cuh → 26 YAML schemas in muh/schema/ 2. parse.py: .muh file parser with extends-inheritance + schema validation 3. gen_yaml.py: .muh → computility-run.yaml (verified: matches competition reference) 4. gen_patch.py: .muh → vllm kernel unified diff patches (6 algorithm mappings) 5. baseline.muh: Competition reference config, all tuning values pending BI-V100 benchmarks Schemas extracted: 26 algorithms, 8-19 params each, SM75/80/90/100 reference tunings Priority mapping: reduce→attention, topk→sampling, scan→paged_attention, transform→activations, batch_memcpy→KV_cache, for→RoPE Tested: extract→parse→validate→gen_yaml→gen_patch full pipeline passes
2026-07-30 10:39:06 +00:00
# muh schema for transform_tile
# Auto-extracted from cub/cub/device/dispatch/tuning/tuning_transform_tile.cuh
# Generated by muh/extract.py
algorithm: transform_tile
source: cub/cub/device/dispatch/tuning/tuning_transform_tile.cuh
parameters:
items:
type: int
range:
- 1
- 1024
step: 1
note: unknown_range
bi_v100:
status: pending_benchmark
note: Run muh benchmark on Iluvatar BI-V100 to fill these values
threads_per_block: TBD
items_per_thread: TBD
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