127 lines
4.9 KiB
C
127 lines
4.9 KiB
C
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/* Copyright 2026 The xLLM Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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https://github.com/jd-opensource/xllm/blob/main/LICENSE
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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==============================================================================*/
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// Iluvatar BI-V100 hardware constants.
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// ALL values verified by on-device probing — do NOT change without re-probing.
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//
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// Probing environment:
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// Machine: cc-adc62d1c-476c-4ee4-9647-0c011c0b6d70-0
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// Cards: 4× Iluvatar BI-V100
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// Bus-Id: 4B:00.0, 4C:00.0, 4D:00.0, 4E:00.0
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// NUMA: node 1, CPU affinity 16-31,80-95
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// Topology: flat PIX (all pairs via single PCIe bridge, equal BW)
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// IX-ML: 3.2.3
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// Driver: 3.2.1
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// CUDA ver: 10.2 (CoreX compatibility layer)
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// SDK path: /usr/local/corex/
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//
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// Probing commands used:
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// ixsmi -L → card count, names, UUIDs
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// ixsmi topo -m → PIX/PXB/PHB/SYS topology matrix
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// ixsmi -q -d MEMORY → HBM capacity per card
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// ixsmi (default) → SM clock, mem clock, TDP
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// debug_warpsize.py → warp size via CUDA kernel (warpSize builtin)
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// torch.cuda.get_device_properties() → partial (warp_size N/A on CoreX)
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#pragma once
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#include <cstdint>
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namespace xllm {
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namespace ilu_hw {
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// ---------- Core compute ----------
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/// Warp size: 64 threads (NOT 32 like NVIDIA).
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/// Verified via: CUDA kernel `warpSize` builtin → 64.
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/// torch.cuda.get_device_properties(0).warp_size returns N/A on CoreX.
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/// This affects all warp-level primitives: __shfl, __ballot, reductions, etc.
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constexpr int32_t kWarpSize = 64;
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/// SM clock: 1500 MHz (from ixsmi).
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constexpr int32_t kSmClockMHz = 1500;
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/// Memory clock: 1200 MHz (from ixsmi).
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constexpr int32_t kMemClockMHz = 1200;
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// ---------- Memory ----------
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/// HBM per card: 32768 MiB (from ixsmi -q -d MEMORY).
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constexpr int64_t kHbmPerCardMiB = 32768;
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constexpr int64_t kHbmPerCardBytes = kHbmPerCardMiB * int64_t{1024} * 1024;
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/// Baseline HBM usage (driver/runtime overhead): ~257 MiB observed idle.
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constexpr int64_t kHbmBaselineUsageMiB = 257;
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// ---------- Topology ----------
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/// Number of cards in the verified configuration.
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constexpr int32_t kVerifiedCardCount = 4;
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/// Topology kind: all pairs are PIX (single PCIe bridge, equal bandwidth).
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/// No NVLink, no HCCS mesh, no multi-switch hierarchy.
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/// If deploying on a different BI-V100 server with PXB/PHB/SYS links,
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/// use IluTopoKind::kGrouped instead.
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constexpr bool kFlatTopology = true;
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// ---------- TDP ----------
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/// TDP per card: 250W (from ixsmi Pwr cap).
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constexpr int32_t kTdpWatts = 250;
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// ---------- KV cache tensor layout (verified from runtime logs) ----------
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//
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// key_cache shape = (n_blocks, n_kv_heads_local, block_size, head_dim/x, x)
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// example = (68837, 1, 32, 16, 8)
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// value_cache shape = (n_blocks, n_kv_heads_local, head_dim, block_size)
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// example = (68837, 1, 256, 16)
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//
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// This is the transposed ("block-major") layout used by the vendor vLLM
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// for Iluvatar BI-V100. Key cache splits head_dim into two factors
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// (head_dim/x, x) where x=8 for fp16 (128-bit / sizeof(fp16)).
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// Value cache transposes block_size to the last axis.
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//
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// Source: runtime log with Qwen3.6-35B-A3B (Qwen3_5 arch), TP=4:
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// [BI100 PAGED_ATTN] decode_dispatch ... query=(1, 4, 256)
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// key_cache=(68837, 1, 32, 16, 8) value_cache=(68837, 1, 256, 16)
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// block_tables=(1, 2841) required_blocks=2841 threshold=32768
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//
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// The x factor for the key cache head_dim split:
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// x = 128 / sizeof(dtype_bits) → 128/16=8 for fp16, 128/16=8 for bf16
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constexpr int32_t kKeyCacheHeadDimSplitFp16 = 8;
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/// Default block size used by the vendor vLLM paged attention.
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constexpr int32_t kDefaultBlockSize = 16;
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// ---------- Qwen3.5 model constants (Qwen3.6-35B-A3B) ----------
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// From the model config and verified runtime shapes:
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// num_attention_heads=16, num_key_value_heads=4, head_dim=256
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// With TP=4: local_q_heads=4, local_kv_heads=1, GQA ratio=4
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// layer_types: interleaved full_attention and linear_attention
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// Linear attention layers (GDN/DeltaNet) do NOT use KV cache.
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constexpr int32_t kQwen35NumAttentionHeads = 16;
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constexpr int32_t kQwen35NumKVHeads = 4;
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constexpr int32_t kQwen35HeadDim = 256;
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constexpr int32_t kQwen35GQARatio = kQwen35NumAttentionHeads / kQwen35NumKVHeads;
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// ---------- Software ----------
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/// CUDA compatibility version exposed by CoreX SDK.
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constexpr int32_t kCudaMajor = 10;
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constexpr int32_t kCudaMinor = 2;
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} // namespace ilu_hw
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} // namespace xllm
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