---
tasks:
- text-generation

widgets:
  - task: text-generation
    inputs:
      - type: text
    examples:
      - name: 1
        title: 示例1
        inputs:
          - name: text
            data: Act as Verilog Programmer.
    inferencespec:
      cpu: 2
      memory: 8000
      gpu: 0
      gpu_memory: 16000

model-type:
- gpt

domain:
- nlp

frameworks:
- pytorch

backbone:
- transformer

containers:

metrics:
- BLEU-4
- Rouge-L

license: Apache License 2.0

finetune-support: True

language: 
- en


---

# Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework

This project use Alpaca Prompt Template to query.

~~~bash
cd alpaca-lora
python generate.py --base_model=../ --lora_weights=../siliconcompiler_peft/
python generate.py --base_model=../ --lora_weights=../nl2v_peft/
python generate.py --base_model=../ --lora_weights=../verilogrepair_peft/
~~~


## SiliconCompiler Example
**Instruction**:
~~~
Develop a Python script using siliconcompiler to run the IC design flow for the 'full_adder.v' design. Utilize the \"TSMC90\" technology, set the layout density to 30, and the clock period to 15. Specify the core area within a width of 800 and a height of 600. Add a timing constraint for the input signal 'A' to ensure it arrives at the full adder with a maximum delay of 5 units of time. Finally, generate a summary report and display the layout file.
~~~

**Output**:
~~~python
import siliconcompiler

def main():
    design = 'full_adder.v'
    technology = 'TSMC90'
    layout_density = '30'
    clock_period = 15
    core_width = 800
    core_height = 600
    input_delay = 5

    chip = siliconcompiler.Chip(design)
    chip.input(design)
    chip.load_target(technology)
    chip.clock('clk', period=clock_period)
    chip.set('constraint', 'input', 'A', 'delay', input_delay)
    chip.set('constraint', 'corearea', [(0, 0), (core_width, core_height)])
    chip.run()
    chip.summary()
    chip.show()

if __name__ == '__main__':
    main()
~~~

## Verilog Generation Example
Instruction:
~~~
Please act as a professional verilog designer.

Implement a multi-bit MUX synchronizer, data_in will remain constant during the period when data_en is high, and data_en is high for at least 3 B clock cycles. When the value of data_en is high, data can be synchronized. The data change frequency of data_in is very low. The change interval between two adjacent data is at least 10 B clock cycles.
Module name:  
    mux               
Input ports：
    input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en 
Output ports：
    output reg  [3:0] 	dataout

~~~
Output:
~~~verilog
module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en 
	output reg  [3:0] 	dataout
    );
	 
	 
	 
	 always @(posedge clk_a or posedge clk_b or posedge arstn or posedge brstn) begin
		if(arstn) begin
			dataout <= 0;
		end
		else begin
			if(data_en) begin
				dataout <= data_in;
			end
			else begin
				dataout <= 0;
			end
		end
	 end
	 
endmodule
~~~
## Verilog Repair Example
Instruction:
~~~
Correct the Verilog code in the input based on EDA tool feedback in the input
~~~
Input:
~~~
code: module Decoder (d0, d1, d2, d3, d4, d5, d6, d7, x, y, z);\n    input x, y, z;\n    output d0, d1, d2, d3, d4, d5, d6, d7;\n\n    wire x0, y0, z0;\n\n    not(x0, x);\n    not(y0, y);\n    not(z0, z);\n\n    and(d0, x0, y0, z0);\n    and(d1, x0, y0, z);\n    and(d2, x0, y, z0);\n    and(d3, x0, y, z);\n    and(d4, x, y0, z0);\n    and(d5, x, y0, z);\n    and(d6, x, y, z0);\n    and(d7, x, y, z);\n\n\twire our_d, our_e;\n\tassign our_d = d0 && d1;\n\tassign our_e = y || our_d;\n\tassign d1 = our_e;\nendmodule // Decoder\n\n, feedback: 4. Executing CHECK pass (checking for obvious problems).\nChecking module Decoder...\nWarning: multiple conflicting drivers for Decoder.$logic_or$./testdir/Wrong/wrong_gate.v:22$18_Y:\n    port Y[0] of cell $logic_or$./testdir/Wrong/wrong_gate.v:22$18 ($logic_or)\n    port Y[0] of cell $and$./testdir/Wrong/wrong_gate.v:12$4 ($and)\nWarning: found logic loop in module Decoder:\n    cell $logic_and$./testdir/Wrong/wrong_gate.v:21$17 ($logic_and)\n    cell $logic_or$./testdir/Wrong/wrong_gate.v:22$18 ($logic_or)\n    wire $logic_and$./testdir/Wrong/wrong_gate.v:21$17_Y\n    wire $logic_or$./testdir/Wrong/wrong_gate.v:22$18_Y\nFound and reported 2 problems.\n\nWarnings: 2 unique messages, 2 total\nEnd of script. Logfile hash: 85f6811747, CPU: user 0.00s system 0.01s, MEM: 12.50 MB peak\n
~~~
Output:
~~~
The module declares an 'd0' output port without a corresponding driver line in the logic. Delete this port declaration.
The module declares an 'd1' output port without a corresponding driver line in the logic. Delete this port declaration.
The module declares an 'd2' output port without a corresponding driver line in the logic. Delete this port declaration.
The module declares an 'd3' output port without a corresponding driver line in the logic. Delete this port declaration.
The module declares an 'd4' output port without a corresponding driver line in the logic. Delete this port declaration.
The module declares an 'd5' output port without a corresponding driver line in the logic. Delete this port declaration.
The module declares an 'd6' output port without a corresponding driver line in the logic. Delete this port declaration.
The module declares an 'd7' output port without a corresponding driver line in the logic. Delete this port declaration.
The module declares an 'x' input port without a corresponding driver line in the logic. Delete this port declaration.
The module declares an 'y' input port without a corresponding driver line in the logic. Delete this port declaration
~~~

Code: https://github.com/aichipdesign/chipgptft

![alt text](image.png)