初始化项目，由ModelHub XC社区提供模型
Model: changkaiyan/ChipGPT-Llama2-SFT-7B Source: Original Platform
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ModelHub XC
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README.md
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README.md
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---
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tasks:
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- text-generation
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widgets:
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- task: text-generation
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inputs:
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- type: text
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examples:
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- name: 1
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title: 示例1
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inputs:
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- name: text
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data: Act as Verilog Programmer.
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inferencespec:
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cpu: 2
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memory: 8000
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gpu: 0
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gpu_memory: 16000
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model-type:
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- gpt
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domain:
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- nlp
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frameworks:
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- pytorch
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backbone:
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- transformer
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containers:
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metrics:
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- BLEU-4
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- Rouge-L
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license: Apache License 2.0
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finetune-support: True
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language:
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- en
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---
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# Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
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This project use Alpaca Prompt Template to query.
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~~~bash
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cd alpaca-lora
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python generate.py --base_model=../ --lora_weights=../siliconcompiler_peft/
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python generate.py --base_model=../ --lora_weights=../nl2v_peft/
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python generate.py --base_model=../ --lora_weights=../verilogrepair_peft/
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~~~
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## SiliconCompiler Example
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**Instruction**:
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~~~
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Develop a Python script using siliconcompiler to run the IC design flow for the 'full_adder.v' design. Utilize the \"TSMC90\" technology, set the layout density to 30, and the clock period to 15. Specify the core area within a width of 800 and a height of 600. Add a timing constraint for the input signal 'A' to ensure it arrives at the full adder with a maximum delay of 5 units of time. Finally, generate a summary report and display the layout file.
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~~~
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**Output**:
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~~~python
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import siliconcompiler
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def main():
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design = 'full_adder.v'
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technology = 'TSMC90'
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layout_density = '30'
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clock_period = 15
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core_width = 800
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core_height = 600
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input_delay = 5
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chip = siliconcompiler.Chip(design)
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chip.input(design)
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chip.load_target(technology)
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chip.clock('clk', period=clock_period)
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chip.set('constraint', 'input', 'A', 'delay', input_delay)
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chip.set('constraint', 'corearea', [(0, 0), (core_width, core_height)])
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chip.run()
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chip.summary()
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chip.show()
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if __name__ == '__main__':
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main()
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~~~
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## Verilog Generation Example
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Instruction:
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~~~
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Please act as a professional verilog designer.
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Implement a multi-bit MUX synchronizer, data_in will remain constant during the period when data_en is high, and data_en is high for at least 3 B clock cycles. When the value of data_en is high, data can be synchronized. The data change frequency of data_in is very low. The change interval between two adjacent data is at least 10 B clock cycles.
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Module name:
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mux
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Input ports：
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input clk_a ,
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input clk_b ,
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input arstn ,
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input brstn ,
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input [3:0] data_in ,
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input data_en
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Output ports：
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output reg [3:0] dataout
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~~~
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Output:
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~~~verilog
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module mux(
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input clk_a ,
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input clk_b ,
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input arstn ,
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input brstn ,
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input [3:0] data_in ,
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input data_en
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output reg [3:0] dataout
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);
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always @(posedge clk_a or posedge clk_b or posedge arstn or posedge brstn) begin
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if(arstn) begin
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dataout <= 0;
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end
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else begin
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if(data_en) begin
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dataout <= data_in;
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end
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else begin
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dataout <= 0;
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end
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end
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end
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endmodule
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~~~
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## Verilog Repair Example
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Instruction:
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~~~
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Correct the Verilog code in the input based on EDA tool feedback in the input
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~~~
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Input:
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~~~
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code: module Decoder (d0, d1, d2, d3, d4, d5, d6, d7, x, y, z);\n input x, y, z;\n output d0, d1, d2, d3, d4, d5, d6, d7;\n\n wire x0, y0, z0;\n\n not(x0, x);\n not(y0, y);\n not(z0, z);\n\n and(d0, x0, y0, z0);\n and(d1, x0, y0, z);\n and(d2, x0, y, z0);\n and(d3, x0, y, z);\n and(d4, x, y0, z0);\n and(d5, x, y0, z);\n and(d6, x, y, z0);\n and(d7, x, y, z);\n\n\twire our_d, our_e;\n\tassign our_d = d0 && d1;\n\tassign our_e = y || our_d;\n\tassign d1 = our_e;\nendmodule // Decoder\n\n, feedback: 4. Executing CHECK pass (checking for obvious problems).\nChecking module Decoder...\nWarning: multiple conflicting drivers for Decoder.$logic_or$./testdir/Wrong/wrong_gate.v:22$18_Y:\n port Y[0] of cell $logic_or$./testdir/Wrong/wrong_gate.v:22$18 ($logic_or)\n port Y[0] of cell $and$./testdir/Wrong/wrong_gate.v:12$4 ($and)\nWarning: found logic loop in module Decoder:\n cell $logic_and$./testdir/Wrong/wrong_gate.v:21$17 ($logic_and)\n cell $logic_or$./testdir/Wrong/wrong_gate.v:22$18 ($logic_or)\n wire $logic_and$./testdir/Wrong/wrong_gate.v:21$17_Y\n wire $logic_or$./testdir/Wrong/wrong_gate.v:22$18_Y\nFound and reported 2 problems.\n\nWarnings: 2 unique messages, 2 total\nEnd of script. Logfile hash: 85f6811747, CPU: user 0.00s system 0.01s, MEM: 12.50 MB peak\n
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~~~
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Output:
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~~~
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The module declares an 'd0' output port without a corresponding driver line in the logic. Delete this port declaration.
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The module declares an 'd1' output port without a corresponding driver line in the logic. Delete this port declaration.
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The module declares an 'd2' output port without a corresponding driver line in the logic. Delete this port declaration.
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The module declares an 'd3' output port without a corresponding driver line in the logic. Delete this port declaration.
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The module declares an 'd4' output port without a corresponding driver line in the logic. Delete this port declaration.
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The module declares an 'd5' output port without a corresponding driver line in the logic. Delete this port declaration.
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The module declares an 'd6' output port without a corresponding driver line in the logic. Delete this port declaration.
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The module declares an 'd7' output port without a corresponding driver line in the logic. Delete this port declaration.
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The module declares an 'x' input port without a corresponding driver line in the logic. Delete this port declaration.
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The module declares an 'y' input port without a corresponding driver line in the logic. Delete this port declaration
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~~~
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Code: https://github.com/aichipdesign/chipgptft
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