初始化项目,由ModelHub XC社区提供模型

Model: Nellyw888/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb
Source: Original Platform
This commit is contained in:
ModelHub XC
2026-05-31 22:19:26 +08:00
commit f2377b9856
14 changed files with 152323 additions and 0 deletions

1
vocab.json Normal file

File diff suppressed because one or more lines are too long