Nellyw888/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb
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初始化项目，由ModelHub XC社区提供模型 Model: Nellyw888/VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb Source: Original Platform
2026-05-31 22:19:26 +08:00
version https://git-lfs.github.com/spec/v1
oid sha256:85a916179210aedca0de8a2a4b9d6fa40e58d4496ec1bf75b2b8793cbe4e69c3
size 8696
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