Nellyw888/VeriReason-Qwen2.5-1.5b-RTLCoder-Verilog-GRPO-reasoning-tb
1
0
Fork 0
Code Issues Pull Requests Actions Projects Releases Wiki Activity

初始化项目，由ModelHub XC社区提供模型

Browse Source 
Model: Nellyw888/VeriReason-Qwen2.5-1.5b-RTLCoder-Verilog-GRPO-reasoning-tb
Source: Original Platform
This commit is contained in:
ModelHub XC
2026-08-02 08:21:20 +08:00
commit bd30909b41
10 changed files with 304012 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
model-00001-of-00002.safetensors Normal file
View File

@@ -0,0 +1,3 @@
version https://git-lfs.github.com/spec/v1
oid sha256:4586fd45b2fa8e9d8feeae61d77d3a8cf61d67abbc8ccf034009f0f43a5d4998
size 4996670464