Nellyw888/VeriReason-Qwen2.5-1.5b-RTLCoder-Verilog-GRPO-reasoning-tb
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初始化项目，由ModelHub XC社区提供模型 Model: Nellyw888/VeriReason-Qwen2.5-1.5b-RTLCoder-Verilog-GRPO-reasoning-tb Source: Original Platform
2026-08-02 08:21:20 +08:00
version https://git-lfs.github.com/spec/v1
oid sha256:4586fd45b2fa8e9d8feeae61d77d3a8cf61d67abbc8ccf034009f0f43a5d4998
size 4996670464
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