Nellyw888/VeriReason-Qwen2.5-1.5b-RTLCoder-Verilog-GRPO-reasoning-tb
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初始化项目，由ModelHub XC社区提供模型 Model: Nellyw888/VeriReason-Qwen2.5-1.5b-RTLCoder-Verilog-GRPO-reasoning-tb Source: Original Platform
2026-08-02 08:21:20 +08:00
version https://git-lfs.github.com/spec/v1
oid sha256:0fa8555329efb4151fd3a36fe1652e168e27c300aa768e16daaf7cb6bd3d6847
size 1178224960
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