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xc-llm-ascend/vllm_ascend
hwhaokun fb9fdcdbe4 [Feat] enable hierarchical mc2 ops on A2 by default (#5545)
### What this PR does / why we need it?
Previously, it was necessary to set the environment variables
HCCL_INTRA_PCIE_ENABLE=1 and HCCL_INTRA_ROCE_ENABLE=0. This PR enables
hierarchical MC2 operations on A2 by default.
### Does this PR introduce _any_ user-facing change?

### How was this patch tested?


- vLLM version: v0.13.0
- vLLM main:
7157596103

Signed-off-by: hwhaokun <haokun0405@163.com>
2026-01-04 14:44:20 +08:00
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