Qiu e07938047e [UT][PCP&DCP] UT for block_table.py (#5032) ...

## Purpose
This PR add unit test for `compute_slot_mapping` function in
`block_table.py` with various `pcp_size` & `dcp_size` &
`cp_kv_cache_interleave_size`.

## Test Plan
```
pytest tests/ut/worker/test_block_table.py
```
## Test Result
```
==== 3 passed, 2 warnings in 0.20s ====
```
- vLLM version: v0.12.0
- vLLM main:
ad32e3e19c

---------

Signed-off-by: QiuChunshuo <qiuchunshuo@huawei.com>

2026-01-06 11:19:25 +08:00

..

e2e

[Main2Main] Upgrade vllm commit to 0105 (#5595)

2026-01-06 08:44:29 +08:00

ut

[UT][PCP&DCP] UT for block_table.py (#5032)

2026-01-06 11:19:25 +08:00

__init__.py

[SpecDecode] Add spec decode support (#500)

2025-04-17 20:16:32 +08:00