### What this PR does / why we need it?
To support tensorList for dispatch_ffn_combine, to adjust eplb
### Does this PR introduce _any_ user-facing change?
N/A
### How was this patch tested?
Single Operator Testing
- vLLM version: v0.13.0
- vLLM main:
2f4e6548ef
---------
Signed-off-by: lhchg <lhao_cheng@163.com>
Co-authored-by: lihaocheng <lihaosheng1@h-partners.com>
177 lines
5.2 KiB
C++
177 lines
5.2 KiB
C++
#ifndef SYNC_UTIL_HPP
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#define SYNC_UTIL_HPP
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#include "kernel_operator.h"
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#include "const_args.hpp"
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#include "moe_distribute_base.h"
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#ifndef HCCL_COMM
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#include "shmem_api.h"
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#endif
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#define FORCE_INLINE_AICORE inline __attribute__((always_inline)) __aicore__
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template<typename T>
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FORCE_INLINE_AICORE void gm_store(__gm__ T *addr, T val) {
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*((__gm__ T *)addr) = val;
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}
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template<typename T>
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FORCE_INLINE_AICORE T gm_load(__gm__ T *cache) {
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return *((__gm__ T *)cache);
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}
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FORCE_INLINE_AICORE void gm_dcci(__gm__ uint8_t * addr) {
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using namespace AscendC;
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GlobalTensor<uint8_t> global;
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global.SetGlobalBuffer(addr);
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// Important: add hint to avoid dcci being optimized by compiler
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__asm__ __volatile__("");
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DataCacheCleanAndInvalid<uint8_t, CacheLine::SINGLE_CACHE_LINE, DcciDst::CACHELINE_OUT>(global);
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__asm__ __volatile__("");
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}
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FORCE_INLINE_AICORE int32_t gm_signal_wait_until_eq_for_barrier(__gm__ int32_t *sig_addr, int32_t cmp_val) {
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do {
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gm_dcci((__gm__ uint8_t *)sig_addr);
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if (*sig_addr == cmp_val) {
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return *sig_addr;
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}
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// in case when peer pe enters next barrier
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if (*sig_addr == cmp_val + 1) {
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return *sig_addr;
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}
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} while (true);
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// never reach
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return -1;
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}
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FORCE_INLINE_AICORE void gm_signal_wait_until_ne(__gm__ int32_t *sig_addr, int32_t cmp_val) {
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do {
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AscendC::LocalTensor<int32_t> ub;
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ub.address_.logicPos = static_cast<uint8_t>(TPosition::VECIN);
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ub.address_.bufferAddr = 0;
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AscendC::GlobalTensor<int32_t> sig;
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sig.SetGlobalBuffer(sig_addr);
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AscendC::DataCopy(ub, sig, 8);
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AscendC::SetFlag<AscendC::HardEvent::MTE2_S>(EVENT_ID0);
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AscendC::WaitFlag<AscendC::HardEvent::MTE2_S>(EVENT_ID0);
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if (ub(0) != cmp_val) {
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return;
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}
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} while (true);
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return;
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}
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constexpr int32_t MAX_RANK_SIZE = 32;
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class HcclShmem {
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public:
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#ifdef HCCL_COMM // HCCL needs to initialize the HCCL context
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__gm__ HcclOpResParamCustom *WinContext_{nullptr};
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Hccl<HCCL_SERVER_TYPE_AICPU> hccl_;
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size_t m_segmentSize;
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int32_t m_rank;
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int32_t m_rankSize;
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FORCE_INLINE_AICORE
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HcclShmem(){
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auto contextGM0 = AscendC::GetHcclContext<HCCL_GROUP_ID_0>();
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WinContext_ = (__gm__ HcclOpResParamCustom *)contextGM0;
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m_rank = WinContext_->localUsrRankId;
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m_rankSize = WinContext_->rankSize;
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m_segmentSize = WinContext_->winSize;
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}
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FORCE_INLINE_AICORE
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size_t SegmentSize() const {
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return m_segmentSize;
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}
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FORCE_INLINE_AICORE
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int32_t RankSize() const {
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return m_rankSize;
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}
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#endif
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FORCE_INLINE_AICORE
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GM_ADDR operator() () const { // No argument: return local peermem
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#ifdef HCCL_COMM
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return (GM_ADDR)(WinContext_->localWindowsIn);
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#else
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return reinterpret_cast<GM_ADDR>(shmemi_get_state()->heap_base);
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#endif
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}
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FORCE_INLINE_AICORE
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GM_ADDR operator() (int32_t index) const { // With index: return remote peermem base address
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#ifdef HCCL_COMM
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return (GM_ADDR)((index == m_rank) ? WinContext_->localWindowsIn :
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((HcclRankRelationResV2Custom *)(WinContext_->remoteRes[index].nextDevicePtr))->windowsIn);
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#else
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return reinterpret_cast<GM_ADDR>(shmem_ptr(shmemi_get_state()->heap_base, index));
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#endif
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}
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FORCE_INLINE_AICORE
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GM_ADDR operator () (int64_t offset, int32_t rankId) const {
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#ifdef HCCL_COMM
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if (offset < 0 || offset >= m_segmentSize) {
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return nullptr;
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}
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if (rankId < 0 || rankId >= m_rankSize) {
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return nullptr;
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}
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return (GM_ADDR)((rankId == m_rank) ? WinContext_->localWindowsIn :
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((HcclRankRelationResV2Custom *)(WinContext_->remoteRes[rankId].nextDevicePtr))->windowsIn) + offset;
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#else
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return shmem_ptr(shmemi_get_state()->heap_base + offset, rankId);
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#endif
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}
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FORCE_INLINE_AICORE
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~HcclShmem() {
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}
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FORCE_INLINE_AICORE
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void CrossRankSync() {
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uint64_t flag_offset = (m_segmentSize - MB_SIZE) / sizeof(int32_t);
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__gm__ int32_t* sync_counter = (__gm__ int32_t*)(*this)() + flag_offset;
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__gm__ int32_t* sync_base = (__gm__ int32_t*)(*this)() + flag_offset + 2048;
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int count = gm_load(sync_base) + 1;
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int vec_id = AscendC::GetBlockIdx();
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int vec_size = AscendC::GetBlockNum() * AscendC::GetTaskRation();
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for(int i = vec_id; i < m_rankSize; i += vec_size) {
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__gm__ int32_t* sync_remote = (__gm__ int32_t*)((*this)(i)) + flag_offset + m_rank * 16;
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gm_store(sync_remote, count);
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gm_dcci((__gm__ uint8_t*)sync_remote);
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auto sync_check = sync_counter + i * 16;
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gm_signal_wait_until_eq_for_barrier(sync_check, count);
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}
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AscendC::SyncAll<true>();
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gm_store(sync_base, count);
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}
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FORCE_INLINE_AICORE
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__gm__ int32_t* SyncBaseAddr() {
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uint64_t flag_offset = (m_segmentSize - MB_SIZE) / sizeof(int32_t);
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return (__gm__ int32_t*)(*this)() + flag_offset + 2048;
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}
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};
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#endif
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