jiangyunfan1 e56b0017a3 [TEST]Add aisbench log and A2 cases (#3841) ...

### What this PR does / why we need it?
This PR adds 2 more A2 caces which we need to test daily. It also
enhances the logging for aisbench test failures to improve issues
identification
### Does this PR introduce _any_ user-facing change?
No
### How was this patch tested?
By running the test

- vLLM version: v0.11.0rc3
- vLLM main:
https://github.com/vllm-project/vllm/commit/releases/v0.11.1

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Signed-off-by: jiangyunfan1 <jiangyunfan1@h-partners.com>

2025-10-28 23:33:15 +08:00

..

e2e

[TEST]Add aisbench log and A2 cases (#3841)

2025-10-28 23:33:15 +08:00

ut

[feat]dcp pcp support aclgraph (#3731)

2025-10-27 09:58:23 +08:00

__init__.py

[SpecDecode] Add spec decode support (#500)

2025-04-17 20:16:32 +08:00